[PATCH v2 0/7] ARM: mvebu: Enable perf support

[PATCH v2 0/7] ARM: mvebu: Enable perf support

[Maxime Ripard]

Hi,

This patch enables the performance monitoring unit found on the Armada
370, 375, 38x and XP, in order to gain hardware-assisted tracing using
perf.

Due to the way the interrupts are implemented in these SoCs, it
required some additions to the interrupt controller in order to unmask
the PMU interrupts.

While doing so, we reworked the way the PPI are supported, in order to
make the driver both easier to read and to extend.

This has been tested on an Armada XP and an Armada 385, and this serie
depends on the patch "irqchip: armada: Fix chained per-cpu interrupts"
sent previously.

Thanks!
Maxime

Changes from v1:
  - Dropped the mask/unmask refactoring
  - Rebased on top of the v2 of the chained PPI fix

Ezequiel Garcia (5):
  irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N
  irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for
    readability
  ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
  ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC
  ARM: mvebu: Enable perf support in mvebu_v7_defconfig

Maxime Ripard (2):
  irqchip: armada-370-xp: Enable the PMU interrupts
  ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs

 arch/arm/boot/dts/armada-370-xp.dtsi |  5 ++
 arch/arm/boot/dts/armada-375.dtsi    |  5 ++
 arch/arm/boot/dts/armada-38x.dtsi    |  5 ++
 arch/arm/configs/mvebu_v7_defconfig  |  1 +
 drivers/irqchip/irq-armada-370-xp.c  | 88 +++++++++++++++++++++++-------------
 5 files changed, 73 insertions(+), 31 deletions(-)

-- 
2.3.0

[PATCH v2 1/7] irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N

[Maxime Ripard]

From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

The irqchip driver called armada_xp_mpic_smp_cpu_init() when CONFIG_SMP=Y
to initialize some per cpu registers. The function is called on each
CPU by calling it explicitly on the boot CPU and then using a CPU notifier
for the non boot CPUs.

This commit removes the CONFIG_SMP constrain, so the per cpu registers are
also initialized when CONFIG_SMP=N, which is the right thing to do.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 47 ++++++++++++++++++-------------------
 1 file changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 4387dae14e45..b455c876974e 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -308,28 +308,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	return 0;
 }
 
-#ifdef CONFIG_SMP
-static void armada_mpic_send_doorbell(const struct cpumask *mask,
-				      unsigned int irq)
-{
-	int cpu;
-	unsigned long map = 0;
-
-	/* Convert our logical CPU mask into a physical one. */
-	for_each_cpu(cpu, mask)
-		map |= 1 << cpu_logical_map(cpu);
-
-	/*
-	 * Ensure that stores to Normal memory are visible to the
-	 * other CPUs before issuing the IPI.
-	 */
-	dsb();
-
-	/* submit softirq */
-	writel((map << 8) | irq, main_int_base +
-		ARMADA_370_XP_SW_TRIG_INT_OFFS);
-}
-
 static void armada_xp_mpic_smp_cpu_init(void)
 {
 	u32 control;
@@ -352,6 +330,28 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 }
 
+#ifdef CONFIG_SMP
+static void armada_mpic_send_doorbell(const struct cpumask *mask,
+				      unsigned int irq)
+{
+	int cpu;
+	unsigned long map = 0;
+
+	/* Convert our logical CPU mask into a physical one. */
+	for_each_cpu(cpu, mask)
+		map |= 1 << cpu_logical_map(cpu);
+
+	/*
+	 * Ensure that stores to Normal memory are visible to the
+	 * other CPUs before issuing the IPI.
+	 */
+	dsb();
+
+	/* submit softirq */
+	writel((map << 8) | irq, main_int_base +
+		ARMADA_370_XP_SW_TRIG_INT_OFFS);
+}
+
 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
 					 unsigned long action, void *hcpu)
 {
@@ -588,9 +588,8 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 
 	BUG_ON(!armada_370_xp_mpic_domain);
 
-#ifdef CONFIG_SMP
+	/* Setup for the boot CPU */
 	armada_xp_mpic_smp_cpu_init();
-#endif
 
 	armada_370_xp_msi_init(node, main_int_res.start);
 
-- 
2.3.0

[PATCH v2 2/7] irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for readability

[Maxime Ripard]

From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

This commit introduces a helper function is_percpu_irq(), to be used
when interrupts are mapped to decide which ones are set as per CPU.

This change will allow to extend the list of per cpu interrupts in a less
intrusive fashion; also, it makes the code slightly more readable by keeping
a list of the per CPU interrupts.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index b455c876974e..ea57fba263cf 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -77,6 +77,16 @@ static DEFINE_MUTEX(msi_used_lock);
 static phys_addr_t msi_doorbell_addr;
 #endif
 
+static inline bool is_percpu_irq(irq_hw_number_t irq)
+{
+	switch (irq) {
+	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
+		return true;
+	default:
+		return false;
+	}
+}
+
 /*
  * In SMP mode:
  * For shared global interrupts, mask/unmask global enable bit
@@ -86,7 +96,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
+	if (!is_percpu_irq(hwirq))
 		writel(hwirq, main_int_base +
 				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
 	else
@@ -98,7 +108,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
+	if (!is_percpu_irq(hwirq))
 		writel(hwirq, main_int_base +
 				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 	else
@@ -287,14 +297,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 				      unsigned int virq, irq_hw_number_t hw)
 {
 	armada_370_xp_irq_mask(irq_get_irq_data(virq));
-	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
+	if (!is_percpu_irq(hw))
 		writel(hw, per_cpu_int_base +
 			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 	else
 		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
-	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
+	if (is_percpu_irq(hw)) {
 		irq_set_percpu_devid(virq);
 		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 					handle_percpu_devid_irq);
-- 
2.3.0

[PATCH v2 3/7] irqchip: armada-370-xp: Enable the PMU interrupts

[Maxime Ripard]

In order to let the Performance Monitoring Unit interrupts flowing in the MPIC,
we need to unmask these interrupts in the Coherency Fabric Local Interrupt Mask
Register.

Since this register is a CPU-local register, unmasking this interrupt needs to
be done on the boot CPU when the driver initializes, but also on the secondary
CPU when they are brought up.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index ea57fba263cf..b36373c019ba 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -38,6 +38,8 @@
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
+#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
+#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
 
 #define ARMADA_370_XP_INT_CONTROL		(0x00)
 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
@@ -56,6 +58,7 @@
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)
+#define ARMADA_370_XP_FABRIC_IRQ		(3)
 
 #define IPI_DOORBELL_START                      (0)
 #define IPI_DOORBELL_END                        (8)
@@ -81,6 +84,7 @@ static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
 	switch (irq) {
 	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
+	case ARMADA_370_XP_FABRIC_IRQ:
 		return true;
 	default:
 		return false;
@@ -340,6 +344,15 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 }
 
+static void armada_xp_mpic_perf_init(void)
+{
+	unsigned long cpuid = cpu_logical_map(smp_processor_id());
+
+	/* Enable Performance Counter Overflow interrupts */
+	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
+	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
+}
+
 #ifdef CONFIG_SMP
 static void armada_mpic_send_doorbell(const struct cpumask *mask,
 				      unsigned int irq)
@@ -365,8 +378,10 @@ static void armada_mpic_send_doorbell(const struct cpumask *mask,
 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
 					 unsigned long action, void *hcpu)
 {
-	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
+	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
+		armada_xp_mpic_perf_init();
 		armada_xp_mpic_smp_cpu_init();
+	}
 
 	return NOTIFY_OK;
 }
@@ -379,8 +394,10 @@ static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
 static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
 					unsigned long action, void *hcpu)
 {
-	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
+	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
+		armada_xp_mpic_perf_init();
 		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
+	}
 
 	return NOTIFY_OK;
 }
@@ -389,7 +406,6 @@ static struct notifier_block mpic_cascaded_cpu_notifier = {
 	.notifier_call = mpic_cascaded_secondary_init,
 	.priority = 100,
 };
-
 #endif /* CONFIG_SMP */
 
 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
@@ -599,6 +615,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	BUG_ON(!armada_370_xp_mpic_domain);
 
 	/* Setup for the boot CPU */
+	armada_xp_mpic_perf_init();
 	armada_xp_mpic_smp_cpu_init();
 
 	armada_370_xp_msi_init(node, main_int_res.start);
-- 
2.3.0

[PATCH v2 4/7] ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs

[Maxime Ripard]

The Armada 370 and XP SoCs have Cortex-A9 compatible CPUs, and with a
Performance Monitoring Unit.

Enable it so that we can have hardware-assisted perf support.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 8a322ad57e5f..508ceb7c967a 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -73,6 +73,11 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts-extended = <&mpic 3>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <1>;
-- 
2.3.0

[PATCH v2 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC

[Maxime Ripard]

From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available
to be used. This commit enables it in the devicetree.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-375.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index ba3c57e0af72..6c8fb3bcd6ef 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -96,6 +96,11 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts-extended = <&mpic 3>;
+	};
+
 	soc {
 		compatible = "marvell,armada375-mbus", "simple-bus";
 		#address-cells = <2>;
-- 
2.3.0

[PATCH v2 6/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC

[Maxime Ripard]

From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

The Armada 380 and 385 SoCs have a Cortex-A9 CPU, so the PMU is available
to be used. This commit enables it in the devicetree.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 885fcee6580c..7cd95801d844 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -64,6 +64,11 @@
 		ethernet2 = &eth2;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts-extended = <&mpic 3>;
+	};
+
 	soc {
 		compatible = "marvell,armada380-mbus", "simple-bus";
 		#address-cells = <2>;
-- 
2.3.0

[PATCH v2 7/7] ARM: mvebu: Enable perf support in mvebu_v7_defconfig

[Maxime Ripard]

From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

Now that Armada 375/38x have support for the PMU, this commit enables perf
events in the defconfig.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/configs/mvebu_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 73673e95f23c..b53606cdff26 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -5,6 +5,7 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-- 
2.3.0

[PATCH v2 1/7] irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> 
> The irqchip driver called armada_xp_mpic_smp_cpu_init() when CONFIG_SMP=Y
> to initialize some per cpu registers. The function is called on each
> CPU by calling it explicitly on the boot CPU and then using a CPU notifier
> for the non boot CPUs.
> 
> This commit removes the CONFIG_SMP constrain, so the per cpu registers are
> also initialized when CONFIG_SMP=N, which is the right thing to do.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

>  drivers/irqchip/irq-armada-370-xp.c | 47 ++++++++++++++++++-------------------
>  1 file changed, 23 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index 4387dae14e45..b455c876974e 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -308,28 +308,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
>  	return 0;
>  }
>  
> -#ifdef CONFIG_SMP
> -static void armada_mpic_send_doorbell(const struct cpumask *mask,
> -				      unsigned int irq)
> -{
> -	int cpu;
> -	unsigned long map = 0;
> -
> -	/* Convert our logical CPU mask into a physical one. */
> -	for_each_cpu(cpu, mask)
> -		map |= 1 << cpu_logical_map(cpu);
> -
> -	/*
> -	 * Ensure that stores to Normal memory are visible to the
> -	 * other CPUs before issuing the IPI.
> -	 */
> -	dsb();
> -
> -	/* submit softirq */
> -	writel((map << 8) | irq, main_int_base +
> -		ARMADA_370_XP_SW_TRIG_INT_OFFS);
> -}
> -
>  static void armada_xp_mpic_smp_cpu_init(void)
>  {
>  	u32 control;
> @@ -352,6 +330,28 @@ static void armada_xp_mpic_smp_cpu_init(void)
>  	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
>  }
>  
> +#ifdef CONFIG_SMP
> +static void armada_mpic_send_doorbell(const struct cpumask *mask,
> +				      unsigned int irq)
> +{
> +	int cpu;
> +	unsigned long map = 0;
> +
> +	/* Convert our logical CPU mask into a physical one. */
> +	for_each_cpu(cpu, mask)
> +		map |= 1 << cpu_logical_map(cpu);
> +
> +	/*
> +	 * Ensure that stores to Normal memory are visible to the
> +	 * other CPUs before issuing the IPI.
> +	 */
> +	dsb();
> +
> +	/* submit softirq */
> +	writel((map << 8) | irq, main_int_base +
> +		ARMADA_370_XP_SW_TRIG_INT_OFFS);
> +}
> +
>  static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
>  					 unsigned long action, void *hcpu)
>  {
> @@ -588,9 +588,8 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
>  
>  	BUG_ON(!armada_370_xp_mpic_domain);
>  
> -#ifdef CONFIG_SMP
> +	/* Setup for the boot CPU */
>  	armada_xp_mpic_smp_cpu_init();
> -#endif
>  
>  	armada_370_xp_msi_init(node, main_int_res.start);
>  
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 2/7] irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for readability

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> 
> This commit introduces a helper function is_percpu_irq(), to be used
> when interrupts are mapped to decide which ones are set as per CPU.
> 
> This change will allow to extend the list of per cpu interrupts in a less
> intrusive fashion; also, it makes the code slightly more readable by keeping
> a list of the per CPU interrupts.

Eventually the is_percpu_irq will be only
irq < ARMADA_370_XP_MAX_PER_CPU_IRQS

using just a couple of the PER_CPU_IRQ was bogus, but it is not something
new. At least this patch improves the readability so:

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Thanks,

Gregory


> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index b455c876974e..ea57fba263cf 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -77,6 +77,16 @@ static DEFINE_MUTEX(msi_used_lock);
>  static phys_addr_t msi_doorbell_addr;
>  #endif
>  
> +static inline bool is_percpu_irq(irq_hw_number_t irq)
> +{
> +	switch (irq) {
> +	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>  /*
>   * In SMP mode:
>   * For shared global interrupts, mask/unmask global enable bit
> @@ -86,7 +96,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
>  {
>  	irq_hw_number_t hwirq = irqd_to_hwirq(d);
>  
> -	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
> +	if (!is_percpu_irq(hwirq))
>  		writel(hwirq, main_int_base +
>  				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
>  	else
> @@ -98,7 +108,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
>  {
>  	irq_hw_number_t hwirq = irqd_to_hwirq(d);
>  
> -	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
> +	if (!is_percpu_irq(hwirq))
>  		writel(hwirq, main_int_base +
>  				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
>  	else
> @@ -287,14 +297,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
>  				      unsigned int virq, irq_hw_number_t hw)
>  {
>  	armada_370_xp_irq_mask(irq_get_irq_data(virq));
> -	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
> +	if (!is_percpu_irq(hw))
>  		writel(hw, per_cpu_int_base +
>  			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
>  	else
>  		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
>  	irq_set_status_flags(virq, IRQ_LEVEL);
>  
> -	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
> +	if (is_percpu_irq(hw)) {
>  		irq_set_percpu_devid(virq);
>  		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
>  					handle_percpu_devid_irq);
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 3/7] irqchip: armada-370-xp: Enable the PMU interrupts

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> In order to let the Performance Monitoring Unit interrupts flowing in the MPIC,
> we need to unmask these interrupts in the Coherency Fabric Local Interrupt Mask
> Register.
> 
> Since this register is a CPU-local register, unmasking this interrupt needs to
> be done on the boot CPU when the driver initializes, but also on the secondary
> CPU when they are brought up.
> 

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/irqchip/irq-armada-370-xp.c | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index ea57fba263cf..b36373c019ba 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -38,6 +38,8 @@
>  /* Interrupt Controller Registers Map */
>  #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
>  #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
> +#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
> +#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
>  
>  #define ARMADA_370_XP_INT_CONTROL		(0x00)
>  #define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
> @@ -56,6 +58,7 @@
>  #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
>  
>  #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)
> +#define ARMADA_370_XP_FABRIC_IRQ		(3)
>  
>  #define IPI_DOORBELL_START                      (0)
>  #define IPI_DOORBELL_END                        (8)
> @@ -81,6 +84,7 @@ static inline bool is_percpu_irq(irq_hw_number_t irq)
>  {
>  	switch (irq) {
>  	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
> +	case ARMADA_370_XP_FABRIC_IRQ:
>  		return true;
>  	default:
>  		return false;
> @@ -340,6 +344,15 @@ static void armada_xp_mpic_smp_cpu_init(void)
>  	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
>  }
>  
> +static void armada_xp_mpic_perf_init(void)
> +{
> +	unsigned long cpuid = cpu_logical_map(smp_processor_id());
> +
> +	/* Enable Performance Counter Overflow interrupts */
> +	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
> +	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
> +}
> +
>  #ifdef CONFIG_SMP
>  static void armada_mpic_send_doorbell(const struct cpumask *mask,
>  				      unsigned int irq)
> @@ -365,8 +378,10 @@ static void armada_mpic_send_doorbell(const struct cpumask *mask,
>  static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
>  					 unsigned long action, void *hcpu)
>  {
> -	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
> +	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
> +		armada_xp_mpic_perf_init();
>  		armada_xp_mpic_smp_cpu_init();
> +	}
>  
>  	return NOTIFY_OK;
>  }
> @@ -379,8 +394,10 @@ static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
>  static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
>  					unsigned long action, void *hcpu)
>  {
> -	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
> +	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
> +		armada_xp_mpic_perf_init();
>  		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
> +	}
>  
>  	return NOTIFY_OK;
>  }
> @@ -389,7 +406,6 @@ static struct notifier_block mpic_cascaded_cpu_notifier = {
>  	.notifier_call = mpic_cascaded_secondary_init,
>  	.priority = 100,
>  };
> -
>  #endif /* CONFIG_SMP */
>  
>  static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
> @@ -599,6 +615,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
>  	BUG_ON(!armada_370_xp_mpic_domain);
>  
>  	/* Setup for the boot CPU */
> +	armada_xp_mpic_perf_init();
>  	armada_xp_mpic_smp_cpu_init();
>  
>  	armada_370_xp_msi_init(node, main_int_res.start);
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> 
> The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available
> to be used. This commit enables it in the devicetree.

This patch (and the following one) had been intensively disscussed in the first
series sent by Ezequiel. So:


Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory


> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-375.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
> index ba3c57e0af72..6c8fb3bcd6ef 100644
> --- a/arch/arm/boot/dts/armada-375.dtsi
> +++ b/arch/arm/boot/dts/armada-375.dtsi
> @@ -96,6 +96,11 @@
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupts-extended = <&mpic 3>;
> +	};
> +
>  	soc {
>  		compatible = "marvell,armada375-mbus", "simple-bus";
>  		#address-cells = <2>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 6/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> 
> The Armada 380 and 385 SoCs have a Cortex-A9 CPU, so the PMU is available
> to be used. This commit enables it in the devicetree.

This patch (and the previous one) had been intensively discussed in the first
series sent by Ezequiel. So:


Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory


> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-38x.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 885fcee6580c..7cd95801d844 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -64,6 +64,11 @@
>  		ethernet2 = &eth2;
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupts-extended = <&mpic 3>;
> +	};
> +
>  	soc {
>  		compatible = "marvell,armada380-mbus", "simple-bus";
>  		#address-cells = <2>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 4/7] ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> The Armada 370 and XP SoCs have Cortex-A9 compatible CPUs, and with a
> Performance Monitoring Unit.
> 
> Enable it so that we can have hardware-assisted perf support.
> 

I guess the fact, that unlike for the Armada 375 and Armada 38x, the
interrupt controller is not cascaded doesn't change the binding.

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory


> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 8a322ad57e5f..508ceb7c967a 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -73,6 +73,11 @@
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupts-extended = <&mpic 3>;
> +	};
> +
>  	soc {
>  		#address-cells = <2>;
>  		#size-cells = <1>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 7/7] ARM: mvebu: Enable perf support in mvebu_v7_defconfig

[Gregory CLEMENT]

Hi Maxime,

On 03/03/2015 11:43, Maxime Ripard wrote:
> From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> 
> Now that Armada 375/38x have support for the PMU, this commit enables perf
> events in the defconfig.



Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/configs/mvebu_v7_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
> index 73673e95f23c..b53606cdff26 100644
> --- a/arch/arm/configs/mvebu_v7_defconfig
> +++ b/arch/arm/configs/mvebu_v7_defconfig
> @@ -5,6 +5,7 @@ CONFIG_HIGH_RES_TIMERS=y
>  CONFIG_LOG_BUF_SHIFT=14
>  CONFIG_BLK_DEV_INITRD=y
>  CONFIG_EXPERT=y
> +CONFIG_PERF_EVENTS=y
>  CONFIG_SLAB=y
>  CONFIG_MODULES=y
>  CONFIG_MODULE_UNLOAD=y
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 0/7] ARM: mvebu: Enable perf support

[Jason Cooper]

On Tue, Mar 03, 2015 at 11:43:13AM +0100, Maxime Ripard wrote:
...
> Ezequiel Garcia (5):
>   irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N
>   irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for
>     readability
...
> 
> Maxime Ripard (2):
>   irqchip: armada-370-xp: Enable the PMU interrupts
...
>  arch/arm/configs/mvebu_v7_defconfig  |  1 +
>  drivers/irqchip/irq-armada-370-xp.c  | 88 +++++++++++++++++++++++-------------
>  5 files changed, 73 insertions(+), 31 deletions(-)

Patches 1-3 applied to irqchip/mvebu with Gregory's Acks.  Please let me know
if you need to use this as a base.

Depends on the fix in irqchip/urgent.

thx,

Jason.

[PATCH v2 0/7] ARM: mvebu: Enable perf support

[Gregory CLEMENT]

Hi Maxime,


On 03/03/2015 11:43, Maxime Ripard wrote:
> Hi,
> 
> This patch enables the performance monitoring unit found on the Armada
> 370, 375, 38x and XP, in order to gain hardware-assisted tracing using
> perf.
> 
> Due to the way the interrupts are implemented in these SoCs, it
> required some additions to the interrupt controller in order to unmask
> the PMU interrupts.
> 
> While doing so, we reworked the way the PPI are supported, in order to
> make the driver both easier to read and to extend.
> 
> This has been tested on an Armada XP and an Armada 385, and this serie
> depends on the patch "irqchip: armada: Fix chained per-cpu interrupts"
> sent previously.
> 
> Thanks!
> Maxime
> 
> Changes from v1:
>   - Dropped the mask/unmask refactoring
>   - Rebased on top of the v2 of the chained PPI fix
> 
> Ezequiel Garcia (5):
>   irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N
>   irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for
>     readability
>   ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
>   ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC
>   ARM: mvebu: Enable perf support in mvebu_v7_defconfig
> 
> Maxime Ripard (2):
>   irqchip: armada-370-xp: Enable the PMU interrupts
>   ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs
> 
>  arch/arm/boot/dts/armada-370-xp.dtsi |  5 ++
>  arch/arm/boot/dts/armada-375.dtsi    |  5 ++
>  arch/arm/boot/dts/armada-38x.dtsi    |  5 ++
>  arch/arm/configs/mvebu_v7_defconfig  |  1 +
>  drivers/irqchip/irq-armada-370-xp.c  | 88 +++++++++++++++++++++++-------------
>  5 files changed, 73 insertions(+), 31 deletions(-)
> 


Now that patches 1-3 have been applied and are also in linux-next, I applied
patches 4-6 to mvebu/dt and pacth 7 to mvebu/defconfig

I also checked that having only patches 4 to 7 without the 3 first ones
didn't break the build or didn't make the kernel crash.


Thanks,

Gregory


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com