From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro
Date: Mon, 5 Sep 2016 17:11:17 +0100 [thread overview]
Message-ID: <20160905161117.GB27305@leverpostej> (raw)
In-Reply-To: <1472828533-28197-3-git-send-email-catalin.marinas@arm.com>
Hi Catalin,
On Fri, Sep 02, 2016 at 04:02:08PM +0100, Catalin Marinas wrote:
> This patch takes the errata workaround code out of cpu_do_switch_mm into
> a dedicated post_ttbr0_update_workaround macro which will be reused in a
> subsequent patch.
> +/*
> + * Errata workaround post TTBR0_EL1 update.
> + */
> + .macro post_ttbr0_update_workaround, ret = 0
> +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
> + .if \ret
> + ret
> + .endif
> + nop
> + nop
> + nop
> +alternative_else
> + ic iallu
> + dsb nsh
> + isb
> + .if \ret
> + ret
> + .endif
> +alternative_endif
> + .endm
IMO, the ret parameter makes the callers harder to read. Can we leave
the ret up to the caller and suffer the marginal penalty of a few nops
in a slow(ish) path?
We can get rid of them in the !CONFIG_CAVIUM_ERRATUM_27456 case with a
simple ifdef:
.macro post_ttbr0_update_workaround
#ifdef CONFIG_CAVIUM_ERRATUM_27456
alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
nop
nop
nop
alternative_else
ic iallu
dsb nsh
isb
alternative_endif
#endif
.endm
> +
> #endif /* __ASM_ASSEMBLER_H */
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 5bb61de23201..9359659f2559 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -125,17 +125,7 @@ ENTRY(cpu_do_switch_mm)
> bfi x0, x1, #48, #16 // set the ASID
> msr ttbr0_el1, x0 // set TTBR0
> isb
> -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
> - ret
> - nop
> - nop
> - nop
> -alternative_else
> - ic iallu
> - dsb nsh
> - isb
> - ret
> -alternative_endif
> + post_ttbr0_update_workaround ret = 1
+ ret
Thanks,
Mark,
next prev parent reply other threads:[~2016-09-05 16:11 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-02 15:02 [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-09-05 15:38 ` Mark Rutland
2016-09-12 14:52 ` Catalin Marinas
2016-09-12 15:09 ` Mark Rutland
2016-09-12 16:26 ` Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas
2016-09-05 16:11 ` Mark Rutland [this message]
2016-09-02 15:02 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-09-05 17:20 ` Mark Rutland
2016-09-06 10:27 ` Catalin Marinas
2016-09-06 10:45 ` Mark Rutland
2016-09-11 13:55 ` [kernel-hardening] " Ard Biesheuvel
2016-09-12 9:32 ` Catalin Marinas
2016-09-09 17:15 ` Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-09-06 17:31 ` Mark Rutland
2016-09-02 15:02 ` [PATCH v2 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-09-02 15:47 ` Mark Rutland
2016-09-07 23:20 ` [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-09-08 12:51 ` Catalin Marinas
2016-09-08 15:50 ` Kees Cook
2016-09-09 16:31 ` Mark Rutland
2016-09-09 18:24 ` Kees Cook
2016-09-09 23:40 ` [kernel-hardening] " David Brown
2016-09-10 9:51 ` Catalin Marinas
2016-09-10 10:56 ` Ard Biesheuvel
2016-09-11 12:16 ` Catalin Marinas
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