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From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>,  <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
	kthota@nvidia.com, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
	linux-tegra@vger.kernel.org, vidyas@nvidia.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V7 04/15] PCI: dwc: Move config space capability search API
Date: Fri, 17 May 2019 18:08:35 +0530
Message-ID: <20190517123846.3708-5-vidyas@nvidia.com> (raw)
In-Reply-To: <20190517123846.3708-1-vidyas@nvidia.com>

Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Changes since [v6]:
* Exported dw_pcie_find_capability() API

Changes since [v5]:
* None

Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
  to pcie-designware.c file based on Bjorn's comments.

Changes since [v3]:
* Rebased to linux-next top of the tree

Changes since [v2]:
* None

Changes since [v1]:
* Removed dw_pcie_find_next_ext_capability() API from here and made a
  separate patch for that

 .../pci/controller/dwc/pcie-designware-ep.c   | 37 +----------------
 drivers/pci/controller/dwc/pcie-designware.c  | 40 +++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h  |  2 +
 3 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 2bf5a35c0570..65f479250087 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 	__dw_pcie_ep_reset_bar(pci, bar, 0);
 }
 
-static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
-			      u8 cap)
-{
-	u8 cap_id, next_cap_ptr;
-	u16 reg;
-
-	if (!cap_ptr)
-		return 0;
-
-	reg = dw_pcie_readw_dbi(pci, cap_ptr);
-	cap_id = (reg & 0x00ff);
-
-	if (cap_id > PCI_CAP_ID_MAX)
-		return 0;
-
-	if (cap_id == cap)
-		return cap_ptr;
-
-	next_cap_ptr = (reg & 0xff00) >> 8;
-	return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
-}
-
-static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
-{
-	u8 next_cap_ptr;
-	u16 reg;
-
-	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
-	next_cap_ptr = (reg & 0x00ff);
-
-	return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
-}
-
 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
 				   struct pci_epf_header *hdr)
 {
@@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
 		return -ENOMEM;
 	}
-	ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
+	ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
 
-	ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
+	ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
 
 	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
 	if (offset) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 83cdd2ce2486..8f53ce63d17e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -14,6 +14,46 @@
 
 #include "pcie-designware.h"
 
+/*
+ * These APIs are different from standard pci_find_*capability() APIs in the
+ * sense that former can only be used post device enumeration as they require
+ * 'struct pci_dev *' pointer whereas these APIs require 'struct dw_pcie *'
+ * pointer and can be used before link up also.
+ */
+static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
+				  u8 cap)
+{
+	u8 cap_id, next_cap_ptr;
+	u16 reg;
+
+	if (!cap_ptr)
+		return 0;
+
+	reg = dw_pcie_readw_dbi(pci, cap_ptr);
+	cap_id = (reg & 0x00ff);
+
+	if (cap_id > PCI_CAP_ID_MAX)
+		return 0;
+
+	if (cap_id == cap)
+		return cap_ptr;
+
+	next_cap_ptr = (reg & 0xff00) >> 8;
+	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
+{
+	u8 next_cap_ptr;
+	u16 reg;
+
+	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
+	next_cap_ptr = (reg & 0x00ff);
+
+	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 14762e262758..6cb978132469 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -251,6 +251,8 @@ struct dw_pcie {
 #define to_dw_pcie_from_ep(endpoint)   \
 		container_of((endpoint), struct dw_pcie, ep)
 
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
 
-- 
2.17.1


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  parent reply index

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-17 12:38 [PATCH V7 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-05-21 10:27   ` Thierry Reding
2019-05-21 16:47     ` Vidya Sagar
2019-05-21 19:34       ` Vidya Sagar
2019-05-21 19:36       ` Bjorn Helgaas
2019-05-22  8:07         ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-21 10:29   ` Thierry Reding
2019-05-17 12:38 ` Vidya Sagar [this message]
2019-05-21 10:29   ` [PATCH V7 04/15] PCI: dwc: Move config space capability search API Thierry Reding
2019-05-21 21:17   ` Bjorn Helgaas
2019-05-22  8:56     ` Vidya Sagar
2019-05-22 14:02       ` Bjorn Helgaas
2019-05-24 14:46         ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-05-21 10:36   ` Thierry Reding
2019-05-21 17:14     ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-05-21 10:37   ` Thierry Reding
2019-05-24 20:23   ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-05-21 10:38   ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-05-21 10:39   ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-05-21 10:51   ` Thierry Reding
2019-05-21 18:00     ` Vidya Sagar
2019-05-24 20:26   ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-05-21 10:52   ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-17 13:03   ` Ard Biesheuvel
2019-05-17 17:38     ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-21 10:54   ` Thierry Reding
2019-05-21 18:17     ` Vidya Sagar
2019-05-22 13:48       ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-21 11:00   ` Thierry Reding
2019-05-21 19:37     ` Vidya Sagar
2019-05-21 11:00   ` Thierry Reding
2019-05-22  8:59     ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-21 11:41   ` Thierry Reding
2019-05-22 12:05     ` Vidya Sagar
2019-05-22 14:14       ` Thierry Reding
2019-05-24 18:07         ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar

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