* [PATCH v7 1/8] PM / devfreq: Add cpu based scaling support to passive_governor
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator Andrew-sh.Cheng
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, Saravana Kannan, linux-mediatek, Sibi Sankar,
linux-arm-kernel
From: Saravana Kannan <skannan@codeaurora.org>
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure that the
cache is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this patch adds support for cpu based scaling to the
passive governor. This is accomplished by taking the current frequency
of each CPU frequency domain and then adjust the frequency of the cache
(or any devfreq device) based on the frequency of the CPUs. It listens
to CPU frequency transition notifiers to keep itself up to date on the
current CPU frequency.
To decide the frequency of the device, the governor does one of the
following:
* Derives the optimal devfreq device opp from required-opps property of
the parent cpu opp_table.
* Scales the device frequency in proportion to the CPU frequency. So, if
the CPUs are running at their max frequency, the device runs at its
max frequency. If the CPUs are running at their min frequency, the
device runs at its min frequency. It is interpolated for frequencies
in between.
Andrew-sh.Cheng change
dev_pm_opp_xlate_opp to dev_pm_opp_xlate_required_opp devfreq->max_freq
to devfreq->user_min_freq_req.data.freq.qos->min_freq.target_value
for kernel-5.7
Change-Id: I5a55c423823b2c93f38dc2b2cbdd88eeef2e74fd
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/devfreq/Kconfig | 2 +
drivers/devfreq/governor_passive.c | 332 +++++++++++++++++++++++++++++++++++--
include/linux/devfreq.h | 29 +++-
3 files changed, 343 insertions(+), 20 deletions(-)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 37dc40d1fcfb..42b1286e98e6 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -73,6 +73,8 @@ config DEVFREQ_GOV_PASSIVE
device. This governor does not change the frequency by itself
through sysfs entries. The passive governor recommends that
devfreq device uses the OPP table to get the frequency/voltage.
+ Alternatively the governor can also be chosen to scale based on
+ the online CPUs current frequency.
comment "DEVFREQ Drivers"
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 2d67d6c12dce..b9ee3a8504cd 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,103 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
#include <linux/device.h>
#include <linux/devfreq.h>
+#include <linux/slab.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+struct devfreq_cpu_state {
+ unsigned int curr_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+ unsigned int first_cpu;
+ struct device *cpu_dev;
+ struct opp_table *opp_table;
+};
+
+static unsigned long xlate_cpufreq_to_devfreq(struct devfreq_passive_data *data,
+ unsigned int cpu)
+{
+ unsigned int cpu_min_freq, cpu_max_freq, cpu_curr_freq_khz, cpu_percent;
+ unsigned long dev_min_freq, dev_max_freq, dev_max_state;
+
+ struct devfreq_cpu_state *cpu_state = data->cpu_state[cpu];
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ unsigned long *dev_freq_table = devfreq->profile->freq_table;
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+ unsigned long cpu_curr_freq, freq;
+
+ if (!cpu_state || cpu_state->first_cpu != cpu ||
+ !cpu_state->opp_table || !devfreq->opp_table)
+ return 0;
+
+ cpu_curr_freq = cpu_state->curr_freq * 1000;
+ p_opp = devfreq_recommended_opp(cpu_state->cpu_dev, &cpu_curr_freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(cpu_state->opp_table,
+ devfreq->opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (!IS_ERR(opp)) {
+ freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+ goto out;
+ }
+
+ /* Use Interpolation if required opps is not available */
+ cpu_min_freq = cpu_state->min_freq;
+ cpu_max_freq = cpu_state->max_freq;
+ cpu_curr_freq_khz = cpu_state->curr_freq;
+
+ if (dev_freq_table) {
+ /* Get minimum frequency according to sorting order */
+ dev_max_state = dev_freq_table[devfreq->profile->max_state - 1];
+ if (dev_freq_table[0] < dev_max_state) {
+ dev_min_freq = dev_freq_table[0];
+ dev_max_freq = dev_max_state;
+ } else {
+ dev_min_freq = dev_max_state;
+ dev_max_freq = dev_freq_table[0];
+ }
+ } else {
+ dev_min_freq = dev_pm_qos_read_value(devfreq->dev.parent,
+ DEV_PM_QOS_MIN_FREQUENCY);
+ dev_max_freq = dev_pm_qos_read_value(devfreq->dev.parent,
+ DEV_PM_QOS_MAX_FREQUENCY);
+
+ if (dev_max_freq <= dev_min_freq)
+ return 0;
+ }
+ cpu_percent = ((cpu_curr_freq_khz - cpu_min_freq) * 100) / cpu_max_freq - cpu_min_freq;
+ freq = dev_min_freq + mult_frac(dev_max_freq - dev_min_freq, cpu_percent, 100);
+
+out:
+ return freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ unsigned int cpu;
+ unsigned long target_freq = 0;
+
+ for_each_online_cpu(cpu)
+ target_freq = max(target_freq,
+ xlate_cpufreq_to_devfreq(p_data, cpu));
+
+ *freq = target_freq;
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -23,16 +115,6 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
int i, count, ret = 0;
/*
- * If the devfreq device with passive governor has the specific method
- * to determine the next frequency, should use the get_target_freq()
- * of struct devfreq_passive_data.
- */
- if (p_data->get_target_freq) {
- ret = p_data->get_target_freq(devfreq, freq);
- goto out;
- }
-
- /*
* If the parent and passive devfreq device uses the OPP table,
* get the next frequency by using the OPP table.
*/
@@ -102,6 +184,37 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return ret;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
static int update_devfreq_passive(struct devfreq *devfreq, unsigned long freq)
{
int ret;
@@ -156,16 +269,200 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ struct devfreq_cpu_state *cpu_state;
+ struct cpufreq_freqs *cpu_freq = ptr;
+ unsigned int curr_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !cpu_freq ||
+ !data->cpu_state[cpu_freq->policy->cpu])
+ return 0;
+
+ cpu_state = data->cpu_state[cpu_freq->policy->cpu];
+ if (cpu_state->curr_freq == cpu_freq->new)
+ return 0;
+
+ /* Backup current freq and pre-update cpu state freq*/
+ curr_freq = cpu_state->curr_freq;
+ cpu_state->curr_freq = cpu_freq->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = update_devfreq(devfreq);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ cpu_state->curr_freq = curr_freq;
+ dev_err(&devfreq->dev, "Couldn't update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register(struct devfreq_passive_data **p_data)
+{
+ struct devfreq_passive_data *data = *p_data;
+ struct devfreq *devfreq = (struct devfreq *)data->this;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_state *cpu_state;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ get_online_cpus();
+
+ data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "Couldn't register cpufreq notifier.\n");
+ data->nb.notifier_call = NULL;
+ goto out;
+ }
+
+ /* Populate devfreq_cpu_state */
+ for_each_online_cpu(cpu) {
+ if (data->cpu_state[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EINVAL;
+ goto out;
+ } else if (PTR_ERR(policy) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ goto out;
+ } else if (IS_ERR(policy)) {
+ ret = PTR_ERR(policy);
+ dev_err(dev, "Couldn't get the cpufreq_poliy.\n");
+ goto out;
+ }
+
+ cpu_state = kzalloc(sizeof(*cpu_state), GFP_KERNEL);
+ if (!cpu_state) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "Couldn't get cpu device.\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(devfreq->opp_table)) {
+ ret = PTR_ERR(opp_table);
+ goto out;
+ }
+
+ cpu_state->cpu_dev = cpu_dev;
+ cpu_state->opp_table = opp_table;
+ cpu_state->first_cpu = cpumask_first(policy->related_cpus);
+ cpu_state->curr_freq = policy->cur;
+ cpu_state->min_freq = policy->cpuinfo.min_freq;
+ cpu_state->max_freq = policy->cpuinfo.max_freq;
+ data->cpu_state[cpu] = cpu_state;
+
+ cpufreq_cpu_put(policy);
+ }
+
+out:
+ put_online_cpus();
+ if (ret)
+ return ret;
+
+ /* Update devfreq */
+ mutex_lock(&devfreq->lock);
+ ret = update_devfreq(devfreq);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "Couldn't update the frequency.\n");
+
+ return ret;
+}
+
+static int cpufreq_passive_unregister(struct devfreq_passive_data **p_data)
+{
+ struct devfreq_passive_data *data = *p_data;
+ struct devfreq_cpu_state *cpu_state;
+ int cpu;
+
+ if (data->nb.notifier_call)
+ cpufreq_unregister_notifier(&data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+
+ for_each_possible_cpu(cpu) {
+ cpu_state = data->cpu_state[cpu];
+ if (cpu_state) {
+ if (cpu_state->opp_table)
+ dev_pm_opp_put_opp_table(cpu_state->opp_table);
+ kfree(cpu_state);
+ cpu_state = NULL;
+ }
+ }
+
+ return 0;
+}
+
+int register_parent_dev_notifier(struct devfreq_passive_data **p_data)
+{
+ struct notifier_block *nb = &(*p_data)->nb;
+ int ret = 0;
+
+ switch ((*p_data)->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ nb->notifier_call = devfreq_passive_notifier_call;
+ ret = devfreq_register_notifier((struct devfreq *)(*p_data)->parent, nb,
+ DEVFREQ_TRANSITION_NOTIFIER);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = cpufreq_passive_register(p_data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+int unregister_parent_dev_notifier(struct devfreq_passive_data **p_data)
+{
+ int ret = 0;
+
+ switch ((*p_data)->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ WARN_ON(devfreq_unregister_notifier((struct devfreq *)(*p_data)->parent,
+ &(*p_data)->nb,
+ DEVFREQ_TRANSITION_NOTIFIER));
+ break;
+ case CPUFREQ_PARENT_DEV:
+ cpufreq_passive_unregister(p_data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
static int devfreq_passive_event_handler(struct devfreq *devfreq,
unsigned int event, void *data)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
- struct notifier_block *nb = &p_data->nb;
int ret = 0;
- if (!parent)
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV && !parent)
return -EPROBE_DEFER;
switch (event) {
@@ -173,15 +470,14 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
if (!p_data->this)
p_data->this = devfreq;
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ ret = register_parent_dev_notifier(&p_data);
break;
+
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ ret = unregister_parent_dev_notifier(&p_data);
break;
default:
+ ret = -EINVAL;
break;
}
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index a4b19d593151..7e5cf2b60902 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -278,6 +278,25 @@ struct devfreq_simple_ondemand_data {
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
/**
+ * struct devfreq_cpu_state - holds the per-cpu state
+ * @freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @dev: reference to cpu device.
+ * @opp_table: reference to cpu opp table.
+ *
+ * This structure stores the required cpu_state of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_state;
+
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
+/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
* @parent: the devfreq instance of parent device.
@@ -288,13 +307,15 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
+ * @parent_type: parent type of the device
* @this: the devfreq instance of own device.
* @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ * @cpu_state: the state min/max/current frequency of all online cpu's
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
- * initialize the 'this' and 'nb' field because the devfreq core will handle
- * them.
+ * initialize the 'this', 'nb' and 'cpu_state' field because the devfreq core
+ * will handle them.
*/
struct devfreq_passive_data {
/* Should set the devfreq instance of parent device */
@@ -303,9 +324,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_state *cpu_state[NR_CPUS];
};
#endif
--
2.12.5
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 1/8] PM / devfreq: Add cpu based scaling support to passive_governor Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-13 9:39 ` Viresh Kumar
2020-07-10 2:31 ` [PATCH v7 3/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Andrew-sh.Cheng
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
Need to enable regulator,
so that the max/min requested value will be recorded
even it is not applied right away.
Intermediate clock is not always enabled by ccf in different projects,
so cpufreq should enable it by itself.
Change-Id: I9f4c8b1ea793794f5f9cdc65427daad1393f5df8
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 0c98dd08273d..4b479c110cc9 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
ret = PTR_ERR(proc_reg);
goto out_free_resources;
}
+ ret = regulator_enable(proc_reg);
+ if (ret) {
+ pr_warn("enable vproc for cpu%d fail\n", cpu);
+ goto out_free_resources;
+ }
/* Both presence and absence of sram regulator are valid cases. */
sram_reg = regulator_get_exclusive(cpu_dev, "sram");
@@ -368,13 +373,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
goto out_free_resources;
}
+ ret = clk_prepare_enable(cpu_clk);
+ if (ret)
+ goto out_free_opp_table;
+
+ ret = clk_prepare_enable(inter_clk);
+ if (ret)
+ goto out_disable_mux_clock;
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
if (IS_ERR(opp)) {
pr_err("failed to get intermediate opp for cpu%d\n", cpu);
ret = PTR_ERR(opp);
- goto out_free_opp_table;
+ goto out_disable_inter_clock;
}
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
@@ -393,6 +406,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
return 0;
+out_disable_inter_clock:
+ clk_disable_unprepare(inter_clk);
+
+out_disable_mux_clock:
+ clk_disable_unprepare(cpu_clk);
+
out_free_opp_table:
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
@@ -411,14 +430,20 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
{
- if (!IS_ERR(info->proc_reg))
+ if (!IS_ERR(info->proc_reg)) {
+ regulator_disable(info->proc_reg);
regulator_put(info->proc_reg);
+ }
if (!IS_ERR(info->sram_reg))
regulator_put(info->sram_reg);
- if (!IS_ERR(info->cpu_clk))
+ if (!IS_ERR(info->cpu_clk)) {
+ clk_disable_unprepare(info->cpu_clk);
clk_put(info->cpu_clk);
- if (!IS_ERR(info->inter_clk))
+ }
+ if (!IS_ERR(info->inter_clk)) {
+ clk_disable_unprepare(info->inter_clk);
clk_put(info->inter_clk);
+ }
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
}
--
2.12.5
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator
2020-07-10 2:31 ` [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator Andrew-sh.Cheng
@ 2020-07-13 9:39 ` Viresh Kumar
2020-07-14 13:18 ` andrew-sh.cheng
0 siblings, 1 reply; 15+ messages in thread
From: Viresh Kumar @ 2020-07-13 9:39 UTC (permalink / raw)
To: Andrew-sh.Cheng
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Mark Brown, Rafael J. Wysocki, Liam Girdwood,
Rob Herring, linux-kernel, Chanwoo Choi, Kyungmin Park,
MyungJoo Ham, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On 10-07-20, 10:31, Andrew-sh.Cheng wrote:
> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
>
> Need to enable regulator,
> so that the max/min requested value will be recorded
> even it is not applied right away.
>
> Intermediate clock is not always enabled by ccf in different projects,
> so cpufreq should enable it by itself.
>
> Change-Id: I9f4c8b1ea793794f5f9cdc65427daad1393f5df8
You are on V7 right now, these should have been gone long back.
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++----
> 1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index 0c98dd08273d..4b479c110cc9 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> ret = PTR_ERR(proc_reg);
> goto out_free_resources;
> }
> + ret = regulator_enable(proc_reg);
> + if (ret) {
> + pr_warn("enable vproc for cpu%d fail\n", cpu);
> + goto out_free_resources;
> + }
This is already done by the OPP core now.
--
viresh
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator
2020-07-13 9:39 ` Viresh Kumar
@ 2020-07-14 13:18 ` andrew-sh.cheng
2020-07-15 3:38 ` Viresh Kumar
0 siblings, 1 reply; 15+ messages in thread
From: andrew-sh.cheng @ 2020-07-14 13:18 UTC (permalink / raw)
To: Viresh Kumar
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Mark Brown, Rafael J. Wysocki, Liam Girdwood,
Rob Herring, linux-kernel, Chanwoo Choi, Kyungmin Park,
MyungJoo Ham, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On Mon, 2020-07-13 at 15:09 +0530, Viresh Kumar wrote:
> On 10-07-20, 10:31, Andrew-sh.Cheng wrote:
> > From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
> >
> > Need to enable regulator,
> > so that the max/min requested value will be recorded
> > even it is not applied right away.
> >
> > Intermediate clock is not always enabled by ccf in different projects,
> > so cpufreq should enable it by itself.
> >
> > Change-Id: I9f4c8b1ea793794f5f9cdc65427daad1393f5df8
>
> You are on V7 right now, these should have been gone long back.
Hi Viresh,
Sorry for forgetting to remove the change-ID message.
>
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++----
> > 1 file changed, 29 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> > index 0c98dd08273d..4b479c110cc9 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> > ret = PTR_ERR(proc_reg);
> > goto out_free_resources;
> > }
> > + ret = regulator_enable(proc_reg);
> > + if (ret) {
> > + pr_warn("enable vproc for cpu%d fail\n", cpu);
> > + goto out_free_resources;
> > + }
>
> This is already done by the OPP core now.
Do you mean I can use dev_pm_opp_set_regulators() and
dev_pm_opp_set_rate() to do dvfs?
Due to mediatek-cpufreq may change Vproc and Vsram by special flow, that
is not suitable.
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator
2020-07-14 13:18 ` andrew-sh.cheng
@ 2020-07-15 3:38 ` Viresh Kumar
0 siblings, 0 replies; 15+ messages in thread
From: Viresh Kumar @ 2020-07-15 3:38 UTC (permalink / raw)
To: andrew-sh.cheng
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Mark Brown, Rafael J. Wysocki, Liam Girdwood,
Rob Herring, linux-kernel, Chanwoo Choi, Kyungmin Park,
MyungJoo Ham, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On 14-07-20, 21:18, andrew-sh.cheng wrote:
> On Mon, 2020-07-13 at 15:09 +0530, Viresh Kumar wrote:
> > On 10-07-20, 10:31, Andrew-sh.Cheng wrote:
> > > From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
> > >
> > > Need to enable regulator,
> > > so that the max/min requested value will be recorded
> > > even it is not applied right away.
> > >
> > > Intermediate clock is not always enabled by ccf in different projects,
> > > so cpufreq should enable it by itself.
> > >
> > > Change-Id: I9f4c8b1ea793794f5f9cdc65427daad1393f5df8
> >
> > You are on V7 right now, these should have been gone long back.
>
> Hi Viresh,
> Sorry for forgetting to remove the change-ID message.
>
> >
> > > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > > ---
> > > drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++----
> > > 1 file changed, 29 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> > > index 0c98dd08273d..4b479c110cc9 100644
> > > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > > @@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> > > ret = PTR_ERR(proc_reg);
> > > goto out_free_resources;
> > > }
> > > + ret = regulator_enable(proc_reg);
> > > + if (ret) {
> > > + pr_warn("enable vproc for cpu%d fail\n", cpu);
> > > + goto out_free_resources;
> > > + }
> >
> > This is already done by the OPP core now.
>
> Do you mean I can use dev_pm_opp_set_regulators() and
> dev_pm_opp_set_rate() to do dvfs?
> Due to mediatek-cpufreq may change Vproc and Vsram by special flow, that
> is not suitable.
Sorry about that. I completely missed that you aren't using
dev_pm_opp_set_rate().
--
viresh
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v7 3/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 1/8] PM / devfreq: Add cpu based scaling support to passive_governor Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 4/8] devfreq: add mediatek " Andrew-sh.Cheng
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
This adds dt-binding documentation of cci devfreq
for Mediatek MT8183 SoC platform.
Change-Id: Ibec52fd49f1a56fa3b04ad95fd5268a5a31be865
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
.../devicetree/bindings/devfreq/mt8183-cci.yaml | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
new file mode 100644
index 000000000000..a7341fd94097
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/mt8183-cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CCI_DEVFREQ driver for MT8183.
+
+maintainers:
+ - Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
+
+description: |
+ This module is used to create CCI DEVFREQ.
+ The performance will depend on both CCI frequency and CPU frequency.
+ For MT8183, CCI co-buck with Little core.
+ Contain CCI opp table for voltage and frequency scaling.
+
+properties:
+ compatible:
+ const: "mediatek,mt8183-cci"
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: "cci"
+
+ operating-points-v2: true
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator that provides the supply voltage.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - proc-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
+
--
2.12.5
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v7 4/8] devfreq: add mediatek cci devfreq
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
` (2 preceding siblings ...)
2020-07-10 2:31 ` [PATCH v7 3/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-10 6:43 ` andrew-sh.cheng
2020-07-10 2:31 ` [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled Andrew-sh.Cheng
` (3 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
This adds a devfreq driver for the Cache Coherent Interconnect (CCI)
of the Mediatek MT8183.
On the MT8183 the CCI is supplied by the same regulator as the LITTLE
cores. The driver is notified when the regulator voltage changes
(driven by cpufreq) and adjusts the CCI frequency to the maximum
possible value.
Change-Id: I3d54ede336418e76df5d316064b6c3857a9f1075
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/devfreq/Kconfig | 10 ++
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mt8183-cci-devfreq.c | 198 +++++++++++++++++++++++++++++++++++
3 files changed, 209 insertions(+)
create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 42b1286e98e6..109aab7ea45b 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -111,6 +111,16 @@ config ARM_IMX8M_DDRC_DEVFREQ
This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
adjusting DRAM frequency.
+config ARM_MT8183_CCI_DEVFREQ
+ tristate "MT8183 CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ
+ help
+ This adds a devfreq driver for Cache Coherent Interconnect
+ of Mediatek MT8183, which is shared the same regulator
+ with cpu cluster.
+ It can track buck voltage and update a proper CCI frequency.
+ Use notification to get regulator status.
+
config ARM_TEGRA_DEVFREQ
tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 3ca1ad0ecb97..78733ff6fa5d 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
new file mode 100644
index 000000000000..62d02464a34b
--- /dev/null
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+
+ * Author: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/time.h>
+
+#define MAX_VOLT_LIMIT (1150000)
+
+struct cci_devfreq {
+ struct devfreq *devfreq;
+ struct regulator *cpu_reg;
+ struct clk *cci_clk;
+ int old_vproc;
+ unsigned long old_freq;
+};
+
+static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
+{
+ int ret;
+
+ ret = regulator_set_voltage(cci_df->cpu_reg, vproc,
+ MAX_VOLT_LIMIT);
+ if (!ret)
+ cci_df->old_vproc = vproc;
+ return ret;
+}
+
+static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ int ret;
+ struct cci_devfreq *cci_df = dev_get_drvdata(dev);
+ struct dev_pm_opp *opp;
+ unsigned long opp_rate, opp_voltage, old_voltage;
+
+ if (!cci_df)
+ return -EINVAL;
+
+ if (cci_df->old_freq == *freq)
+ return 0;
+
+ opp_rate = *freq;
+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+ opp_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ old_voltage = cci_df->old_vproc;
+ if (old_voltage == 0)
+ old_voltage = regulator_get_voltage(cci_df->cpu_reg);
+
+ // scale up: set voltage first then freq
+ if (opp_voltage > old_voltage) {
+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
+ if (ret) {
+ pr_err("cci: failed to scale up voltage\n");
+ return ret;
+ }
+ }
+
+ ret = clk_set_rate(cci_df->cci_clk, *freq);
+ if (ret) {
+ pr_err("%s: failed cci to set rate: %d\n", __func__,
+ ret);
+ mtk_cci_set_voltage(cci_df, old_voltage);
+ return ret;
+ }
+
+ // scale down: set freq first then voltage
+ if (opp_voltage < old_voltage) {
+ ret = mtk_cci_set_voltage(cci_df, opp_voltage);
+ if (ret) {
+ pr_err("cci: failed to scale down voltage\n");
+ clk_set_rate(cci_df->cci_clk, cci_df->old_freq);
+ return ret;
+ }
+ }
+
+ cci_df->old_freq = *freq;
+
+ return 0;
+}
+
+static struct devfreq_dev_profile cci_devfreq_profile = {
+ .target = mtk_cci_devfreq_target,
+};
+
+static int mtk_cci_devfreq_probe(struct platform_device *pdev)
+{
+ struct device *cci_dev = &pdev->dev;
+ struct cci_devfreq *cci_df;
+ struct devfreq_passive_data *passive_data;
+ int ret;
+
+ cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
+ if (!cci_df)
+ return -ENOMEM;
+
+ cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
+ ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get clock for CCI: %d\n",
+ ret);
+ return ret;
+ }
+ cci_df->cpu_reg = devm_regulator_get_optional(cci_dev, "proc");
+ ret = PTR_ERR_OR_ZERO(cci_df->cpu_reg);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
+ ret);
+ return ret;
+ }
+ ret = regulator_enable(cci_df->cpu_reg);
+ if (ret) {
+ dev_err(cci_dev, "enable buck for cci fail\n");
+ return ret;
+ }
+
+ ret = dev_pm_opp_of_add_table(cci_dev);
+ if (ret) {
+ dev_err(cci_dev, "Fail to get OPP table for CCI: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, cci_df);
+
+ passive_data = devm_kzalloc(cci_dev, sizeof(*passive_data), GFP_KERNEL);
+ if (!passive_data) {
+ ret = -ENOMEM;
+ goto err_opp;
+ }
+
+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
+
+ cci_df->devfreq = devm_devfreq_add_device(cci_dev,
+ &cci_devfreq_profile,
+ DEVFREQ_GOV_PASSIVE,
+ passive_data);
+ if (IS_ERR(cci_df->devfreq)) {
+ ret = PTR_ERR(cci_df->devfreq);
+ dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret);
+ goto err_opp;
+ }
+
+ return 0;
+
+err_opp:
+ dev_pm_opp_of_remove_table(cci_dev);
+ return ret;
+}
+
+static int mtk_cci_devfreq_remove(struct platform_device *pdev)
+{
+ struct device *cci_dev = &pdev->dev;
+ struct cci_devfreq *cci_df;
+ struct notifier_block *opp_nb;
+
+ cci_df = platform_get_drvdata(pdev);
+ opp_nb = &cci_df->opp_nb;
+
+ dev_pm_opp_unregister_notifier(cci_dev, opp_nb);
+ dev_pm_opp_of_remove_table(cci_dev);
+ regulator_disable(cci_df->cpu_reg);
+
+ return 0;
+}
+
+static const __maybe_unused struct of_device_id
+ mediatek_cci_of_match[] = {
+ { .compatible = "mediatek,mt8183-cci" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mediatek_cci_of_match);
+
+static struct platform_driver cci_devfreq_driver = {
+ .probe = mtk_cci_devfreq_probe,
+ .remove = mtk_cci_devfreq_remove,
+ .driver = {
+ .name = "mediatek-cci-devfreq",
+ .of_match_table = of_match_ptr(mediatek_cci_of_match),
+ },
+};
+
+module_platform_driver(cci_devfreq_driver);
+
+MODULE_DESCRIPTION("Mediatek CCI devfreq driver");
+MODULE_AUTHOR("Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.12.5
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v7 4/8] devfreq: add mediatek cci devfreq
2020-07-10 2:31 ` [PATCH v7 4/8] devfreq: add mediatek " Andrew-sh.Cheng
@ 2020-07-10 6:43 ` andrew-sh.cheng
0 siblings, 0 replies; 15+ messages in thread
From: andrew-sh.cheng @ 2020-07-10 6:43 UTC (permalink / raw)
To: MyungJoo Ham
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Viresh Kumar, Mark Brown, Rafael J. Wysocki,
Liam Girdwood, linux-kernel, Chanwoo Choi, Kyungmin Park,
Rob Herring, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On Fri, 2020-07-10 at 10:31 +0800, Andrew-sh.Cheng wrote:
> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
>
> This adds a devfreq driver for the Cache Coherent Interconnect (CCI)
> of the Mediatek MT8183.
>
Hi Chanwoo Choi~
Due to my mail system crash, I couldn't find your mail to reply your
suggestion at patch version-6.
I reply at here.
> On the MT8183 the CCI is supplied by the same regulator as the LITTLE
> cores. The driver is notified when the regulator voltage changes
> (driven by cpufreq) and adjusts the CCI frequency to the maximum
> possible value.
>
> Change-Id: I3d54ede336418e76df5d316064b6c3857a9f1075
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> ---
> drivers/devfreq/Kconfig | 10 ++
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mt8183-cci-devfreq.c | 198 +++++++++++++++++++++++++++++++++++
> 3 files changed, 209 insertions(+)
> create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 42b1286e98e6..109aab7ea45b 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -111,6 +111,16 @@ config ARM_IMX8M_DDRC_DEVFREQ
> This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
> adjusting DRAM frequency.
>
> +config ARM_MT8183_CCI_DEVFREQ
> + tristate "MT8183 CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ
> + help
> + This adds a devfreq driver for Cache Coherent Interconnect
> + of Mediatek MT8183, which is shared the same regulator
> + with cpu cluster.
> + It can track buck voltage and update a proper CCI frequency.
> + Use notification to get regulator status.
> +
> config ARM_TEGRA_DEVFREQ
> tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
> depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 3ca1ad0ecb97..78733ff6fa5d 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o
> diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
> new file mode 100644
> index 000000000000..62d02464a34b
> --- /dev/null
> +++ b/drivers/devfreq/mt8183-cci-devfreq.c
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> +
> + * Author: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/time.h>
> +
> +#define MAX_VOLT_LIMIT (1150000)
> +
> +struct cci_devfreq {
> + struct devfreq *devfreq;
> + struct regulator *cpu_reg;
> + struct clk *cci_clk;
> + int old_vproc;
> + unsigned long old_freq;
> +};
> +
> +static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
> +{
> + int ret;
> +
> + ret = regulator_set_voltage(cci_df->cpu_reg, vproc,
> + MAX_VOLT_LIMIT);
> + if (!ret)
> + cci_df->old_vproc = vproc;
> + return ret;
> +}
> +
> +static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
> + u32 flags)
> +{
> + int ret;
> + struct cci_devfreq *cci_df = dev_get_drvdata(dev);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate, opp_voltage, old_voltage;
> +
> + if (!cci_df)
> + return -EINVAL;
> +
> + if (cci_df->old_freq == *freq)
> + return 0;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + opp_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + old_voltage = cci_df->old_vproc;
> + if (old_voltage == 0)
> + old_voltage = regulator_get_voltage(cci_df->cpu_reg);
> +
> + // scale up: set voltage first then freq
> + if (opp_voltage > old_voltage) {
> + ret = mtk_cci_set_voltage(cci_df, opp_voltage);
> + if (ret) {
> + pr_err("cci: failed to scale up voltage\n");
> + return ret;
> + }
> + }
> +
> + ret = clk_set_rate(cci_df->cci_clk, *freq);
> + if (ret) {
> + pr_err("%s: failed cci to set rate: %d\n", __func__,
> + ret);
> + mtk_cci_set_voltage(cci_df, old_voltage);
> + return ret;
> + }
> +
> + // scale down: set freq first then voltage
> + if (opp_voltage < old_voltage) {
> + ret = mtk_cci_set_voltage(cci_df, opp_voltage);
> + if (ret) {
> + pr_err("cci: failed to scale down voltage\n");
> + clk_set_rate(cci_df->cci_clk, cci_df->old_freq);
> + return ret;
> + }
> + }
> +
When notified by OPP_EVENT_ADJUST_VOLTAGE, I need to set voltage, even
the freqeuncy not chagne.
I didn't use dev_pm_opp_set_regulators() and dev_pm_opp_set_rate() to
change cci ratio at this version.
> + cci_df->old_freq = *freq;
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile cci_devfreq_profile = {
> + .target = mtk_cci_devfreq_target,
I didn't add .exit to do dev_pm_opp_of_remove_table(), this will be
called at driver.remove.
> +};
> +
> +static int mtk_cci_devfreq_probe(struct platform_device *pdev)
> +{
> + struct device *cci_dev = &pdev->dev;
> + struct cci_devfreq *cci_df;
> + struct devfreq_passive_data *passive_data;
> + int ret;
> +
> + cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
> + if (!cci_df)
> + return -ENOMEM;
> +
> + cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
> + ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(cci_dev, "failed to get clock for CCI: %d\n",
> + ret);
> + return ret;
> + }
> + cci_df->cpu_reg = devm_regulator_get_optional(cci_dev, "proc");
> + ret = PTR_ERR_OR_ZERO(cci_df->cpu_reg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
> + ret);
> + return ret;
> + }
> + ret = regulator_enable(cci_df->cpu_reg);
> + if (ret) {
> + dev_err(cci_dev, "enable buck for cci fail\n");
> + return ret;
> + }
> +
> + ret = dev_pm_opp_of_add_table(cci_dev);
> + if (ret) {
> + dev_err(cci_dev, "Fail to get OPP table for CCI: %d\n", ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, cci_df);
> +
> + passive_data = devm_kzalloc(cci_dev, sizeof(*passive_data), GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto err_opp;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> +
> + cci_df->devfreq = devm_devfreq_add_device(cci_dev,
> + &cci_devfreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(cci_df->devfreq)) {
> + ret = PTR_ERR(cci_df->devfreq);
> + dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret);
> + goto err_opp;
> + }
> +
> + return 0;
> +
> +err_opp:
> + dev_pm_opp_of_remove_table(cci_dev);
> + return ret;
> +}
> +
> +static int mtk_cci_devfreq_remove(struct platform_device *pdev)
> +{
> + struct device *cci_dev = &pdev->dev;
> + struct cci_devfreq *cci_df;
> + struct notifier_block *opp_nb;
> +
> + cci_df = platform_get_drvdata(pdev);
> + opp_nb = &cci_df->opp_nb;
> +
> + dev_pm_opp_unregister_notifier(cci_dev, opp_nb);
I understand what you mean when I type this reply...
I will move it to to patch "cci devfreq register opp notification for
SVS support" next time.
> + dev_pm_opp_of_remove_table(cci_dev);
> + regulator_disable(cci_df->cpu_reg);
> +
> + return 0;
> +}
> +
> +static const __maybe_unused struct of_device_id
> + mediatek_cci_of_match[] = {
Actually, I don't quite understand when to us __maybe_unused
This is a suggestion from patch version 2.
https://patchwork.kernel.org/patch/10876449/
Please give me some advice.
Thank you.
> + { .compatible = "mediatek,mt8183-cci" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mediatek_cci_of_match);
> +
> +static struct platform_driver cci_devfreq_driver = {
> + .probe = mtk_cci_devfreq_probe,
> + .remove = mtk_cci_devfreq_remove,
> + .driver = {
> + .name = "mediatek-cci-devfreq",
> + .of_match_table = of_match_ptr(mediatek_cci_of_match),
> + },
> +};
> +
> +module_platform_driver(cci_devfreq_driver);
> +
> +MODULE_DESCRIPTION("Mediatek CCI devfreq driver");
> +MODULE_AUTHOR("Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
` (3 preceding siblings ...)
2020-07-10 2:31 ` [PATCH v7 4/8] devfreq: add mediatek " Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-13 9:42 ` Viresh Kumar
2020-07-10 2:31 ` [PATCH v7 6/8] cpufreq: mediatek: add opp notification for SVS support Andrew-sh.Cheng
` (2 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
Modify dev_pm_opp_get_freq() to return freqeuncy
even this opp item is not available.
So that we can get the information of disable opp items.
Change-Id: I54dacf13050397f5080ccdb8b07d6220e7461e4e
CR-Id:
Feature:
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/opp/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index eed42d6b2e6b..5213e0462382 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -118,7 +118,7 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_get_voltage);
*/
unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp)
{
- if (IS_ERR_OR_NULL(opp) || !opp->available) {
+ if (IS_ERR_OR_NULL(opp)) {
pr_err("%s: Invalid parameters\n", __func__);
return 0;
}
--
2.12.5
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled
2020-07-10 2:31 ` [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled Andrew-sh.Cheng
@ 2020-07-13 9:42 ` Viresh Kumar
2020-07-16 11:28 ` andrew-sh.cheng
0 siblings, 1 reply; 15+ messages in thread
From: Viresh Kumar @ 2020-07-13 9:42 UTC (permalink / raw)
To: Andrew-sh.Cheng
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Mark Brown, Rafael J. Wysocki, Liam Girdwood,
Rob Herring, linux-kernel, Chanwoo Choi, Kyungmin Park,
MyungJoo Ham, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On 10-07-20, 10:31, Andrew-sh.Cheng wrote:
> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
>
> Modify dev_pm_opp_get_freq() to return freqeuncy
> even this opp item is not available.
> So that we can get the information of disable opp items.
>
> Change-Id: I54dacf13050397f5080ccdb8b07d6220e7461e4e
> CR-Id:
> Feature:
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> ---
> drivers/opp/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/opp/core.c b/drivers/opp/core.c
> index eed42d6b2e6b..5213e0462382 100644
> --- a/drivers/opp/core.c
> +++ b/drivers/opp/core.c
> @@ -118,7 +118,7 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_get_voltage);
> */
> unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp)
> {
> - if (IS_ERR_OR_NULL(opp) || !opp->available) {
> + if (IS_ERR_OR_NULL(opp)) {
> pr_err("%s: Invalid parameters\n", __func__);
> return 0;
> }
Please cleanup this patch for all the extra stuff that isn't required mainline
and send it again to me separately from this series.
--
viresh
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled
2020-07-13 9:42 ` Viresh Kumar
@ 2020-07-16 11:28 ` andrew-sh.cheng
0 siblings, 0 replies; 15+ messages in thread
From: andrew-sh.cheng @ 2020-07-16 11:28 UTC (permalink / raw)
To: Viresh Kumar
Cc: Mark Rutland, Nishanth Menon, srv_heupstream, linux-pm,
Stephen Boyd, Mark Brown, Rafael J. Wysocki, Liam Girdwood,
Rob Herring, linux-kernel, Chanwoo Choi, Kyungmin Park,
MyungJoo Ham, linux-mediatek, linux-arm-kernel, Matthias Brugger,
devicetree
On Mon, 2020-07-13 at 15:12 +0530, Viresh Kumar wrote:
> On 10-07-20, 10:31, Andrew-sh.Cheng wrote:
> > From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
> >
> > Modify dev_pm_opp_get_freq() to return freqeuncy
> > even this opp item is not available.
> > So that we can get the information of disable opp items.
> >
> > Change-Id: I54dacf13050397f5080ccdb8b07d6220e7461e4e
> > CR-Id:
> > Feature:
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > ---
> > drivers/opp/core.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/opp/core.c b/drivers/opp/core.c
> > index eed42d6b2e6b..5213e0462382 100644
> > --- a/drivers/opp/core.c
> > +++ b/drivers/opp/core.c
> > @@ -118,7 +118,7 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_get_voltage);
> > */
> > unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp)
> > {
> > - if (IS_ERR_OR_NULL(opp) || !opp->available) {
> > + if (IS_ERR_OR_NULL(opp)) {
> > pr_err("%s: Invalid parameters\n", __func__);
> > return 0;
> > }
>
> Please cleanup this patch for all the extra stuff that isn't required mainline
> and send it again to me separately from this series.
Hi Viresh~
I just resend this single patch to
--to="Viresh Kumar <viresh.kumar@linaro.org>"
--cc=srv_heupstream@mediatek.com
Please help check.
Thank you.
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v7 6/8] cpufreq: mediatek: add opp notification for SVS support
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
` (4 preceding siblings ...)
2020-07-10 2:31 ` [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 7/8] devfreq: mediatek: cci devfreq register " Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 8/8] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183 Andrew-sh.Cheng
7 siblings, 0 replies; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
cpufreq should listen opp notification and do proper actions
when receiving disable and voltage adjustment events,
which are triggered when SVS is enabled.
Change-Id: Icf7807fdebc312dfcea4c98487fe4f79a08459ce
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++++++++++++++++++++++++++--
1 file changed, 85 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 4b479c110cc9..71395ab87ac7 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -42,6 +42,11 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ struct mutex lock; /* avoid notify and policy race condition */
+ struct notifier_block opp_nb;
+ int opp_cpu;
+ unsigned long opp_freq;
+ int old_vproc;
};
static LIST_HEAD(dvfs_info_list);
@@ -192,11 +197,16 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
{
+ int ret;
+
if (info->need_voltage_tracking)
- return mtk_cpufreq_voltage_tracking(info, vproc);
+ ret = mtk_cpufreq_voltage_tracking(info, vproc);
else
- return regulator_set_voltage(info->proc_reg, vproc,
- vproc + VOLT_TOL);
+ ret = regulator_set_voltage(info->proc_reg, vproc,
+ MAX_VOLT_LIMIT);
+ if (!ret)
+ info->old_vproc = vproc;
+ return ret;
}
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
@@ -214,7 +224,9 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
inter_vproc = info->intermediate_voltage;
old_freq_hz = clk_get_rate(cpu_clk);
- old_vproc = regulator_get_voltage(info->proc_reg);
+ old_vproc = info->old_vproc;
+ if (old_vproc == 0)
+ old_vproc = regulator_get_voltage(info->proc_reg);
if (old_vproc < 0) {
pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
return old_vproc;
@@ -231,6 +243,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_lock(&info->lock);
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -242,6 +255,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pr_err("cpu%d: failed to scale up voltage!\n",
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
}
@@ -253,6 +267,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -263,6 +278,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -273,6 +289,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -288,15 +305,69 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, old_freq_hz);
clk_set_parent(cpu_clk, armpll);
+ mutex_unlock(&info->lock);
return ret;
}
}
+ info->opp_freq = freq_hz;
+ mutex_unlock(&info->lock);
+
return 0;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *new_opp;
+ struct mtk_cpu_dvfs_info *info;
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev, "failed to scale voltage: %d\n",
+ ret);
+ }
+ mutex_unlock(&info->lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = dev_pm_opp_get_freq(opp);
+ /* case of current opp item is disabled */
+ if (info->opp_freq == freq) {
+ freq = 1;
+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (!IS_ERR(new_opp)) {
+ dev_pm_opp_put(new_opp);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy,
+ freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ } else {
+ pr_err("%s: all opp items are disabled\n",
+ __func__);
+ }
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -392,11 +463,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ pr_warn("cannot register opp notification\n");
+ goto out_disable_inter_clock;
+ }
+
+ mutex_init(&info->lock);
info->cpu_dev = cpu_dev;
info->proc_reg = proc_reg;
info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
info->cpu_clk = cpu_clk;
info->inter_clk = inter_clk;
+ info->opp_freq = clk_get_rate(cpu_clk);
/*
* If SRAM regulator is present, software "voltage tracking" is needed
--
2.12.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v7 7/8] devfreq: mediatek: cci devfreq register opp notification for SVS support
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
` (5 preceding siblings ...)
2020-07-10 2:31 ` [PATCH v7 6/8] cpufreq: mediatek: add opp notification for SVS support Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 8/8] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183 Andrew-sh.Cheng
7 siblings, 0 replies; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
SVS will change the voltage of opp item.
CCI devfreq need to react to change frequency.
Change-Id: I9d2ea9bd4be85970333eac92ab6fc330766e88da
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/devfreq/mt8183-cci-devfreq.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
index 62d02464a34b..9ccc49ba0b9a 100644
--- a/drivers/devfreq/mt8183-cci-devfreq.c
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -21,6 +21,7 @@ struct cci_devfreq {
struct clk *cci_clk;
int old_vproc;
unsigned long old_freq;
+ struct notifier_block opp_nb;
};
static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc)
@@ -89,6 +90,26 @@ static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
return 0;
}
+static int ccidevfreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct cci_devfreq *cci_df = container_of(nb, struct cci_devfreq,
+ opp_nb);
+ unsigned long freq, volt;
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+ /* current opp item is changed */
+ if (freq == cci_df->old_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ mtk_cci_set_voltage(cci_df, volt);
+ }
+ }
+
+ return 0;
+}
+
static struct devfreq_dev_profile cci_devfreq_profile = {
.target = mtk_cci_devfreq_target,
};
@@ -98,12 +119,15 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
struct device *cci_dev = &pdev->dev;
struct cci_devfreq *cci_df;
struct devfreq_passive_data *passive_data;
+ struct notifier_block *opp_nb;
int ret;
cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
if (!cci_df)
return -ENOMEM;
+ opp_nb = &cci_df->opp_nb;
+
cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
if (ret) {
@@ -152,6 +176,9 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
goto err_opp;
}
+ opp_nb->notifier_call = ccidevfreq_opp_notifier;
+ dev_pm_opp_register_notifier(cci_dev, opp_nb);
+
return 0;
err_opp:
--
2.12.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v7 8/8] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
` (6 preceding siblings ...)
2020-07-10 2:31 ` [PATCH v7 7/8] devfreq: mediatek: cci devfreq register " Andrew-sh.Cheng
@ 2020-07-10 2:31 ` Andrew-sh.Cheng
7 siblings, 0 replies; 15+ messages in thread
From: Andrew-sh.Cheng @ 2020-07-10 2:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
add cpufreq and cci devfreq nodes for mt8183
base on regulator node
https://patchwork.kernel.org/patch/11500339/
Now queued for v5.7-next/dts64
Change-Id: I9d7d8f9ec9bda2b70ef50a54cfbf151afc734314
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 245 ++++++++++++++++++++++++++++
2 files changed, 281 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index afd6ddbcbdf2..8f738c6d5169 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -378,6 +378,42 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e6193c4f1684..8961cd61bc3a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -32,6 +32,219 @@
i2c11 = &i2c11;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ }; };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ cci_opp: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -74,6 +287,10 @@
reg = <0x000>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -84,6 +301,10 @@
reg = <0x001>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -94,6 +315,10 @@
reg = <0x002>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -104,6 +329,10 @@
reg = <0x003>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -114,6 +343,10 @@
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -124,6 +357,10 @@
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -134,6 +371,10 @@
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -144,6 +385,10 @@
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
--
2.12.5
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^ permalink raw reply related [flat|nested] 15+ messages in thread