From: "Pali Rohár" <pali@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: "Marek Behún" <kabel@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Russell King" <rmk+kernel@armlinux.org.uk>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts
Date: Fri, 7 Jan 2022 12:50:53 +0100 [thread overview]
Message-ID: <20220107115053.k5d2uv7yrftrpcez@pali> (raw)
In-Reply-To: <874k6gvkhz.wl-maz@kernel.org>
On Thursday 06 January 2022 17:31:36 Marc Zyngier wrote:
> On Thu, 06 Jan 2022 17:20:44 +0000,
> Marek Behún <kabel@kernel.org> wrote:
> >
> > On Thu, 06 Jan 2022 16:27:44 +0000
> > Marc Zyngier <maz@kernel.org> wrote:
> > > You are completely missing my point. I'm talking about data
> > > structures, you're talking about interrupts. You have this:
> > >
> > > struct mvebu_pcie_port {
> > > // Tons of stuff
> > > struct irq_chip intx_chip;
> > > };
> > >
> > > What I want you to do is:
> > >
> > > struct mvebu_pcie_port {
> > > // Tons of stuff
> > > };
> > >
> > > static struct irq_chip intx_chip = {
> > > .name = "INTx",
> > > .irq_mask = mvebu_pcie_intx_irq_mask,
> > > .irq_unmask = mvebu_pcie_intx_irq_unmask;
> > > };
> > >
> > > That's it. No more, no less.
> > >
> > > M.
> > >
> >
> > Hmm, but struct irq_chip contains a dynamic member,
> > struct device *parent_device;
> > Isn't that used? Or are you planning to kill it?
>
> Indeed, and I am definitely planning to kill it. This is the wrong
> place for this stuff, and I want it gone. There are thankfully very
> few users of this misfeature.
Ok, so what about this change?
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 1e90ab888075..5c816338a569 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -54,9 +54,10 @@
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_INT_CAUSE_OFF 0x1900
+#define PCIE_INT_UNMASK_OFF 0x1910
+#define PCIE_INT_INTX(i) BIT(24+i)
#define PCIE_INT_PM_PME BIT(28)
-#define PCIE_MASK_OFF 0x1910
-#define PCIE_MASK_ENABLE_INTS 0x0f000000
+#define PCIE_INT_ALL_MASK GENMASK(31, 0)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_CTRL_RC_MODE BIT(1)
@@ -110,6 +111,9 @@ struct mvebu_pcie_port {
struct mvebu_pcie_window iowin;
u32 saved_pcie_stat;
struct resource regs;
+ struct irq_domain *intx_irq_domain;
+ raw_spinlock_t irq_lock;
+ int intx_irq;
};
static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
@@ -235,7 +239,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
- u32 ctrl, lnkcap, cmd, dev_rev, mask;
+ u32 ctrl, lnkcap, cmd, dev_rev, unmask;
/* Setup PCIe controller to Root Complex mode. */
ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
@@ -288,10 +292,30 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
- /* Enable interrupt lines A-D. */
- mask = mvebu_readl(port, PCIE_MASK_OFF);
- mask |= PCIE_MASK_ENABLE_INTS;
- mvebu_writel(port, mask, PCIE_MASK_OFF);
+ /* Mask all interrupt sources. */
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
+
+ /* Clear all interrupt causes. */
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
+
+ if (port->intx_irq <= 0) {
+ /*
+ * When neither "summary" interrupt, nor "intx" interrupt was
+ * specified in DT then unmask all legacy INTx interrupts as in
+ * this case driver does not provide a way for masking and
+ * unmasking of individual legacy INTx interrupts. In this case
+ * all interrupts, including legacy INTx are reported via one
+ * shared GIC source and therefore kernel cannot distinguish
+ * which individual legacy INTx was triggered. These interrupts
+ * are shared, so it should not cause any issue. Just
+ * performance penalty as every PCIe interrupt handler needs to
+ * be called when some interrupt is triggered.
+ */
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) |
+ PCIE_INT_INTX(2) | PCIE_INT_INTX(3);
+ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
+ }
}
static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
@@ -924,6 +948,108 @@ static struct pci_ops mvebu_pcie_ops = {
.write = mvebu_pcie_wr_conf,
};
+static void mvebu_pcie_intx_irq_mask(struct irq_data *d)
+{
+ struct mvebu_pcie_port *port = d->domain->host_data;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ unsigned long flags;
+ u32 unmask;
+
+ raw_spin_lock_irqsave(&port->irq_lock, flags);
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ unmask &= ~PCIE_INT_INTX(hwirq);
+ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
+ raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+static void mvebu_pcie_intx_irq_unmask(struct irq_data *d)
+{
+ struct mvebu_pcie_port *port = d->domain->host_data;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ unsigned long flags;
+ u32 unmask;
+
+ raw_spin_lock_irqsave(&port->irq_lock, flags);
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ unmask |= PCIE_INT_INTX(hwirq);
+ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
+ raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+static struct irq_chip intx_irq_chip = {
+ .name = "mvebu-INTx",
+ .irq_mask = mvebu_pcie_intx_irq_mask,
+ .irq_unmask = mvebu_pcie_intx_irq_unmask,
+};
+
+static int mvebu_pcie_intx_irq_map(struct irq_domain *h,
+ unsigned int virq, irq_hw_number_t hwirq)
+{
+ struct mvebu_pcie_port *port = h->host_data;
+
+ irq_set_status_flags(virq, IRQ_LEVEL);
+ irq_set_chip_and_handler(virq, &intx_irq_chip, handle_level_irq);
+ irq_set_chip_data(virq, port);
+
+ return 0;
+}
+
+static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_ops = {
+ .map = mvebu_pcie_intx_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port)
+{
+ struct device *dev = &port->pcie->pdev->dev;
+ struct device_node *pcie_intc_node;
+
+ raw_spin_lock_init(&port->irq_lock);
+
+ pcie_intc_node = of_get_next_child(port->dn, NULL);
+ if (!pcie_intc_node) {
+ dev_err(dev, "No PCIe Intc node found for %s\n", port->name);
+ return -ENODEV;
+ }
+
+ port->intx_irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
+ &mvebu_pcie_intx_irq_domain_ops,
+ port);
+ of_node_put(pcie_intc_node);
+ if (!port->intx_irq_domain) {
+ dev_err(dev, "Failed to get INTx IRQ domain for %s\n", port->name);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void mvebu_pcie_irq_handler(struct irq_desc *desc)
+{
+ struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct device *dev = &port->pcie->pdev->dev;
+ u32 cause, unmask, status;
+ int i;
+
+ chained_irq_enter(chip, desc);
+
+ cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ status = cause & unmask;
+
+ /* Process legacy INTx interrupts */
+ for (i = 0; i < PCI_NUM_INTX; i++) {
+ if (!(status & PCIE_INT_INTX(i)))
+ continue;
+
+ if (generic_handle_domain_irq(port->intx_irq_domain, i) == -EINVAL)
+ dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A');
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
/* Interrupt support on mvebu emulated bridges is not implemented yet */
@@ -1121,6 +1247,21 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
port->io_attr = -1;
}
+ /*
+ * Old DT bindings do not contain "intx" interrupt
+ * so do not fail probing driver when interrupt does not exist.
+ */
+ port->intx_irq = of_irq_get_byname(child, "intx");
+ if (port->intx_irq == -EPROBE_DEFER) {
+ ret = port->intx_irq;
+ goto err;
+ }
+ if (port->intx_irq <= 0) {
+ dev_warn(dev, "%s: legacy INTx interrupts cannot be masked individually, "
+ "%pOF does not contain intx interrupt\n",
+ port->name, child);
+ }
+
reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
if (reset_gpio == -EPROBE_DEFER) {
ret = reset_gpio;
@@ -1317,6 +1458,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = &pcie->ports[i];
+ int irq = port->intx_irq;
child = port->dn;
if (!child)
@@ -1344,6 +1486,22 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
continue;
}
+ if (irq > 0) {
+ ret = mvebu_pcie_init_irq_domain(port);
+ if (ret) {
+ dev_err(dev, "%s: cannot init irq domain\n",
+ port->name);
+ pci_bridge_emul_cleanup(&port->bridge);
+ devm_iounmap(dev, port->base);
+ port->base = NULL;
+ mvebu_pcie_powerdown(port);
+ continue;
+ }
+ irq_set_chained_handler_and_data(irq,
+ mvebu_pcie_irq_handler,
+ port);
+ }
+
/*
* PCIe topology exported by mvebu hw is quite complicated. In
* reality has something like N fully independent host bridges
@@ -1448,6 +1606,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = &pcie->ports[i];
+ int irq = port->intx_irq;
if (!port->base)
continue;
@@ -1458,7 +1617,17 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Mask all interrupt sources. */
- mvebu_writel(port, 0, PCIE_MASK_OFF);
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
+
+ /* Clear all interrupt causes. */
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
+
+ /* Remove IRQ domains. */
+ if (port->intx_irq_domain)
+ irq_domain_remove(port->intx_irq_domain);
+
+ if (irq > 0)
+ irq_set_chained_handler_and_data(irq, NULL, NULL);
/* Free config space for emulated root bridge. */
pci_bridge_emul_cleanup(&port->bridge);
--
2.20.1
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next prev parent reply other threads:[~2022-01-07 11:52 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 1:29 ` Rob Herring
2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-05 15:41 ` Rob Herring
2022-01-05 15:49 ` Pali Rohár
2022-01-12 1:43 ` Pali Rohár
2022-01-12 14:53 ` Rob Herring
2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 1:30 ` Rob Herring
2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-01-06 15:28 ` Marc Zyngier
2022-01-06 15:44 ` Pali Rohár
2022-01-06 15:55 ` Marc Zyngier
2022-01-06 16:20 ` Pali Rohár
2022-01-06 16:27 ` Marc Zyngier
2022-01-06 17:20 ` Marek Behún
2022-01-06 17:31 ` Marc Zyngier
2022-01-07 11:50 ` Pali Rohár [this message]
2022-01-07 18:53 ` Marc Zyngier
2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-12 15:18 ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-12 15:18 ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-12 15:18 ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-12 15:18 ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 15:18 ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-20 17:09 ` Rob Herring
2022-01-20 17:19 ` Pali Rohár
2022-01-12 15:18 ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-12 15:18 ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-12 15:18 ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-20 16:49 ` Rob Herring
2022-01-20 16:55 ` Pali Rohár
2022-01-20 18:40 ` Rob Herring
2022-01-12 15:18 ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 15:36 ` Marek Behún
2022-01-12 15:18 ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-02-11 17:19 ` Lorenzo Pieralisi
2022-02-11 17:52 ` Pali Rohár
2022-02-11 18:21 ` Lorenzo Pieralisi
2022-02-12 10:59 ` Marc Zyngier
2022-02-16 23:40 ` Pali Rohár
2022-02-22 10:21 ` Lorenzo Pieralisi
2022-02-22 10:51 ` Pali Rohár
2022-02-22 15:24 ` Lorenzo Pieralisi
2022-02-22 15:42 ` Pali Rohár
2022-02-22 15:45 ` Lorenzo Pieralisi
2022-02-22 15:55 ` Pali Rohár
2022-01-12 15:18 ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-02-14 15:07 ` Gregory CLEMENT
2022-02-14 15:09 ` Pali Rohár
2022-02-14 15:26 ` Gregory CLEMENT
[not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>
2022-02-15 10:48 ` Luís Mendes
2022-02-15 10:52 ` Pali Rohár
2022-02-18 21:53 ` Luís Mendes
2022-02-19 13:36 ` Pali Rohár
2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-11 18:01 ` Pali Rohár
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