linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: "Pali Rohár" <pali@kernel.org>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Marek Behún" <kabel@kernel.org>,
	"Russell King" <rmk+kernel@armlinux.org.uk>,
	"Andrew Lunn" <andrew@lunn.ch>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts
Date: Mon, 14 Feb 2022 16:09:23 +0100	[thread overview]
Message-ID: <20220214150923.a5ttxoh426cfxn4v@pali> (raw)
In-Reply-To: <87wnhxjxlq.fsf@BL-laptop>

On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote:
> Hello Pali,
> 
> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported
> > separately and not mixed into one Linux virq source anymore.
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> >  arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++-----
> 
> Is there any reason for not doing the same change in armada-380.dtsi ?

I do not have A380 HW, so I did this change only for A385 which I have tested.

> Grégory
> 
> >  1 file changed, 44 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
> > index f0022d10c715..83392b92dae2 100644
> > --- a/arch/arm/boot/dts/armada-385.dtsi
> > +++ b/arch/arm/boot/dts/armada-385.dtsi
> > @@ -69,16 +69,25 @@
> >  				reg = <0x0800 0 0 0 0>;
> >  				#address-cells = <3>;
> >  				#size-cells = <2>;
> > +				interrupt-names = "intx";
> > +				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> >  				#interrupt-cells = <1>;
> >  				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> >  					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
> >  				bus-range = <0x00 0xff>;
> > -				interrupt-map-mask = <0 0 0 0>;
> > -				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-map-mask = <0 0 0 7>;
> > +				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> > +						<0 0 0 2 &pcie1_intc 1>,
> > +						<0 0 0 3 &pcie1_intc 2>,
> > +						<0 0 0 4 &pcie1_intc 3>;
> >  				marvell,pcie-port = <0>;
> >  				marvell,pcie-lane = <0>;
> >  				clocks = <&gateclk 8>;
> >  				status = "disabled";
> > +				pcie1_intc: interrupt-controller {
> > +					interrupt-controller;
> > +					#interrupt-cells = <1>;
> > +				};
> >  			};
> >  
> >  			/* x1 port */
> > @@ -88,16 +97,25 @@
> >  				reg = <0x1000 0 0 0 0>;
> >  				#address-cells = <3>;
> >  				#size-cells = <2>;
> > +				interrupt-names = "intx";
> > +				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> >  				#interrupt-cells = <1>;
> >  				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> >  					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
> >  				bus-range = <0x00 0xff>;
> > -				interrupt-map-mask = <0 0 0 0>;
> > -				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-map-mask = <0 0 0 7>;
> > +				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> > +						<0 0 0 2 &pcie2_intc 1>,
> > +						<0 0 0 3 &pcie2_intc 2>,
> > +						<0 0 0 4 &pcie2_intc 3>;
> >  				marvell,pcie-port = <1>;
> >  				marvell,pcie-lane = <0>;
> >  				clocks = <&gateclk 5>;
> >  				status = "disabled";
> > +				pcie2_intc: interrupt-controller {
> > +					interrupt-controller;
> > +					#interrupt-cells = <1>;
> > +				};
> >  			};
> >  
> >  			/* x1 port */
> > @@ -107,16 +125,25 @@
> >  				reg = <0x1800 0 0 0 0>;
> >  				#address-cells = <3>;
> >  				#size-cells = <2>;
> > +				interrupt-names = "intx";
> > +				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> >  				#interrupt-cells = <1>;
> >  				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> >  					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
> >  				bus-range = <0x00 0xff>;
> > -				interrupt-map-mask = <0 0 0 0>;
> > -				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-map-mask = <0 0 0 7>;
> > +				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> > +						<0 0 0 2 &pcie3_intc 1>,
> > +						<0 0 0 3 &pcie3_intc 2>,
> > +						<0 0 0 4 &pcie3_intc 3>;
> >  				marvell,pcie-port = <2>;
> >  				marvell,pcie-lane = <0>;
> >  				clocks = <&gateclk 6>;
> >  				status = "disabled";
> > +				pcie3_intc: interrupt-controller {
> > +					interrupt-controller;
> > +					#interrupt-cells = <1>;
> > +				};
> >  			};
> >  
> >  			/*
> > @@ -129,16 +156,25 @@
> >  				reg = <0x2000 0 0 0 0>;
> >  				#address-cells = <3>;
> >  				#size-cells = <2>;
> > +				interrupt-names = "intx";
> > +				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> >  				#interrupt-cells = <1>;
> >  				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
> >  					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
> >  				bus-range = <0x00 0xff>;
> > -				interrupt-map-mask = <0 0 0 0>;
> > -				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-map-mask = <0 0 0 7>;
> > +				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
> > +						<0 0 0 2 &pcie4_intc 1>,
> > +						<0 0 0 3 &pcie4_intc 2>,
> > +						<0 0 0 4 &pcie4_intc 3>;
> >  				marvell,pcie-port = <3>;
> >  				marvell,pcie-lane = <0>;
> >  				clocks = <&gateclk 7>;
> >  				status = "disabled";
> > +				pcie4_intc: interrupt-controller {
> > +					interrupt-controller;
> > +					#interrupt-cells = <1>;
> > +				};
> >  			};
> >  		};
> >  	};
> > -- 
> > 2.20.1
> >
> 
> -- 
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-02-14 15:10 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12  1:29   ` Rob Herring
2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-05 15:41   ` Rob Herring
2022-01-05 15:49     ` Pali Rohár
2022-01-12  1:43     ` Pali Rohár
2022-01-12 14:53       ` Rob Herring
2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12  1:30   ` Rob Herring
2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-01-06 15:28   ` Marc Zyngier
2022-01-06 15:44     ` Pali Rohár
2022-01-06 15:55       ` Marc Zyngier
2022-01-06 16:20         ` Pali Rohár
2022-01-06 16:27           ` Marc Zyngier
2022-01-06 17:20             ` Marek Behún
2022-01-06 17:31               ` Marc Zyngier
2022-01-07 11:50                 ` Pali Rohár
2022-01-07 18:53                   ` Marc Zyngier
2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-12 15:18   ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-12 15:18   ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-12 15:18   ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-12 15:18   ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 15:18   ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-20 17:09     ` Rob Herring
2022-01-20 17:19       ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-12 15:18   ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-12 15:18   ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-20 16:49     ` Rob Herring
2022-01-20 16:55       ` Pali Rohár
2022-01-20 18:40         ` Rob Herring
2022-01-12 15:18   ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 15:36     ` Marek Behún
2022-01-12 15:18   ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-02-11 17:19     ` Lorenzo Pieralisi
2022-02-11 17:52       ` Pali Rohár
2022-02-11 18:21         ` Lorenzo Pieralisi
2022-02-12 10:59           ` Marc Zyngier
2022-02-16 23:40         ` Pali Rohár
2022-02-22 10:21           ` Lorenzo Pieralisi
2022-02-22 10:51             ` Pali Rohár
2022-02-22 15:24               ` Lorenzo Pieralisi
2022-02-22 15:42                 ` Pali Rohár
2022-02-22 15:45                   ` Lorenzo Pieralisi
2022-02-22 15:55                     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-02-14 15:07     ` Gregory CLEMENT
2022-02-14 15:09       ` Pali Rohár [this message]
2022-02-14 15:26         ` Gregory CLEMENT
     [not found]           ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>
2022-02-15 10:48             ` Luís Mendes
2022-02-15 10:52               ` Pali Rohár
2022-02-18 21:53                 ` Luís Mendes
2022-02-19 13:36                   ` Pali Rohár
2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-11 18:01   ` Pali Rohár

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220214150923.a5ttxoh426cfxn4v@pali \
    --to=pali@kernel.org \
    --cc=andrew@lunn.ch \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=gregory.clement@bootlin.com \
    --cc=kabel@kernel.org \
    --cc=kw@linux.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=rmk+kernel@armlinux.org.uk \
    --cc=robh+dt@kernel.org \
    --cc=thomas.petazzoni@bootlin.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).