[PATCH 1/6] arm64: dts: ls2080a-qds: add mdio mux nodes from on-board FPGA

[PATCH 1/6] arm64: dts: ls2080a-qds: add mdio mux nodes from on-board FPGA

[Li Yang]

Add mmio mdio mux nodes from the on-board FPGA.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 .../boot/dts/freescale/fsl-ls2080a-qds.dts    | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index f6c3ee78ace0..c3caca1c0ab6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -23,3 +23,72 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 };
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+	phy-handle = <&mdio0_phy12>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac10 {
+	phy-handle = <&mdio0_phy13>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac11 {
+	phy-handle = <&mdio0_phy14>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac12 {
+	phy-handle = <&mdio0_phy15>;
+	phy-connection-type = "sgmii";
+};
+
+&ifc {
+	boardctrl: board-control@3,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
+		reg = <3 0 0x300>;
+		ranges = <0 3 0 0x300>;
+
+		mdio_mux_emi1 {
+			compatible = "mdio-mux-mmioreg", "mdio-mux";
+			mdio-parent-bus = <&emdio1>;
+			reg = <0x54 1>;		/* BRDCFG4 */
+			mux-mask = <0xe0>;	/* EMI1_MDIO */
+
+			#address-cells=<1>;
+			#size-cells = <0>;
+
+			/* Child MDIO buses, one for each riser card:
+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+			 * VSC8234 PHYs on the riser cards.
+			 */
+
+			mdio_mux3: mdio@60 {
+				reg = <0x60>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mdio0_phy12: mdio_phy0@1c {
+					reg = <0x1c>;
+				};
+
+				mdio0_phy13: mdio_phy1@1d {
+					reg = <0x1d>;
+				};
+
+				mdio0_phy14: mdio_phy2@1e {
+					reg = <0x1e>;
+				};
+
+				mdio0_phy15: mdio_phy3@1f {
+					reg = <0x1f>;
+				};
+			};
+		};
+	};
+};
+
-- 
2.25.1


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[PATCH 2/6] arm64: dts: ls2088a-qds: add mdio mux nodes from on-board FPGA

[Li Yang]

Add mmio mdio mux nodes from the on-board FPGA.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 .../boot/dts/freescale/fsl-ls2088a-qds.dts    | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
index 7c17b1bd4529..d36cf7f3432b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
@@ -22,3 +22,71 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 };
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+	phy-handle = <&mdio0_phy12>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac10 {
+	phy-handle = <&mdio0_phy13>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac11 {
+	phy-handle = <&mdio0_phy14>;
+	phy-connection-type = "sgmii";
+};
+
+&dpmac12 {
+	phy-handle = <&mdio0_phy15>;
+	phy-connection-type = "sgmii";
+};
+
+&ifc {
+	boardctrl: board-control@3,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
+		reg = <3 0 0x300>;
+		ranges = <0 3 0 0x300>;
+
+		mdio_mux_emi1 {
+			compatible = "mdio-mux-mmioreg", "mdio-mux";
+			mdio-parent-bus = <&emdio1>;
+			reg = <0x54 1>;		/* BRDCFG4 */
+			mux-mask = <0xe0>;	/* EMI1_MDIO */
+
+			#address-cells=<1>;
+			#size-cells = <0>;
+
+			/* Child MDIO buses, one for each riser card:
+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+			 * VSC8234 PHYs on the riser cards.
+			 */
+
+			mdio_mux3: mdio@60 {
+				reg = <0x60>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mdio0_phy12: mdio_phy0@1c {
+					reg = <0x1c>;
+				};
+
+				mdio0_phy13: mdio_phy1@1d {
+					reg = <0x1d>;
+				};
+
+				mdio0_phy14: mdio_phy2@1e {
+					reg = <0x1e>;
+				};
+
+				mdio0_phy15: mdio_phy3@1f {
+					reg = <0x1f>;
+				};
+			};
+		};
+	};
+};
-- 
2.25.1


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[PATCH 3/6] arm64: dts: ls2080a-rdb: add phy nodes

[Li Yang]

Define PHY nodes on the board.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 .../boot/dts/freescale/fsl-ls2080a-rdb.dts    | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index 44894356059c..1c8c99a74071 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -23,3 +23,71 @@ chosen {
 		stdout-path = "serial1:115200n8";
 	};
 };
+
+&dpmac5 {
+	phy-handle = <&mdio2_phy1>;
+	phy-connection-type = "10gbase-r";
+};
+
+&dpmac6 {
+	phy-handle = <&mdio2_phy2>;
+	phy-connection-type = "10gbase-r";
+};
+
+&dpmac7 {
+	phy-handle = <&mdio2_phy3>;
+	phy-connection-type = "10gbase-r";
+};
+
+&dpmac8 {
+	phy-handle = <&mdio2_phy4>;
+	phy-connection-type = "10gbase-r";
+};
+
+&emdio1 {
+	status = "disabled";
+
+	/* CS4340 PHYs */
+	mdio1_phy1: emdio1_phy@1 {
+		reg = <0x10>;
+	};
+
+	mdio1_phy2: emdio1_phy@2 {
+		reg = <0x11>;
+	};
+
+	mdio1_phy3: emdio1_phy@3 {
+		reg = <0x12>;
+	};
+
+	mdio1_phy4: emdio1_phy@4 {
+		reg = <0x13>;
+	};
+};
+
+&emdio2 {
+	/* AQR405 PHYs */
+	mdio2_phy1: emdio2_phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 1 0x4>; /* Level high type */
+		reg = <0x0>;
+	};
+
+	mdio2_phy2: emdio2_phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 2 0x4>; /* Level high type */
+		reg = <0x1>;
+	};
+
+	mdio2_phy3: emdio2_phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 4 0x4>; /* Level high type */
+		reg = <0x2>;
+	};
+
+	mdio2_phy4: emdio2_phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 5 0x4>; /* Level high type */
+		reg = <0x3>;
+	};
+};
-- 
2.25.1


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[PATCH 4/6] arm64: dts: ls2081a-rdb: Add DTS support for NXP LS2081ARDB

[Li Yang]

From: Priyanka Jain <priyanka.jain@nxp.com>

This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.

LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional
perspective both are same.  Hence,ls2088a SoC dtsi files are included
from ls2081ARDB dts

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Tao Yang <b31903@freescale.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../boot/dts/freescale/fsl-ls2081a-rdb.dts    | 131 ++++++++++++++++++
 2 files changed, 132 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6d8f0a532587..1b5cb71a6828 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
new file mode 100644
index 000000000000..908b9aff0489
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for NXP LS2081A RDB Board.
+ *
+ * Copyright 2017 NXP
+ *
+ * Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2088a.dtsi"
+
+/ {
+	model = "NXP Layerscape 2081A RDB Board";
+	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+};
+
+&dspi {
+	status = "okay";
+
+	n25q512a: flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <3000000>;
+		reg = <0>;
+	};
+};
+
+&esdhc {
+	status = "okay";
+};
+
+&ifc {
+	status = "disabled";
+};
+
+&i2c0 {
+	status = "okay";
+
+	pca9547: mux@75 {
+		compatible = "nxp,pca9547";
+		reg = <0x75>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x01>;
+			rtc@51 {
+				compatible = "nxp,pcf2129";
+				reg = <0x51>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <500>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			adt7481@4c {
+				compatible = "adi,adt7461";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&qspi {
+	status = "okay";
+
+	s25fs512s0: flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+
+	s25fs512s1: flash@1 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		spi-max-frequency = <20000000>;
+		reg = <1>;
+	};
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
-- 
2.25.1


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[PATCH 5/6] arm64: dts: ls208xa-rdb: fix errata E-00013

[Li Yang]

From: Biwen Li <biwen.li@nxp.com>

Specify a channel zero in idle state to
avoid enterring tri-stated state for PCA9547.
About E-00013:
	- Description: I2C1 and I2C3 buses
	  are missing pull-up.
	- Impact: When the PCA954x device is tri-stated, the I2C bus
	  will float. This makes the I2C bus and its associated
	  downstream devices inaccessible.
	- Hardware fix: Populate resistors R189 and R190 for I2C1
	  and resistors R228 and R229 for I2C3.
	- Software fix: Remove the tri-state option from the PCA954x
	  driver(PCA954x always on enable status, specify a
	  channel zero in dts to fix the errata E-00013).

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index 4b71c4fcb35f..a752f06a2e74 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -49,6 +49,8 @@ pca9547@75 {
 		reg = <0x75>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		idle-state = <0>;
+
 		i2c@1 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.25.1


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[PATCH 6/6] arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.

[Li Yang]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.
However this problem has been fixed in A72 core cluster used in LS2088.
Therefore remove the erratum from LS2088A. Keeping it only in LS2085.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 3 +--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 6f6667b70028..a2cadf757148 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -150,3 +150,7 @@ &pcie4 {
 	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
 		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 };
+
+&timer {
+	fsl,erratum-a008585;
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 3cb9c21d2775..d823d54a01a5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -239,13 +239,12 @@ map0 {
 		};
 	};
 
-	timer {
+	timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
 			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
 			     <1 11 4>, /* Virtual PPI, active-low */
 			     <1 10 4>; /* Hypervisor PPI, active-low */
-		fsl,erratum-a008585;
 	};
 
 	pmu {
-- 
2.25.1


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Re: [PATCH 1/6] arm64: dts: ls2080a-qds: add mdio mux nodes from on-board FPGA

[Shawn Guo]

On Thu, Mar 17, 2022 at 02:01:04PM -0500, Li Yang wrote:
> Add mmio mdio mux nodes from the on-board FPGA.
> 
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
>  .../boot/dts/freescale/fsl-ls2080a-qds.dts    | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> index f6c3ee78ace0..c3caca1c0ab6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> @@ -23,3 +23,72 @@ chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
>  };
> +
> +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
> +&dpmac9 {
> +	phy-handle = <&mdio0_phy12>;
> +	phy-connection-type = "sgmii";
> +};
> +
> +&dpmac10 {
> +	phy-handle = <&mdio0_phy13>;
> +	phy-connection-type = "sgmii";
> +};
> +
> +&dpmac11 {
> +	phy-handle = <&mdio0_phy14>;
> +	phy-connection-type = "sgmii";
> +};
> +
> +&dpmac12 {
> +	phy-handle = <&mdio0_phy15>;
> +	phy-connection-type = "sgmii";
> +};
> +
> +&ifc {
> +	boardctrl: board-control@3,0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
> +		reg = <3 0 0x300>;
> +		ranges = <0 3 0 0x300>;
> +
> +		mdio_mux_emi1 {
> +			compatible = "mdio-mux-mmioreg", "mdio-mux";
> +			mdio-parent-bus = <&emdio1>;
> +			reg = <0x54 1>;		/* BRDCFG4 */

Please ensure the patch doesn't introduce additional DTC warnings.  I
think 'reg' should present only in nodes with a matching unit-address.

Shawn

> +			mux-mask = <0xe0>;	/* EMI1_MDIO */
> +
> +			#address-cells=<1>;
> +			#size-cells = <0>;
> +
> +			/* Child MDIO buses, one for each riser card:
> +			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
> +			 * VSC8234 PHYs on the riser cards.
> +			 */
> +
> +			mdio_mux3: mdio@60 {
> +				reg = <0x60>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				mdio0_phy12: mdio_phy0@1c {
> +					reg = <0x1c>;
> +				};
> +
> +				mdio0_phy13: mdio_phy1@1d {
> +					reg = <0x1d>;
> +				};
> +
> +				mdio0_phy14: mdio_phy2@1e {
> +					reg = <0x1e>;
> +				};
> +
> +				mdio0_phy15: mdio_phy3@1f {
> +					reg = <0x1f>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> -- 
> 2.25.1
> 

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Re: [PATCH 3/6] arm64: dts: ls2080a-rdb: add phy nodes

[Shawn Guo]

On Thu, Mar 17, 2022 at 02:01:06PM -0500, Li Yang wrote:
> Define PHY nodes on the board.
> 
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
>  .../boot/dts/freescale/fsl-ls2080a-rdb.dts    | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> index 44894356059c..1c8c99a74071 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> @@ -23,3 +23,71 @@ chosen {
>  		stdout-path = "serial1:115200n8";
>  	};
>  };
> +
> +&dpmac5 {
> +	phy-handle = <&mdio2_phy1>;
> +	phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac6 {
> +	phy-handle = <&mdio2_phy2>;
> +	phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac7 {
> +	phy-handle = <&mdio2_phy3>;
> +	phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac8 {
> +	phy-handle = <&mdio2_phy4>;
> +	phy-connection-type = "10gbase-r";
> +};
> +
> +&emdio1 {
> +	status = "disabled";
> +
> +	/* CS4340 PHYs */
> +	mdio1_phy1: emdio1_phy@1 {

We prefer hyphen rather than underscore in node name.

Shawn

> +		reg = <0x10>;
> +	};
> +
> +	mdio1_phy2: emdio1_phy@2 {
> +		reg = <0x11>;
> +	};
> +
> +	mdio1_phy3: emdio1_phy@3 {
> +		reg = <0x12>;
> +	};
> +
> +	mdio1_phy4: emdio1_phy@4 {
> +		reg = <0x13>;
> +	};
> +};
> +
> +&emdio2 {
> +	/* AQR405 PHYs */
> +	mdio2_phy1: emdio2_phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		interrupts = <0 1 0x4>; /* Level high type */
> +		reg = <0x0>;
> +	};
> +
> +	mdio2_phy2: emdio2_phy@2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		interrupts = <0 2 0x4>; /* Level high type */
> +		reg = <0x1>;
> +	};
> +
> +	mdio2_phy3: emdio2_phy@3 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		interrupts = <0 4 0x4>; /* Level high type */
> +		reg = <0x2>;
> +	};
> +
> +	mdio2_phy4: emdio2_phy@4 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		interrupts = <0 5 0x4>; /* Level high type */
> +		reg = <0x3>;
> +	};
> +};
> -- 
> 2.25.1
> 

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Re: [PATCH 4/6] arm64: dts: ls2081a-rdb: Add DTS support for NXP LS2081ARDB

[Shawn Guo]

On Thu, Mar 17, 2022 at 02:01:07PM -0500, Li Yang wrote:
> From: Priyanka Jain <priyanka.jain@nxp.com>
> 
> This patch add support for NXP LS2081ARDB board which has
> LS2081A SoC.
> 
> LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional

... SoC. So, ...?

> perspective both are same.  Hence,ls2088a SoC dtsi files are included

Hence, ls2088a ...

> from ls2081ARDB dts

LS2081ARDB dts.

I won't review the patch content until the commit log looks good.

Shawn

> 
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
> Signed-off-by: Tao Yang <b31903@freescale.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../boot/dts/freescale/fsl-ls2081a-rdb.dts    | 131 ++++++++++++++++++
>  2 files changed, 132 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 6d8f0a532587..1b5cb71a6828 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> new file mode 100644
> index 000000000000..908b9aff0489
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for NXP LS2081A RDB Board.
> + *
> + * Copyright 2017 NXP
> + *
> + * Priyanka Jain <priyanka.jain@nxp.com>
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-ls2088a.dtsi"
> +
> +/ {
> +	model = "NXP Layerscape 2081A RDB Board";
> +	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
> +
> +	aliases {
> +		serial0 = &serial0;
> +		serial1 = &serial1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial1:115200n8";
> +	};
> +};
> +
> +&dspi {
> +	status = "okay";
> +
> +	n25q512a: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <3000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&esdhc {
> +	status = "okay";
> +};
> +
> +&ifc {
> +	status = "disabled";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	pca9547: mux@75 {
> +		compatible = "nxp,pca9547";
> +		reg = <0x75>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c@1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x01>;
> +			rtc@51 {
> +				compatible = "nxp,pcf2129";
> +				reg = <0x51>;
> +			};
> +		};
> +
> +		i2c@2 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x02>;
> +
> +			ina220@40 {
> +				compatible = "ti,ina220";
> +				reg = <0x40>;
> +				shunt-resistor = <500>;
> +			};
> +		};
> +
> +		i2c@3 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x3>;
> +
> +			adt7481@4c {
> +				compatible = "adi,adt7461";
> +				reg = <0x4c>;
> +			};
> +		};
> +	};
> +};
> +
> +&qspi {
> +	status = "okay";
> +
> +	s25fs512s0: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +
> +	s25fs512s1: flash@1 {
> +		compatible = "jedec,spi-nor";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;
> +		spi-max-frequency = <20000000>;
> +		reg = <1>;
> +	};
> +};
> +
> +&sata0 {
> +	status = "okay";
> +};
> +
> +&sata1 {
> +	status = "okay";
> +};
> +
> +&usb0 {
> +	status = "okay";
> +};
> +
> +&usb1 {
> +	status = "okay";
> +};
> -- 
> 2.25.1
> 

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Re: [PATCH 5/6] arm64: dts: ls208xa-rdb: fix errata E-00013

[Shawn Guo]

On Thu, Mar 17, 2022 at 02:01:08PM -0500, Li Yang wrote:
> From: Biwen Li <biwen.li@nxp.com>
> 
> Specify a channel zero in idle state to
> avoid enterring tri-stated state for PCA9547.

Please check Documentation/process/submitting-patches.rst for commit log
wrapping requirement.

> About E-00013:
> 	- Description: I2C1 and I2C3 buses

Use space instead of tab for bullet indent.

Shawn

> 	  are missing pull-up.
> 	- Impact: When the PCA954x device is tri-stated, the I2C bus
> 	  will float. This makes the I2C bus and its associated
> 	  downstream devices inaccessible.
> 	- Hardware fix: Populate resistors R189 and R190 for I2C1
> 	  and resistors R228 and R229 for I2C3.
> 	- Software fix: Remove the tri-state option from the PCA954x
> 	  driver(PCA954x always on enable status, specify a
> 	  channel zero in dts to fix the errata E-00013).
> 
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
> index 4b71c4fcb35f..a752f06a2e74 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
> @@ -49,6 +49,8 @@ pca9547@75 {
>  		reg = <0x75>;
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> +		idle-state = <0>;
> +
>  		i2c@1 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -- 
> 2.25.1
> 

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Re: [PATCH 6/6] arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.

[Shawn Guo]

On Thu, Mar 17, 2022 at 02:01:09PM -0500, Li Yang wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
> 
> NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.

s/LS2085rev1/LS2085 rev1

Shawn

> However this problem has been fixed in A72 core cluster used in LS2088.
> Therefore remove the erratum from LS2088A. Keeping it only in LS2085.
> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
> Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
>  arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 3 +--
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index 6f6667b70028..a2cadf757148 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -150,3 +150,7 @@ &pcie4 {
>  	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
>  		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
>  };
> +
> +&timer {
> +	fsl,erratum-a008585;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> index 3cb9c21d2775..d823d54a01a5 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> @@ -239,13 +239,12 @@ map0 {
>  		};
>  	};
>  
> -	timer {
> +	timer: timer {
>  		compatible = "arm,armv8-timer";
>  		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
>  			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
>  			     <1 11 4>, /* Virtual PPI, active-low */
>  			     <1 10 4>; /* Hypervisor PPI, active-low */
> -		fsl,erratum-a008585;
>  	};
>  
>  	pmu {
> -- 
> 2.25.1
> 

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