[PATCH v3 1/6] clk: Introduce devm_clk_hw_register_mux_parent_data()

[PATCH v3 1/6] clk: Introduce devm_clk_hw_register_mux_parent_data()

[Marek Vasut]

Add an API for clock mux that uses parent_data for the parent instead of
a string parent_name.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V3: New patch
---
 include/linux/clk-provider.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 8c6ad6ea53e52..1f5dff4507812 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -964,6 +964,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
 			      (parent_names), NULL, NULL, (flags), (reg),     \
 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
 			      NULL, (lock))
+#define devm_clk_hw_register_mux_parent_data(dev, name, parent_data,	      \
+					     num_parents, flags, reg, shift,  \
+					     width, clk_mux_flags, lock)      \
+	__devm_clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
+			      NULL, NULL, (parent_data), (flags), (reg),      \
+			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
+			      NULL, (lock))
 
 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
 			 unsigned int val);
-- 
2.35.1


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[PATCH v3 2/6] clk: Introduce devm_clk_hw_register_gate_parent_data()

[Marek Vasut]

Add an API for clock gate that uses parent_data for the parent instead of
a string parent_name.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V3: New patch
---
 include/linux/clk-provider.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1f5dff4507812..4d9212b0f571f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -570,6 +570,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
 			       NULL, (flags), (reg), (bit_idx),		      \
 			       (clk_gate_flags), (lock))
+
+/**
+ * devm_clk_hw_register_gate - register a gate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_data: parent clk data
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags,  \
+					      reg, bit_idx, clk_gate_flags,   \
+					      lock)			      \
+	__devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL,	      \
+				    (parent_data), (flags), (reg), (bit_idx), \
+				    (clk_gate_flags), (lock))
+
 void clk_unregister_gate(struct clk *clk);
 void clk_hw_unregister_gate(struct clk_hw *hw);
 int clk_gate_is_enabled(struct clk_hw *hw);
-- 
2.35.1


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[PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Model it as a large static table of
gates and muxes with one exception, which is the PLL14xx . The PLL14xx
SAI PLL has to be registered separately.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V2: No change
V3: - Use devm_platform_ioremap_resource
    - Use clk_hw_onecell_data instead of clk_imx8mp_audiomix_priv
    - Include mod_devicetable.h for of_device_id struct
    - Use struct clk_parent_data instead of string parent_name
---
 drivers/clk/imx/Makefile              |   2 +-
 drivers/clk/imx/clk-imx8mp-audiomix.c | 286 ++++++++++++++++++++++++++
 2 files changed, 287 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/imx/clk-imx8mp-audiomix.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 88b9b9285d22e..c4290937637eb 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
 
 obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
 obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
-obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
+obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
 obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
 
 obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
new file mode 100644
index 0000000000000..2d5d8255c7fa2
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for i.MX8M Plus Audio BLK_CTRL
+ *
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+#include "clk.h"
+
+#define CLKEN0			0x000
+#define CLKEN1			0x004
+#define SAI_MCLK_SEL(n)		(300 + 4 * (n))	/* n in 0..5 */
+#define PDM_SEL			0x318
+#define SAI_PLL_GNRL_CTL	0x400
+
+#define SAIn_MCLK1_PARENT(n)						\
+static const struct clk_parent_data					\
+clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = {			\
+	{								\
+		.fw_name = "sai"__stringify(n),				\
+		.name = "sai"__stringify(n)				\
+	}, {								\
+		.fw_name = "sai"__stringify(n)"_mclk",			\
+		.name = "sai"__stringify(n)"_mclk"			\
+	},								\
+}
+
+SAIn_MCLK1_PARENT(1);
+SAIn_MCLK1_PARENT(2);
+SAIn_MCLK1_PARENT(3);
+SAIn_MCLK1_PARENT(5);
+SAIn_MCLK1_PARENT(6);
+SAIn_MCLK1_PARENT(7);
+
+static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
+	{ .fw_name = "sai1", .name = "sai1" },
+	{ .fw_name = "sai2", .name = "sai2" },
+	{ .fw_name = "sai3", .name = "sai3" },
+	{ .name = "dummy" },
+	{ .fw_name = "sai5", .name = "sai5" },
+	{ .fw_name = "sai6", .name = "sai6" },
+	{ .fw_name = "sai7", .name = "sai7" },
+	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+	{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
+	{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
+	{ .name = "dummy" },
+	{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
+	{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
+	{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
+	{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
+	{ .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
+	{ .fw_name = "pdm", .name = "pdm" },
+	{ .name = "sai_pll_out_div2" },
+	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+	{ .name = "dummy" },
+};
+
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
+	{ .fw_name = "osc_24m", .name = "osc_24m" },
+	{ .name = "dummy" },
+	{ .name = "dummy" },
+	{ .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
+	{ .fw_name = "sai_pll", .name = "sai_pll" },
+	{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
+};
+
+#define CLK_GATE(gname, cname)						\
+	{								\
+		gname"_cg",						\
+		IMX8MP_CLK_AUDIOMIX_##cname,				\
+		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
+		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
+		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
+	}
+
+#define CLK_SAIn(n)							\
+	{								\
+		"sai"__stringify(n)"_mclk1_sel",			\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {},		\
+		clk_imx8mp_audiomix_sai##n##_mclk1_parents,		\
+		ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
+		SAI_MCLK_SEL(n), 1, 0					\
+	}, {								\
+		"sai"__stringify(n)"_mclk2_sel",			\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {},		\
+		clk_imx8mp_audiomix_sai_mclk2_parents,			\
+		ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents),	\
+		SAI_MCLK_SEL(n), 4, 1					\
+	}, {								\
+		"sai"__stringify(n)"_ipg_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG,			\
+		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG		\
+	}, {								\
+		"sai"__stringify(n)"_mclk1_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1,			\
+		{							\
+			.fw_name = "sai"__stringify(n)"_mclk1_sel",	\
+			.name = "sai"__stringify(n)"_mclk1_sel"		\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1		\
+	}, {								\
+		"sai"__stringify(n)"_mclk2_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2,			\
+		{							\
+			.fw_name = "sai"__stringify(n)"_mclk2_sel",	\
+			.name = "sai"__stringify(n)"_mclk2_sel"		\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2		\
+	}, {								\
+		"sai"__stringify(n)"_mclk3_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3,			\
+		{							\
+			.fw_name = "sai_pll_out_div2",			\
+			.name = "sai_pll_out_div2"			\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3		\
+	}
+
+#define CLK_PDM								\
+	{								\
+		"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {},		\
+		clk_imx8mp_audiomix_pdm_parents,			\
+		ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents),		\
+		PDM_SEL, 2, 0						\
+	}
+
+struct clk_imx8mp_audiomix_sel {
+	const char			*name;
+	int				clkid;
+	const struct clk_parent_data	parent;		/* For gate */
+	const struct clk_parent_data	*parents;	/* For mux */
+	int				num_parents;
+	u16				reg;
+	u8				width;
+	u8				shift;
+};
+
+static struct clk_imx8mp_audiomix_sel sels[] = {
+	CLK_GATE("asrc", ASRC_IPG),
+	CLK_GATE("pdm", PDM_IPG),
+	CLK_GATE("earc", EARC_IPG),
+	CLK_GATE("ocrama", OCRAMA_IPG),
+	CLK_GATE("aud2htx", AUD2HTX_IPG),
+	CLK_GATE("earc_phy", EARC_PHY),
+	CLK_GATE("sdma2", SDMA2_ROOT),
+	CLK_GATE("sdma3", SDMA3_ROOT),
+	CLK_GATE("spba2", SPBA2_ROOT),
+	CLK_GATE("dsp", DSP_ROOT),
+	CLK_GATE("dspdbg", DSPDBG_ROOT),
+	CLK_GATE("edma", EDMA_ROOT),
+	CLK_GATE("audpll", AUDPLL_ROOT),
+	CLK_GATE("mu2", MU2_ROOT),
+	CLK_GATE("mu3", MU3_ROOT),
+	CLK_PDM,
+	CLK_SAIn(1),
+	CLK_SAIn(2),
+	CLK_SAIn(3),
+	CLK_SAIn(5),
+	CLK_SAIn(6),
+	CLK_SAIn(7)
+};
+
+static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *priv;
+	struct device *dev = &pdev->dev;
+	void __iomem *base;
+	struct clk_hw *hw;
+	int i;
+
+	priv = devm_kzalloc(dev,
+			    struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->num = IMX8MP_CLK_AUDIOMIX_END;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	for (i = 0; i < ARRAY_SIZE(sels); i++) {
+		if (sels[i].num_parents == 1) {
+			hw = devm_clk_hw_register_gate_parent_data(dev,
+								   sels[i].name,
+								   &sels[i].parent,
+								   0,
+								   base + sels[i].reg,
+								   sels[i].shift,
+								   0, NULL);
+		} else {
+			hw = devm_clk_hw_register_mux_parent_data(dev,
+								  sels[i].name,
+								  sels[i].parents,
+								  sels[i].num_parents,
+								  0,
+								  base + sels[i].reg,
+								  sels[i].shift,
+								  sels[i].width,
+								  0, NULL);
+		}
+
+		if (IS_ERR(hw))
+			return PTR_ERR(hw);
+
+		priv->hws[sels[i].clkid] = hw;
+	}
+
+	/* SAI PLL */
+	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_ref_sel",
+						  clk_imx8mp_audiomix_pll_parents,
+						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
+						  CLK_SET_RATE_NO_REPARENT,
+						  base + SAI_PLL_GNRL_CTL,
+						  0, 2, 0, NULL);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
+
+	hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
+				    base + 0x400, &imx_1443x_pll);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
+
+	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_bypass",
+						  clk_imx8mp_audiomix_pll_bypass_sels,
+						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
+						  CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+						  base + SAI_PLL_GNRL_CTL,
+						  16, 1, 0, NULL);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
+
+	hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
+				       0, base + SAI_PLL_GNRL_CTL, 13,
+				       0, NULL);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
+
+	hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
+					       "sai_pll_out", 0, 1, 2);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+					   priv);
+}
+
+static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
+	{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
+
+static struct platform_driver clk_imx8mp_audiomix_driver = {
+	.probe	= clk_imx8mp_audiomix_probe,
+	.driver = {
+		.name = "imx8mp-audio-blk-ctrl",
+		.of_match_table = clk_imx8mp_audiomix_of_match,
+	},
+};
+
+module_platform_driver(clk_imx8mp_audiomix_driver);
+
+MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
+MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
+MODULE_LICENSE("GPL");
-- 
2.35.1


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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-06-25 03:32:32, Marek Vasut wrote:
> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> series of clock gates and muxes. Model it as a large static table of
> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> SAI PLL has to be registered separately.
>

Again, there is a chance that the blk-ctrl driver might disable the PD
from under this.

Lucas, are you OK with this implementation, considering that it might
break the future work of audiomix blk-ctrl driver ?

> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-imx@nxp.com
> ---
> V2: No change
> V3: - Use devm_platform_ioremap_resource
>     - Use clk_hw_onecell_data instead of clk_imx8mp_audiomix_priv
>     - Include mod_devicetable.h for of_device_id struct
>     - Use struct clk_parent_data instead of string parent_name
> ---
>  drivers/clk/imx/Makefile              |   2 +-
>  drivers/clk/imx/clk-imx8mp-audiomix.c | 286 ++++++++++++++++++++++++++
>  2 files changed, 287 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/imx/clk-imx8mp-audiomix.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 88b9b9285d22e..c4290937637eb 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -25,7 +25,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
>
>  obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
>  obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
> -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
> +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
>  obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
>
>  obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
> diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
> new file mode 100644
> index 0000000000000..2d5d8255c7fa2
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Driver for i.MX8M Plus Audio BLK_CTRL
> + *
> + * Copyright (C) 2022 Marek Vasut <marex@denx.de>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +
> +#include "clk.h"
> +
> +#define CLKEN0			0x000
> +#define CLKEN1			0x004
> +#define SAI_MCLK_SEL(n)		(300 + 4 * (n))	/* n in 0..5 */
> +#define PDM_SEL			0x318
> +#define SAI_PLL_GNRL_CTL	0x400
> +
> +#define SAIn_MCLK1_PARENT(n)						\
> +static const struct clk_parent_data					\
> +clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = {			\
> +	{								\
> +		.fw_name = "sai"__stringify(n),				\
> +		.name = "sai"__stringify(n)				\
> +	}, {								\
> +		.fw_name = "sai"__stringify(n)"_mclk",			\
> +		.name = "sai"__stringify(n)"_mclk"			\
> +	},								\
> +}
> +
> +SAIn_MCLK1_PARENT(1);
> +SAIn_MCLK1_PARENT(2);
> +SAIn_MCLK1_PARENT(3);
> +SAIn_MCLK1_PARENT(5);
> +SAIn_MCLK1_PARENT(6);
> +SAIn_MCLK1_PARENT(7);
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
> +	{ .fw_name = "sai1", .name = "sai1" },
> +	{ .fw_name = "sai2", .name = "sai2" },
> +	{ .fw_name = "sai3", .name = "sai3" },
> +	{ .name = "dummy" },
> +	{ .fw_name = "sai5", .name = "sai5" },
> +	{ .fw_name = "sai6", .name = "sai6" },
> +	{ .fw_name = "sai7", .name = "sai7" },
> +	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
> +	{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
> +	{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
> +	{ .name = "dummy" },
> +	{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
> +	{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
> +	{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
> +	{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
> +	{ .name = "dummy" },
> +};
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
> +	{ .fw_name = "pdm", .name = "pdm" },
> +	{ .name = "sai_pll_out_div2" },
> +	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
> +	{ .name = "dummy" },
> +};
> +
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
> +	{ .fw_name = "osc_24m", .name = "osc_24m" },
> +	{ .name = "dummy" },
> +	{ .name = "dummy" },
> +	{ .name = "dummy" },
> +};
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
> +	{ .fw_name = "sai_pll", .name = "sai_pll" },
> +	{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
> +};
> +
> +#define CLK_GATE(gname, cname)						\
> +	{								\
> +		gname"_cg",						\
> +		IMX8MP_CLK_AUDIOMIX_##cname,				\
> +		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
> +		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
> +		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
> +	}
> +
> +#define CLK_SAIn(n)							\
> +	{								\
> +		"sai"__stringify(n)"_mclk1_sel",			\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {},		\
> +		clk_imx8mp_audiomix_sai##n##_mclk1_parents,		\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
> +		SAI_MCLK_SEL(n), 1, 0					\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk2_sel",			\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {},		\
> +		clk_imx8mp_audiomix_sai_mclk2_parents,			\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents),	\
> +		SAI_MCLK_SEL(n), 4, 1					\
> +	}, {								\
> +		"sai"__stringify(n)"_ipg_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG,			\
> +		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk1_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1,			\
> +		{							\
> +			.fw_name = "sai"__stringify(n)"_mclk1_sel",	\
> +			.name = "sai"__stringify(n)"_mclk1_sel"		\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk2_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2,			\
> +		{							\
> +			.fw_name = "sai"__stringify(n)"_mclk2_sel",	\
> +			.name = "sai"__stringify(n)"_mclk2_sel"		\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk3_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3,			\
> +		{							\
> +			.fw_name = "sai_pll_out_div2",			\
> +			.name = "sai_pll_out_div2"			\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3		\
> +	}
> +
> +#define CLK_PDM								\
> +	{								\
> +		"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {},		\
> +		clk_imx8mp_audiomix_pdm_parents,			\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents),		\
> +		PDM_SEL, 2, 0						\
> +	}
> +
> +struct clk_imx8mp_audiomix_sel {
> +	const char			*name;
> +	int				clkid;
> +	const struct clk_parent_data	parent;		/* For gate */
> +	const struct clk_parent_data	*parents;	/* For mux */
> +	int				num_parents;
> +	u16				reg;
> +	u8				width;
> +	u8				shift;
> +};
> +
> +static struct clk_imx8mp_audiomix_sel sels[] = {
> +	CLK_GATE("asrc", ASRC_IPG),
> +	CLK_GATE("pdm", PDM_IPG),
> +	CLK_GATE("earc", EARC_IPG),
> +	CLK_GATE("ocrama", OCRAMA_IPG),
> +	CLK_GATE("aud2htx", AUD2HTX_IPG),
> +	CLK_GATE("earc_phy", EARC_PHY),
> +	CLK_GATE("sdma2", SDMA2_ROOT),
> +	CLK_GATE("sdma3", SDMA3_ROOT),
> +	CLK_GATE("spba2", SPBA2_ROOT),
> +	CLK_GATE("dsp", DSP_ROOT),
> +	CLK_GATE("dspdbg", DSPDBG_ROOT),
> +	CLK_GATE("edma", EDMA_ROOT),
> +	CLK_GATE("audpll", AUDPLL_ROOT),
> +	CLK_GATE("mu2", MU2_ROOT),
> +	CLK_GATE("mu3", MU3_ROOT),
> +	CLK_PDM,
> +	CLK_SAIn(1),
> +	CLK_SAIn(2),
> +	CLK_SAIn(3),
> +	CLK_SAIn(5),
> +	CLK_SAIn(6),
> +	CLK_SAIn(7)
> +};
> +
> +static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> +{
> +	struct clk_hw_onecell_data *priv;
> +	struct device *dev = &pdev->dev;
> +	void __iomem *base;
> +	struct clk_hw *hw;
> +	int i;
> +
> +	priv = devm_kzalloc(dev,
> +			    struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
> +			    GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->num = IMX8MP_CLK_AUDIOMIX_END;
> +
> +	base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	for (i = 0; i < ARRAY_SIZE(sels); i++) {
> +		if (sels[i].num_parents == 1) {
> +			hw = devm_clk_hw_register_gate_parent_data(dev,
> +								   sels[i].name,
> +								   &sels[i].parent,
> +								   0,
> +								   base + sels[i].reg,
> +								   sels[i].shift,
> +								   0, NULL);
> +		} else {
> +			hw = devm_clk_hw_register_mux_parent_data(dev,
> +								  sels[i].name,
> +								  sels[i].parents,
> +								  sels[i].num_parents,
> +								  0,
> +								  base + sels[i].reg,
> +								  sels[i].shift,
> +								  sels[i].width,
> +								  0, NULL);
> +		}
> +
> +		if (IS_ERR(hw))
> +			return PTR_ERR(hw);
> +
> +		priv->hws[sels[i].clkid] = hw;
> +	}
> +
> +	/* SAI PLL */
> +	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_ref_sel",
> +						  clk_imx8mp_audiomix_pll_parents,
> +						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
> +						  CLK_SET_RATE_NO_REPARENT,
> +						  base + SAI_PLL_GNRL_CTL,
> +						  0, 2, 0, NULL);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
> +
> +	hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
> +				    base + 0x400, &imx_1443x_pll);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
> +
> +	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_bypass",
> +						  clk_imx8mp_audiomix_pll_bypass_sels,
> +						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
> +						  CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> +						  base + SAI_PLL_GNRL_CTL,
> +						  16, 1, 0, NULL);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
> +
> +	hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
> +				       0, base + SAI_PLL_GNRL_CTL, 13,
> +				       0, NULL);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
> +
> +	hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
> +					       "sai_pll_out", 0, 1, 2);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> +					   priv);
> +}
> +
> +static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
> +	{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
> +
> +static struct platform_driver clk_imx8mp_audiomix_driver = {
> +	.probe	= clk_imx8mp_audiomix_probe,
> +	.driver = {
> +		.name = "imx8mp-audio-blk-ctrl",
> +		.of_match_table = clk_imx8mp_audiomix_of_match,
> +	},
> +};
> +
> +module_platform_driver(clk_imx8mp_audiomix_driver);
> +
> +MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
> +MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
> +MODULE_LICENSE("GPL");
> --
> 2.35.1
>

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 6/27/22 17:35, Abel Vesa wrote:
> On 22-06-25 03:32:32, Marek Vasut wrote:
>> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
>> series of clock gates and muxes. Model it as a large static table of
>> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
>> SAI PLL has to be registered separately.
>>
> 
> Again, there is a chance that the blk-ctrl driver might disable the PD
> from under this.

Can you elaborate a bit more on this ? How/why do you think so ?

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-06-27 18:23:33, Marek Vasut wrote:
> On 6/27/22 17:35, Abel Vesa wrote:
> > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> > > series of clock gates and muxes. Model it as a large static table of
> > > gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> > > SAI PLL has to be registered separately.
> > >
> >
> > Again, there is a chance that the blk-ctrl driver might disable the PD
> > from under this.
>
> Can you elaborate a bit more on this ? How/why do you think so ?

At some point, the PDs from the Audiomix IP block will be added to the
drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with the
same address range and the imx8mp-blk-ctrl also has runtime PM enabled.

My worry here is the possibility of imx8mp-blk-ctrl audiomix (when that
will be added) will mess with the PD leaving your clock provider driver
hanging.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 6/28/22 09:44, Abel Vesa wrote:
> On 22-06-27 18:23:33, Marek Vasut wrote:
>> On 6/27/22 17:35, Abel Vesa wrote:
>>> On 22-06-25 03:32:32, Marek Vasut wrote:
>>>> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
>>>> series of clock gates and muxes. Model it as a large static table of
>>>> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
>>>> SAI PLL has to be registered separately.
>>>>
>>>
>>> Again, there is a chance that the blk-ctrl driver might disable the PD
>>> from under this.
>>
>> Can you elaborate a bit more on this ? How/why do you think so ?
> 
> At some point, the PDs from the Audiomix IP block will be added to the
> drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with the
> same address range and the imx8mp-blk-ctrl also has runtime PM enabled.

Why would the PDs be added into the block control driver?

The audiomix is purely a clock mux driver, not really a block control 
driver providing PDs of its own.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-06-28 19:06:39, Marek Vasut wrote:
> On 6/28/22 09:44, Abel Vesa wrote:
> > On 22-06-27 18:23:33, Marek Vasut wrote:
> > > On 6/27/22 17:35, Abel Vesa wrote:
> > > > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > > > Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> > > > > series of clock gates and muxes. Model it as a large static table of
> > > > > gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> > > > > SAI PLL has to be registered separately.
> > > > >
> > > >
> > > > Again, there is a chance that the blk-ctrl driver might disable the PD
> > > > from under this.
> > >
> > > Can you elaborate a bit more on this ? How/why do you think so ?
> >
> > At some point, the PDs from the Audiomix IP block will be added to the
> > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with the
> > same address range and the imx8mp-blk-ctrl also has runtime PM enabled.
>
> Why would the PDs be added into the block control driver?
>
> The audiomix is purely a clock mux driver, not really a block control driver
> providing PDs of its own.

OK then, fine by me.

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RE: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Peng Fan]

> Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
> 
> On 6/28/22 09:44, Abel Vesa wrote:
> > On 22-06-27 18:23:33, Marek Vasut wrote:
> >> On 6/27/22 17:35, Abel Vesa wrote:
> >>> On 22-06-25 03:32:32, Marek Vasut wrote:
> >>>> Unlike the other block control IPs in i.MX8M, the audiomix is
> >>>> mostly a series of clock gates and muxes. Model it as a large
> >>>> static table of gates and muxes with one exception, which is the
> >>>> PLL14xx . The PLL14xx SAI PLL has to be registered separately.
> >>>>
> >>>
> >>> Again, there is a chance that the blk-ctrl driver might disable the
> >>> PD from under this.
> >>
> >> Can you elaborate a bit more on this ? How/why do you think so ?
> >
> > At some point, the PDs from the Audiomix IP block will be added to the
> > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
> > the same address range and the imx8mp-blk-ctrl also has runtime PM
> enabled.
> 
> Why would the PDs be added into the block control driver?
> 
> The audiomix is purely a clock mux driver, not really a block control driver
> providing PDs of its own.

I recalled that with with blk-ctrl working as clock provider, there is dead lock
issue, if the blk-ctrl node has a power-domain entry. Not very sure.

Regards,
Peng.
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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 8/4/22 11:13, Peng Fan wrote:
>> Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
>>
>> On 6/28/22 09:44, Abel Vesa wrote:
>>> On 22-06-27 18:23:33, Marek Vasut wrote:
>>>> On 6/27/22 17:35, Abel Vesa wrote:
>>>>> On 22-06-25 03:32:32, Marek Vasut wrote:
>>>>>> Unlike the other block control IPs in i.MX8M, the audiomix is
>>>>>> mostly a series of clock gates and muxes. Model it as a large
>>>>>> static table of gates and muxes with one exception, which is the
>>>>>> PLL14xx . The PLL14xx SAI PLL has to be registered separately.
>>>>>>
>>>>>
>>>>> Again, there is a chance that the blk-ctrl driver might disable the
>>>>> PD from under this.
>>>>
>>>> Can you elaborate a bit more on this ? How/why do you think so ?
>>>
>>> At some point, the PDs from the Audiomix IP block will be added to the
>>> drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
>>> the same address range and the imx8mp-blk-ctrl also has runtime PM
>> enabled.
>>
>> Why would the PDs be added into the block control driver?
>>
>> The audiomix is purely a clock mux driver, not really a block control driver
>> providing PDs of its own.
> 
> I recalled that with with blk-ctrl working as clock provider, there is dead lock
> issue, if the blk-ctrl node has a power-domain entry. Not very sure.

How can I verify that ? Lockdep ?

I run this series for months and haven't seen a lock up or splat.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-08-04 11:31:33, Marek Vasut wrote:
> On 8/4/22 11:13, Peng Fan wrote:
> > > Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
> > > 
> > > On 6/28/22 09:44, Abel Vesa wrote:
> > > > On 22-06-27 18:23:33, Marek Vasut wrote:
> > > > > On 6/27/22 17:35, Abel Vesa wrote:
> > > > > > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > > > > > Unlike the other block control IPs in i.MX8M, the audiomix is
> > > > > > > mostly a series of clock gates and muxes. Model it as a large
> > > > > > > static table of gates and muxes with one exception, which is the
> > > > > > > PLL14xx . The PLL14xx SAI PLL has to be registered separately.
> > > > > > > 
> > > > > > 
> > > > > > Again, there is a chance that the blk-ctrl driver might disable the
> > > > > > PD from under this.
> > > > > 
> > > > > Can you elaborate a bit more on this ? How/why do you think so ?
> > > > 
> > > > At some point, the PDs from the Audiomix IP block will be added to the
> > > > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
> > > > the same address range and the imx8mp-blk-ctrl also has runtime PM
> > > enabled.
> > > 
> > > Why would the PDs be added into the block control driver?
> > > 
> > > The audiomix is purely a clock mux driver, not really a block control driver
> > > providing PDs of its own.
> > 
> > I recalled that with with blk-ctrl working as clock provider, there is dead lock
> > issue, if the blk-ctrl node has a power-domain entry. Not very sure.
> 
> How can I verify that ? Lockdep ?
> 
> I run this series for months and haven't seen a lock up or splat.

Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
end up with an ABBA deadlock between genpd lock and clock prepare lock.

Have a read here:

https://lore.kernel.org/lkml/160453833813.3965362.13967343909525787375@swboyd.mtv.corp.google.com/T/#m0160265b0604ac8a524fedae7845e9f60bae67ef

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 8/11/22 16:20, Abel Vesa wrote:
> On 22-08-04 11:31:33, Marek Vasut wrote:
>> On 8/4/22 11:13, Peng Fan wrote:
>>>> Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
>>>>
>>>> On 6/28/22 09:44, Abel Vesa wrote:
>>>>> On 22-06-27 18:23:33, Marek Vasut wrote:
>>>>>> On 6/27/22 17:35, Abel Vesa wrote:
>>>>>>> On 22-06-25 03:32:32, Marek Vasut wrote:
>>>>>>>> Unlike the other block control IPs in i.MX8M, the audiomix is
>>>>>>>> mostly a series of clock gates and muxes. Model it as a large
>>>>>>>> static table of gates and muxes with one exception, which is the
>>>>>>>> PLL14xx . The PLL14xx SAI PLL has to be registered separately.
>>>>>>>>
>>>>>>>
>>>>>>> Again, there is a chance that the blk-ctrl driver might disable the
>>>>>>> PD from under this.
>>>>>>
>>>>>> Can you elaborate a bit more on this ? How/why do you think so ?
>>>>>
>>>>> At some point, the PDs from the Audiomix IP block will be added to the
>>>>> drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
>>>>> the same address range and the imx8mp-blk-ctrl also has runtime PM
>>>> enabled.
>>>>
>>>> Why would the PDs be added into the block control driver?
>>>>
>>>> The audiomix is purely a clock mux driver, not really a block control driver
>>>> providing PDs of its own.
>>>
>>> I recalled that with with blk-ctrl working as clock provider, there is dead lock
>>> issue, if the blk-ctrl node has a power-domain entry. Not very sure.
>>
>> How can I verify that ? Lockdep ?
>>
>> I run this series for months and haven't seen a lock up or splat.
> 
> Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
> end up with an ABBA deadlock between genpd lock and clock prepare lock.

Unlike the other mix drivers, this is a pure clock driver, not a power 
domain driver. The PD is already available to this clock driver, see:
[PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX

Can you please elaborate on the deadlock problem ?
Because really, I just don't see it.

Were you able to reproduce the deadlock with this driver ?

> Have a read here:
> 
> https://lore.kernel.org/lkml/160453833813.3965362.13967343909525787375@swboyd.mtv.corp.google.com/T/#m0160265b0604ac8a524fedae7845e9f60bae67ef

Which part of the lengthy thread do you refer to ? I suspect the 
'permalink' might help pointing to specific email in the thread.

Note that the aforementioned thread discusses the other mix drivers 
which are PDs, this driver is not, there is a difference.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-08-11 16:30:20, Marek Vasut wrote:
> On 8/11/22 16:20, Abel Vesa wrote:
> > On 22-08-04 11:31:33, Marek Vasut wrote:
> > > On 8/4/22 11:13, Peng Fan wrote:
> > > > > Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
> > > > > 
> > > > > On 6/28/22 09:44, Abel Vesa wrote:
> > > > > > On 22-06-27 18:23:33, Marek Vasut wrote:
> > > > > > > On 6/27/22 17:35, Abel Vesa wrote:
> > > > > > > > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > > > > > > > Unlike the other block control IPs in i.MX8M, the audiomix is
> > > > > > > > > mostly a series of clock gates and muxes. Model it as a large
> > > > > > > > > static table of gates and muxes with one exception, which is the
> > > > > > > > > PLL14xx . The PLL14xx SAI PLL has to be registered separately.
> > > > > > > > > 
> > > > > > > > 
> > > > > > > > Again, there is a chance that the blk-ctrl driver might disable the
> > > > > > > > PD from under this.
> > > > > > > 
> > > > > > > Can you elaborate a bit more on this ? How/why do you think so ?
> > > > > > 
> > > > > > At some point, the PDs from the Audiomix IP block will be added to the
> > > > > > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
> > > > > > the same address range and the imx8mp-blk-ctrl also has runtime PM
> > > > > enabled.
> > > > > 
> > > > > Why would the PDs be added into the block control driver?
> > > > > 
> > > > > The audiomix is purely a clock mux driver, not really a block control driver
> > > > > providing PDs of its own.
> > > > 
> > > > I recalled that with with blk-ctrl working as clock provider, there is dead lock
> > > > issue, if the blk-ctrl node has a power-domain entry. Not very sure.
> > > 
> > > How can I verify that ? Lockdep ?
> > > 
> > > I run this series for months and haven't seen a lock up or splat.
> > 
> > Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
> > end up with an ABBA deadlock between genpd lock and clock prepare lock.
> 
> Unlike the other mix drivers, this is a pure clock driver, not a power
> domain driver. The PD is already available to this clock driver, see:
> [PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX

When you will enable the runtime PM for this driver, the deadlock is
going to happen and it will be in some scenario like:
    clk_disable_unused_subtree
      -> clk_prepare (takes prepare lock) (for a clock from your driver)
	-> runtime pm (takes genpd lock)
	  -> clk_prepare (tries to take prepare lock again) (for the clock of the PD)

> 
> Can you please elaborate on the deadlock problem ?
> Because really, I just don't see it.
> 
> Were you able to reproduce the deadlock with this driver ?
> 
> > Have a read here:
> > 
> > https://lore.kernel.org/lkml/160453833813.3965362.13967343909525787375@swboyd.mtv.corp.google.com/T/#m0160265b0604ac8a524fedae7845e9f60bae67ef
> 
> Which part of the lengthy thread do you refer to ? I suspect the 'permalink'
> might help pointing to specific email in the thread.
> 
> Note that the aforementioned thread discusses the other mix drivers which
> are PDs, this driver is not, there is a difference.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-08-11 18:03:04, Abel Vesa wrote:
> On 22-08-11 16:30:20, Marek Vasut wrote:
> > On 8/11/22 16:20, Abel Vesa wrote:
> > > On 22-08-04 11:31:33, Marek Vasut wrote:
> > > > On 8/4/22 11:13, Peng Fan wrote:
> > > > > > Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
> > > > > > 
> > > > > > On 6/28/22 09:44, Abel Vesa wrote:
> > > > > > > On 22-06-27 18:23:33, Marek Vasut wrote:
> > > > > > > > On 6/27/22 17:35, Abel Vesa wrote:
> > > > > > > > > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > > > > > > > > Unlike the other block control IPs in i.MX8M, the audiomix is
> > > > > > > > > > mostly a series of clock gates and muxes. Model it as a large
> > > > > > > > > > static table of gates and muxes with one exception, which is the
> > > > > > > > > > PLL14xx . The PLL14xx SAI PLL has to be registered separately.
> > > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > Again, there is a chance that the blk-ctrl driver might disable the
> > > > > > > > > PD from under this.
> > > > > > > > 
> > > > > > > > Can you elaborate a bit more on this ? How/why do you think so ?
> > > > > > > 
> > > > > > > At some point, the PDs from the Audiomix IP block will be added to the
> > > > > > > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
> > > > > > > the same address range and the imx8mp-blk-ctrl also has runtime PM
> > > > > > enabled.
> > > > > > 
> > > > > > Why would the PDs be added into the block control driver?
> > > > > > 
> > > > > > The audiomix is purely a clock mux driver, not really a block control driver
> > > > > > providing PDs of its own.
> > > > > 
> > > > > I recalled that with with blk-ctrl working as clock provider, there is dead lock
> > > > > issue, if the blk-ctrl node has a power-domain entry. Not very sure.
> > > > 
> > > > How can I verify that ? Lockdep ?
> > > > 
> > > > I run this series for months and haven't seen a lock up or splat.
> > > 
> > > Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
> > > end up with an ABBA deadlock between genpd lock and clock prepare lock.
> > 
> > Unlike the other mix drivers, this is a pure clock driver, not a power
> > domain driver. The PD is already available to this clock driver, see:
> > [PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
> 
> When you will enable the runtime PM for this driver, the deadlock is
> going to happen and it will be in some scenario like:
>     clk_disable_unused_subtree
>       -> clk_prepare (takes prepare lock) (for a clock from your driver)
> 	-> runtime pm (takes genpd lock)
> 	  -> clk_prepare (tries to take prepare lock again) (for the clock of the PD)
> 

Actually, I'm wrong, that is not a deadlock, but this one is:

[   11.667711][  T108] -> #1 (&genpd->mlock){+.+.}-{3:3}:
[   11.675041][  T108]        __lock_acquire+0xae4/0xef8
[   11.680093][  T108]        lock_acquire+0xfc/0x2f8
[   11.684888][  T108]        __mutex_lock+0x90/0x870
[   11.689685][  T108]        mutex_lock_nested+0x44/0x50
[   11.694826][  T108]        genpd_lock_mtx+0x18/0x24
[   11.699706][  T108]        genpd_runtime_resume+0x90/0x214 (hold genpd->mlock)
[   11.705194][  T108]        __rpm_callback+0x80/0x2c0
[   11.710160][  T108]        rpm_resume+0x468/0x650
[   11.714866][  T108]        __pm_runtime_resume+0x60/0x88
[   11.720180][  T108]        clk_pm_runtime_get+0x28/0x9c
[   11.725410][  T108]        clk_disable_unused_subtree+0x8c/0x144
[   11.731420][  T108]        clk_disable_unused_subtree+0x124/0x144
[   11.737518][  T108]        clk_disable_unused+0xa4/0x11c (hold prepare_lock)
[   11.742833][  T108]        do_one_initcall+0x98/0x178
[   11.747888][  T108]        do_initcall_level+0x9c/0xb8
[   11.753028][  T108]        do_initcalls+0x54/0x94
[   11.757736][  T108]        do_basic_setup+0x24/0x30
[   11.762614][  T108]        kernel_init_freeable+0x70/0xa4
[   11.768014][  T108]        kernel_init+0x14/0x18c
[   11.772722][  T108]        ret_from_fork+0x10/0x18

[   11.777512][  T108] -> #0 (prepare_lock){+.+.}-{3:3}:
[   11.784749][  T108]        check_noncircular+0x134/0x13c
[   11.790064][  T108]        validate_chain+0x590/0x2a04
[   11.795204][  T108]        __lock_acquire+0xae4/0xef8
[   11.800258][  T108]        lock_acquire+0xfc/0x2f8
[   11.805050][  T108]        __mutex_lock+0x90/0x870
[   11.809841][  T108]        mutex_lock_nested+0x44/0x50
[   11.814983][  T108]        clk_unprepare+0x5c/0x100 ((hold prepare_lock))
[   11.819864][  T108]        imx8m_pd_power_off+0xac/0x110
[   11.825179][  T108]        genpd_power_off+0x1b4/0x2dc
[   11.830318][  T108]        genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock)
[   11.835981][  T108]        process_one_work+0x270/0x444
[   11.841208][  T108]        worker_thread+0x280/0x4e4
[   11.846176][  T108]        kthread+0x13c/0x14

All it needs is the runtime PM in your current driver.

Bottom line is, we cannot have clock providers that have PDs that have
in turn their own clocks.

So we need to drop the blk_ctrl as clock providers and go with Lucas's
approach.

> > 
> > Can you please elaborate on the deadlock problem ?
> > Because really, I just don't see it.
> > 
> > Were you able to reproduce the deadlock with this driver ?
> > 
> > > Have a read here:
> > > 
> > > https://lore.kernel.org/lkml/160453833813.3965362.13967343909525787375@swboyd.mtv.corp.google.com/T/#m0160265b0604ac8a524fedae7845e9f60bae67ef
> > 
> > Which part of the lengthy thread do you refer to ? I suspect the 'permalink'
> > might help pointing to specific email in the thread.
> > 
> > Note that the aforementioned thread discusses the other mix drivers which
> > are PDs, this driver is not, there is a difference.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 8/11/22 17:03, Abel Vesa wrote:
> On 22-08-11 16:30:20, Marek Vasut wrote:
>> On 8/11/22 16:20, Abel Vesa wrote:
>>> On 22-08-04 11:31:33, Marek Vasut wrote:
>>>> On 8/4/22 11:13, Peng Fan wrote:
>>>>>> Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
>>>>>>
>>>>>> On 6/28/22 09:44, Abel Vesa wrote:
>>>>>>> On 22-06-27 18:23:33, Marek Vasut wrote:
>>>>>>>> On 6/27/22 17:35, Abel Vesa wrote:
>>>>>>>>> On 22-06-25 03:32:32, Marek Vasut wrote:
>>>>>>>>>> Unlike the other block control IPs in i.MX8M, the audiomix is
>>>>>>>>>> mostly a series of clock gates and muxes. Model it as a large
>>>>>>>>>> static table of gates and muxes with one exception, which is the
>>>>>>>>>> PLL14xx . The PLL14xx SAI PLL has to be registered separately.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Again, there is a chance that the blk-ctrl driver might disable the
>>>>>>>>> PD from under this.
>>>>>>>>
>>>>>>>> Can you elaborate a bit more on this ? How/why do you think so ?
>>>>>>>
>>>>>>> At some point, the PDs from the Audiomix IP block will be added to the
>>>>>>> drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
>>>>>>> the same address range and the imx8mp-blk-ctrl also has runtime PM
>>>>>> enabled.
>>>>>>
>>>>>> Why would the PDs be added into the block control driver?
>>>>>>
>>>>>> The audiomix is purely a clock mux driver, not really a block control driver
>>>>>> providing PDs of its own.
>>>>>
>>>>> I recalled that with with blk-ctrl working as clock provider, there is dead lock
>>>>> issue, if the blk-ctrl node has a power-domain entry. Not very sure.
>>>>
>>>> How can I verify that ? Lockdep ?
>>>>
>>>> I run this series for months and haven't seen a lock up or splat.
>>>
>>> Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
>>> end up with an ABBA deadlock between genpd lock and clock prepare lock.
>>
>> Unlike the other mix drivers, this is a pure clock driver, not a power
>> domain driver. The PD is already available to this clock driver, see:
>> [PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
> 
> When you will enable the runtime PM for this driver, the deadlock is
> going to happen and it will be in some scenario like:
>      clk_disable_unused_subtree
>        -> clk_prepare (takes prepare lock) (for a clock from your driver)
> 	-> runtime pm (takes genpd lock)
> 	  -> clk_prepare (tries to take prepare lock again) (for the clock of the PD)

Since you seem to have a test case, can you share the test case, 
verbatim, so I can reproduce it locally ?

I seem to be asking for that repeatedly and I am not getting any clear 
answer.

>> Can you please elaborate on the deadlock problem ?
>> Because really, I just don't see it.
>>
>> Were you able to reproduce the deadlock with this driver ?

[...]

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-08-11 18:38:49, Marek Vasut wrote:
> On 8/11/22 17:03, Abel Vesa wrote:
> > On 22-08-11 16:30:20, Marek Vasut wrote:
> > > On 8/11/22 16:20, Abel Vesa wrote:
> > > > On 22-08-04 11:31:33, Marek Vasut wrote:
> > > > > On 8/4/22 11:13, Peng Fan wrote:
> > > > > > > Subject: Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control
> > > > > > > 
> > > > > > > On 6/28/22 09:44, Abel Vesa wrote:
> > > > > > > > On 22-06-27 18:23:33, Marek Vasut wrote:
> > > > > > > > > On 6/27/22 17:35, Abel Vesa wrote:
> > > > > > > > > > On 22-06-25 03:32:32, Marek Vasut wrote:
> > > > > > > > > > > Unlike the other block control IPs in i.MX8M, the audiomix is
> > > > > > > > > > > mostly a series of clock gates and muxes. Model it as a large
> > > > > > > > > > > static table of gates and muxes with one exception, which is the
> > > > > > > > > > > PLL14xx . The PLL14xx SAI PLL has to be registered separately.
> > > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > Again, there is a chance that the blk-ctrl driver might disable the
> > > > > > > > > > PD from under this.
> > > > > > > > > 
> > > > > > > > > Can you elaborate a bit more on this ? How/why do you think so ?
> > > > > > > > 
> > > > > > > > At some point, the PDs from the Audiomix IP block will be added to the
> > > > > > > > drivers/soc/imx/imx8mp-blk-ctrl.c. Then, you'll have 2 drivers with
> > > > > > > > the same address range and the imx8mp-blk-ctrl also has runtime PM
> > > > > > > enabled.
> > > > > > > 
> > > > > > > Why would the PDs be added into the block control driver?
> > > > > > > 
> > > > > > > The audiomix is purely a clock mux driver, not really a block control driver
> > > > > > > providing PDs of its own.
> > > > > > 
> > > > > > I recalled that with with blk-ctrl working as clock provider, there is dead lock
> > > > > > issue, if the blk-ctrl node has a power-domain entry. Not very sure.
> > > > > 
> > > > > How can I verify that ? Lockdep ?
> > > > > 
> > > > > I run this series for months and haven't seen a lock up or splat.
> > > > 
> > > > Audiomix (and every mix actually) has a PD. Once you add the PD, you'll
> > > > end up with an ABBA deadlock between genpd lock and clock prepare lock.
> > > 
> > > Unlike the other mix drivers, this is a pure clock driver, not a power
> > > domain driver. The PD is already available to this clock driver, see:
> > > [PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX
> > 
> > When you will enable the runtime PM for this driver, the deadlock is
> > going to happen and it will be in some scenario like:
> >      clk_disable_unused_subtree
> >        -> clk_prepare (takes prepare lock) (for a clock from your driver)
> > 	-> runtime pm (takes genpd lock)
> > 	  -> clk_prepare (tries to take prepare lock again) (for the clock of the PD)
> 
> Since you seem to have a test case, can you share the test case, verbatim,
> so I can reproduce it locally ?

I do not have a test case, but we do have a prior experience with this
happening.

> 
> I seem to be asking for that repeatedly and I am not getting any clear
> answer.

I do not have a board to test on anymore.

But anyway, lets apply it and if there is a problem, we can figure it
out later.

> 
> > > Can you please elaborate on the deadlock problem ?
> > > Because really, I just don't see it.
> > > 
> > > Were you able to reproduce the deadlock with this driver ?
> 
> [...]

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Abel Vesa]

On 22-06-25 03:32:32, Marek Vasut wrote:
> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> series of clock gates and muxes. Model it as a large static table of
> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> SAI PLL has to be registered separately.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-imx@nxp.com

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

> ---
> V2: No change
> V3: - Use devm_platform_ioremap_resource
>     - Use clk_hw_onecell_data instead of clk_imx8mp_audiomix_priv
>     - Include mod_devicetable.h for of_device_id struct
>     - Use struct clk_parent_data instead of string parent_name
> ---
>  drivers/clk/imx/Makefile              |   2 +-
>  drivers/clk/imx/clk-imx8mp-audiomix.c | 286 ++++++++++++++++++++++++++
>  2 files changed, 287 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/imx/clk-imx8mp-audiomix.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 88b9b9285d22e..c4290937637eb 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -25,7 +25,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
>
>  obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
>  obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
> -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
> +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
>  obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
>
>  obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
> diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
> new file mode 100644
> index 0000000000000..2d5d8255c7fa2
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Driver for i.MX8M Plus Audio BLK_CTRL
> + *
> + * Copyright (C) 2022 Marek Vasut <marex@denx.de>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +
> +#include "clk.h"
> +
> +#define CLKEN0			0x000
> +#define CLKEN1			0x004
> +#define SAI_MCLK_SEL(n)		(300 + 4 * (n))	/* n in 0..5 */
> +#define PDM_SEL			0x318
> +#define SAI_PLL_GNRL_CTL	0x400
> +
> +#define SAIn_MCLK1_PARENT(n)						\
> +static const struct clk_parent_data					\
> +clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = {			\
> +	{								\
> +		.fw_name = "sai"__stringify(n),				\
> +		.name = "sai"__stringify(n)				\
> +	}, {								\
> +		.fw_name = "sai"__stringify(n)"_mclk",			\
> +		.name = "sai"__stringify(n)"_mclk"			\
> +	},								\
> +}
> +
> +SAIn_MCLK1_PARENT(1);
> +SAIn_MCLK1_PARENT(2);
> +SAIn_MCLK1_PARENT(3);
> +SAIn_MCLK1_PARENT(5);
> +SAIn_MCLK1_PARENT(6);
> +SAIn_MCLK1_PARENT(7);
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
> +	{ .fw_name = "sai1", .name = "sai1" },
> +	{ .fw_name = "sai2", .name = "sai2" },
> +	{ .fw_name = "sai3", .name = "sai3" },
> +	{ .name = "dummy" },
> +	{ .fw_name = "sai5", .name = "sai5" },
> +	{ .fw_name = "sai6", .name = "sai6" },
> +	{ .fw_name = "sai7", .name = "sai7" },
> +	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
> +	{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
> +	{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
> +	{ .name = "dummy" },
> +	{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
> +	{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
> +	{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
> +	{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
> +	{ .name = "dummy" },
> +};
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
> +	{ .fw_name = "pdm", .name = "pdm" },
> +	{ .name = "sai_pll_out_div2" },
> +	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
> +	{ .name = "dummy" },
> +};
> +
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
> +	{ .fw_name = "osc_24m", .name = "osc_24m" },
> +	{ .name = "dummy" },
> +	{ .name = "dummy" },
> +	{ .name = "dummy" },
> +};
> +
> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
> +	{ .fw_name = "sai_pll", .name = "sai_pll" },
> +	{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
> +};
> +
> +#define CLK_GATE(gname, cname)						\
> +	{								\
> +		gname"_cg",						\
> +		IMX8MP_CLK_AUDIOMIX_##cname,				\
> +		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
> +		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
> +		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
> +	}
> +
> +#define CLK_SAIn(n)							\
> +	{								\
> +		"sai"__stringify(n)"_mclk1_sel",			\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {},		\
> +		clk_imx8mp_audiomix_sai##n##_mclk1_parents,		\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
> +		SAI_MCLK_SEL(n), 1, 0					\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk2_sel",			\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {},		\
> +		clk_imx8mp_audiomix_sai_mclk2_parents,			\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents),	\
> +		SAI_MCLK_SEL(n), 4, 1					\
> +	}, {								\
> +		"sai"__stringify(n)"_ipg_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG,			\
> +		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk1_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1,			\
> +		{							\
> +			.fw_name = "sai"__stringify(n)"_mclk1_sel",	\
> +			.name = "sai"__stringify(n)"_mclk1_sel"		\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk2_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2,			\
> +		{							\
> +			.fw_name = "sai"__stringify(n)"_mclk2_sel",	\
> +			.name = "sai"__stringify(n)"_mclk2_sel"		\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2		\
> +	}, {								\
> +		"sai"__stringify(n)"_mclk3_cg",				\
> +		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3,			\
> +		{							\
> +			.fw_name = "sai_pll_out_div2",			\
> +			.name = "sai_pll_out_div2"			\
> +		}, NULL, 1,						\
> +		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3		\
> +	}
> +
> +#define CLK_PDM								\
> +	{								\
> +		"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {},		\
> +		clk_imx8mp_audiomix_pdm_parents,			\
> +		ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents),		\
> +		PDM_SEL, 2, 0						\
> +	}
> +
> +struct clk_imx8mp_audiomix_sel {
> +	const char			*name;
> +	int				clkid;
> +	const struct clk_parent_data	parent;		/* For gate */
> +	const struct clk_parent_data	*parents;	/* For mux */
> +	int				num_parents;
> +	u16				reg;
> +	u8				width;
> +	u8				shift;
> +};
> +
> +static struct clk_imx8mp_audiomix_sel sels[] = {
> +	CLK_GATE("asrc", ASRC_IPG),
> +	CLK_GATE("pdm", PDM_IPG),
> +	CLK_GATE("earc", EARC_IPG),
> +	CLK_GATE("ocrama", OCRAMA_IPG),
> +	CLK_GATE("aud2htx", AUD2HTX_IPG),
> +	CLK_GATE("earc_phy", EARC_PHY),
> +	CLK_GATE("sdma2", SDMA2_ROOT),
> +	CLK_GATE("sdma3", SDMA3_ROOT),
> +	CLK_GATE("spba2", SPBA2_ROOT),
> +	CLK_GATE("dsp", DSP_ROOT),
> +	CLK_GATE("dspdbg", DSPDBG_ROOT),
> +	CLK_GATE("edma", EDMA_ROOT),
> +	CLK_GATE("audpll", AUDPLL_ROOT),
> +	CLK_GATE("mu2", MU2_ROOT),
> +	CLK_GATE("mu3", MU3_ROOT),
> +	CLK_PDM,
> +	CLK_SAIn(1),
> +	CLK_SAIn(2),
> +	CLK_SAIn(3),
> +	CLK_SAIn(5),
> +	CLK_SAIn(6),
> +	CLK_SAIn(7)
> +};
> +
> +static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> +{
> +	struct clk_hw_onecell_data *priv;
> +	struct device *dev = &pdev->dev;
> +	void __iomem *base;
> +	struct clk_hw *hw;
> +	int i;
> +
> +	priv = devm_kzalloc(dev,
> +			    struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
> +			    GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->num = IMX8MP_CLK_AUDIOMIX_END;
> +
> +	base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	for (i = 0; i < ARRAY_SIZE(sels); i++) {
> +		if (sels[i].num_parents == 1) {
> +			hw = devm_clk_hw_register_gate_parent_data(dev,
> +								   sels[i].name,
> +								   &sels[i].parent,
> +								   0,
> +								   base + sels[i].reg,
> +								   sels[i].shift,
> +								   0, NULL);
> +		} else {
> +			hw = devm_clk_hw_register_mux_parent_data(dev,
> +								  sels[i].name,
> +								  sels[i].parents,
> +								  sels[i].num_parents,
> +								  0,
> +								  base + sels[i].reg,
> +								  sels[i].shift,
> +								  sels[i].width,
> +								  0, NULL);
> +		}
> +
> +		if (IS_ERR(hw))
> +			return PTR_ERR(hw);
> +
> +		priv->hws[sels[i].clkid] = hw;
> +	}
> +
> +	/* SAI PLL */
> +	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_ref_sel",
> +						  clk_imx8mp_audiomix_pll_parents,
> +						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
> +						  CLK_SET_RATE_NO_REPARENT,
> +						  base + SAI_PLL_GNRL_CTL,
> +						  0, 2, 0, NULL);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
> +
> +	hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
> +				    base + 0x400, &imx_1443x_pll);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
> +
> +	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_bypass",
> +						  clk_imx8mp_audiomix_pll_bypass_sels,
> +						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
> +						  CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> +						  base + SAI_PLL_GNRL_CTL,
> +						  16, 1, 0, NULL);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
> +
> +	hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
> +				       0, base + SAI_PLL_GNRL_CTL, 13,
> +				       0, NULL);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
> +
> +	hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
> +					       "sai_pll_out", 0, 1, 2);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> +					   priv);
> +}
> +
> +static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
> +	{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
> +
> +static struct platform_driver clk_imx8mp_audiomix_driver = {
> +	.probe	= clk_imx8mp_audiomix_probe,
> +	.driver = {
> +		.name = "imx8mp-audio-blk-ctrl",
> +		.of_match_table = clk_imx8mp_audiomix_of_match,
> +	},
> +};
> +
> +module_platform_driver(clk_imx8mp_audiomix_driver);
> +
> +MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
> +MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
> +MODULE_LICENSE("GPL");
> --
> 2.35.1
>

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 10/14/22 03:53, Shengjiu Wang wrote:
> Hi Marek

Hi,

[...]

>> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
>> +       { .fw_name = "osc_24m", .name = "osc_24m" },
>> +       { .name = "dummy" },
>> +       { .name = "dummy" },
>> +       { .name = "dummy" },
>> +};
>> +
>> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[]
>> = {
>> +       { .fw_name = "sai_pll", .name = "sai_pll" },
>> +       { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
>> +};
>> +
>> +#define CLK_GATE(gname, cname)                                         \
>> +       {                                                               \
>> +               gname"_cg",                                             \
>> +               IMX8MP_CLK_AUDIOMIX_##cname,                            \
>> +               { .fw_name = "ahb", .name = "ahb" }, NULL, 1,           \
>>
>> { .fw_name = "audio_root_clk", .name = "audio_root_clk" }, NULL, 1,
>>       \
>>
>> Should be the 'audio_root_clk' better?
>>
>> Then the 'clocks' and 'clock-names' can be removed in dts node?
>>
>> Will you continue to follow up this patch series?

Sure. Did anyone from NXP finally test this patch series, and can 
provide useful review ?

I am somewhat unhappy with the feedback I got thus far, which is based 
on downstream kernel fork, different power domain driver and different 
audiomix driver. I would really appreciate feedback for THIS driver instead.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 10/20/22 05:06, Shengjiu Wang wrote:
> On Wed, Oct 19, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> 
>> On 10/14/22 03:53, Shengjiu Wang wrote:
>>> Hi Marek
>>
>> Hi,
>>
>> [...]
>>
>>>> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[]
>> = {
>>>> +       { .fw_name = "osc_24m", .name = "osc_24m" },
>>>> +       { .name = "dummy" },
>>>> +       { .name = "dummy" },
>>>> +       { .name = "dummy" },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data
>> clk_imx8mp_audiomix_pll_bypass_sels[]
>>>> = {
>>>> +       { .fw_name = "sai_pll", .name = "sai_pll" },
>>>> +       { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
>>>> +};
>>>> +
>>>> +#define CLK_GATE(gname, cname)
>>   \
>>>> +       {
>>   \
>>>> +               gname"_cg",
>>   \
>>>> +               IMX8MP_CLK_AUDIOMIX_##cname,
>> \
>>>> +               { .fw_name = "ahb", .name = "ahb" }, NULL, 1,
>>   \
>>>>
>>>> { .fw_name = "audio_root_clk", .name = "audio_root_clk" }, NULL, 1,
>>>>        \
>>>>
>>>> Should be the 'audio_root_clk' better?
>>>>
>>>> Then the 'clocks' and 'clock-names' can be removed in dts node?
>>>>
>>>> Will you continue to follow up this patch series?
>>
>> Sure. Did anyone from NXP finally test this patch series, and can
>> provide useful review ?
>>
> 
> I have tested it, and I think "ahb" should be "audio_root_clk". others LGTM.

It seems those clock are actually called IMX8MP_CLK_AUDIO_AHB_ROOT in 
the NXP downstream BSP, so those clock do drive AHB, correct ? If so, we 
should keep the "ahb" name here, to differentiate them from already 
existing IMX8MP_CLK_AUDIO_AXI , which seem to drive the AXI part.

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Marek Vasut]

On 10/26/22 12:36, Shengjiu Wang wrote:
> Hi Marek
> 
> On Wed, Oct 26, 2022 at 5:10 AM Marek Vasut <marex@denx.de> wrote:
> 
>> On 10/20/22 05:06, Shengjiu Wang wrote:
>>> On Wed, Oct 19, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>>
>>>> On 10/14/22 03:53, Shengjiu Wang wrote:
>>>>> Hi Marek
>>>>
>>>> Hi,
>>>>
>>>> [...]
>>>>
>>>>>> +static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[]
>>>> = {
>>>>>> +       { .fw_name = "osc_24m", .name = "osc_24m" },
>>>>>> +       { .name = "dummy" },
>>>>>> +       { .name = "dummy" },
>>>>>> +       { .name = "dummy" },
>>>>>> +};
>>>>>> +
>>>>>> +static const struct clk_parent_data
>>>> clk_imx8mp_audiomix_pll_bypass_sels[]
>>>>>> = {
>>>>>> +       { .fw_name = "sai_pll", .name = "sai_pll" },
>>>>>> +       { .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
>>>>>> +};
>>>>>> +
>>>>>> +#define CLK_GATE(gname, cname)
>>>>    \
>>>>>> +       {
>>>>    \
>>>>>> +               gname"_cg",
>>>>    \
>>>>>> +               IMX8MP_CLK_AUDIOMIX_##cname,
>>>> \
>>>>>> +               { .fw_name = "ahb", .name = "ahb" }, NULL, 1,
>>>>    \
>>>>>>
>>>>>> { .fw_name = "audio_root_clk", .name = "audio_root_clk" }, NULL, 1,
>>>>>>         \
>>>>>>
>>>>>> Should be the 'audio_root_clk' better?
>>>>>>
>>>>>> Then the 'clocks' and 'clock-names' can be removed in dts node?
>>>>>>
>>>>>> Will you continue to follow up this patch series?
>>>>
>>>> Sure. Did anyone from NXP finally test this patch series, and can
>>>> provide useful review ?
>>>>
>>>
>>> I have tested it, and I think "ahb" should be "audio_root_clk". others
>> LGTM.
>>
>> It seems those clock are actually called IMX8MP_CLK_AUDIO_AHB_ROOT in
>> the NXP downstream BSP, so those clock do drive AHB, correct ? If so, we
>> should keep the "ahb" name here, to differentiate them from already
>> existing IMX8MP_CLK_AUDIO_AXI , which seem to drive the AXI part.
>>
> 
> Seems IMX8MP_CLK_AUDIO_ROOT needs to be changed to
> IMX8MP_CLK_AUDIO_AHB_ROOT in clk-imx8mp.c
> 
> and
> "ocrama"  parent clock is "audio_axi_root"
> "earc_phy"  parent clock is "sai_pll_out_div2"
> "dsp" parent clock is "audio_axi_root"
> "dspdbg" parent clock is "audio_axi_root"
> "audpll" parent clock is "osc_24m"
> 
> so I think it is better to include downstream change in this patch
> series:
> -       hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk",
> "ipg_root", ccm_base + 0x4650, 0);
> +
> +       hws[IMX8MP_CLK_AUDIO_AHB_ROOT] =
> imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650,
> 0, &share_count_audio);
> +       hws[IMX8MP_CLK_AUDIO_AXI_ROOT] =
> imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650,
> 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root",
> "sai1", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root",
> "sai2", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root",
> "sai3", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root",
> "sai5", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root",
> "sai6", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root",
> "sai7", ccm_base + 0x4650, 0, &share_count_audio);
> +       hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root",
> "pdm", ccm_base + 0x4650, 0, &share_count_audio);
> 

Can you prepare such a clock rename patch and submit it ?

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Re: [PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Luca Ceresoli]

Hi Marek,

On Sat, 25 Jun 2022 03:32:32 +0200
Marek Vasut <marex@denx.de> wrote:

> Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
> series of clock gates and muxes. Model it as a large static table of
> gates and muxes with one exception, which is the PLL14xx . The PLL14xx
> SAI PLL has to be registered separately.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-imx@nxp.com

[Tested on MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM]
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[PATCH v3 4/6] dt-bindings: clock: imx8mp: Add audiomix block control

[Marek Vasut]

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Add DT bindings for this IP.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V2: No change
V3: - Add missed RB from Rob from V1
    - Rename audio_ahb to plain ahb
---
 .../bindings/clock/imx8mp-audiomix.yaml       | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
new file mode 100644
index 0000000000000..01b4e1e311cef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP AudioMIX Block Control Binding
+
+maintainers:
+  - Marek Vasut <marex@denx.de>
+
+description: |
+  NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
+  used to control Audio related clock on the SoC.
+
+properties:
+  compatible:
+    const: fsl,imx8mp-audio-blk-ctrl
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  power-domain-names:
+    const: audio
+
+  clocks:
+    minItems: 7
+    maxItems: 7
+
+  clock-names:
+    items:
+      - const: ahb
+      - const: sai1
+      - const: sai2
+      - const: sai3
+      - const: sai5
+      - const: sai6
+      - const: sai7
+
+  '#clock-cells':
+    const: 1
+    description:
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
+      for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  # Clock Control Module node:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+
+    clock-controller@30e20000 {
+        #clock-cells = <1>;
+        compatible = "fsl,imx8mp-audio-blk-ctrl";
+        clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+                 <&clk IMX8MP_CLK_SAI1>,
+                 <&clk IMX8MP_CLK_SAI2>,
+                 <&clk IMX8MP_CLK_SAI3>,
+                 <&clk IMX8MP_CLK_SAI5>,
+                 <&clk IMX8MP_CLK_SAI6>,
+                 <&clk IMX8MP_CLK_SAI7>;
+        clock-names = "ahb",
+                      "sai1", "sai2", "sai3",
+                      "sai5", "sai6", "sai7";
+        power-domains = <&pgc_audio>;
+        power-domain-names = "audio";
+        reg = <0x30e20000 0x10000>;
+    };
+
+...
-- 
2.35.1


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[PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX

[Marek Vasut]

Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
needed to get audio operational on i.MX8MP .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V2: - Add AUDIO_AXI clock to audio gpc
    - Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock
V3: Rename audio_ahb to plain ahb
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 153 ++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 8c76725e3d20d..9bf60a1863757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -551,6 +551,13 @@ pgc_usb2_phy: power-domain@3 {
 						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
 					};
 
+					pgc_audio: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
+						clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+							 <&clk IMX8MP_CLK_AUDIO_AXI>;
+					};
+
 					pgc_gpu2d: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@@ -1044,6 +1051,152 @@ eqos: ethernet@30bf0000 {
 			};
 		};
 
+		aips5: bus@30c00000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30c00000 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			spba-bus@30c00000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				reg = <0x30c00000 0x100000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				sai1: sai@30c10000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c10000 0x10000>;
+					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai2: sai@30c20000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c20000 0x10000>;
+					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai3: sai@30c30000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c30000 0x10000>;
+					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai5: sai@30c50000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c50000 0x10000>;
+					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai6: sai@30c60000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c60000 0x10000>;
+					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai7: sai@30c80000 {
+					compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+					reg = <0x30c80000 0x10000>;
+					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
+						 <&clk IMX8MP_CLK_DUMMY>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
+						 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
+					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+			};
+
+			sdma3: dma-controller@30e00000 {
+				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+				reg = <0x30e00000 0x10000>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
+					 <&clk IMX8MP_CLK_AUDIO_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			sdma2: dma-controller@30e10000 {
+				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+				reg = <0x30e10000 0x10000>;
+				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
+					 <&clk IMX8MP_CLK_AUDIO_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			audio_blk_ctrl: blk-ctrl@30e20000 {
+				#clock-cells = <1>;
+				compatible = "fsl,imx8mp-audio-blk-ctrl";
+				clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+					 <&clk IMX8MP_CLK_SAI1>,
+					 <&clk IMX8MP_CLK_SAI2>,
+					 <&clk IMX8MP_CLK_SAI3>,
+					 <&clk IMX8MP_CLK_SAI5>,
+					 <&clk IMX8MP_CLK_SAI6>,
+					 <&clk IMX8MP_CLK_SAI7>;
+				clock-names = "ahb",
+					      "sai1", "sai2", "sai3",
+					      "sai5", "sai6", "sai7";
+				power-domains = <&pgc_audio>;
+				power-domain-names = "audio";
+				reg = <0x30e20000 0x10000>;
+			};
+		};
+
 		aips4: bus@32c00000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x32c00000 0x400000>;
-- 
2.35.1


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Re: [PATCH v3 5/6] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX

[Luca Ceresoli]

Hi Marek,

On Sat, 25 Jun 2022 03:32:34 +0200
Marek Vasut <marex@denx.de> wrote:

> Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is
> needed to get audio operational on i.MX8MP .
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-imx@nxp.com

Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
[Tested on MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM]
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>


-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[PATCH v3 6/6] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK

[Marek Vasut]

Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
This is all that is needed to get analog audio output operational
on i.MX8MP EVK.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
---
V2: No change
V3: No change
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 60 ++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 2627d25ce7958..99731aaa3bcfb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -40,6 +40,16 @@ pcie0_refclk: pcie0-refclk {
 			clock-frequency = <100000000>;
 	};
 
+	reg_audio_pwr: regulator-audio-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "audio-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
 	reg_can1_stby: regulator-can1-stby {
 		compatible = "regulator-fixed";
 		regulator-name = "can1-stby";
@@ -83,6 +93,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	sound-wm8960 {
+		compatible = "fsl,imx-audio-wm8960";
+		model = "wm8960-audio";
+		audio-cpu = <&sai3>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HP_L",
+			"Headphone Jack", "HP_R",
+			"Ext Spk", "SPK_LP",
+			"Ext Spk", "SPK_LN",
+			"Ext Spk", "SPK_RP",
+			"Ext Spk", "SPK_RN",
+			"LINPUT1", "Mic Jack",
+			"LINPUT3", "Mic Jack",
+			"Mic Jack", "MICB";
+	};
 };
 
 &A53_0 {
@@ -333,6 +360,17 @@ &i2c3 {
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
 
+	codec: wm8960@1a {
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
+		clock-names = "mclk";
+		wlf,shared-lrclk;
+		wlf,hp-cfg = <3 2 3>;
+		wlf,gpio-cfg = <1 3>;
+		SPKVDD1-supply = <&reg_audio_pwr>;
+	};
+
 	pca6416: gpio@20 {
 		compatible = "ti,tca6416";
 		reg = <0x20>;
@@ -402,6 +440,16 @@ &pcie{
 	status = "okay";
 };
 
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <12288000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -594,6 +642,18 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
 		>;
 	};
 
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0xd6
+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0xd6
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
-- 
2.35.1


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Re: [PATCH v3 6/6] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK

[Luca Ceresoli]

Hello Marek,

On Sat, 25 Jun 2022 03:32:35 +0200
Marek Vasut <marex@denx.de> wrote:

> Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
> This is all that is needed to get analog audio output operational
> on i.MX8MP EVK.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Jacky Bai <ping.bai@nxp.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-imx@nxp.com

I'm sending in reply to this e-mail the device tree patch I have used
for my audio testing on the MSC SM2-MB-EP1 board. Feel free to add it to
your series if you want, it obviously depends on it.

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Luca Ceresoli]

The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
NXPP SGTL5000 audio codec connected to I2S-0 (sai2).

This requires to:

 * add the power supplies (always on)
 * enable sai2 with pinmuxes
 * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
   IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
 .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
index 470ff8e31e32..894d9809f76d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
@@ -14,6 +14,57 @@ / {
 	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
 		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
 		     "fsl,imx8mp";
+
+	reg_vcc_3v3_audio: 3v3_audio_regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3_AUD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_vcc_1v8_audio: 1v8_audio_regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_1V8_AUD";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	sgtl5000-sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx-sgtl5000";
+		audio-cpu = <&sai2>;
+		audio-codec = <&sgtl5000_codec>;
+	};
+};
+
+&i2c1 {
+	sgtl5000_codec: sgtl5000@a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+
+		assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
+		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+		assigned-clock-rates = <24000000>;
+		clocks = <&clk IMX8MP_CLK_CLKOUT1>;
+		clock-names = "mclk";
+
+		VDDA-supply  = <&reg_vcc_3v3_audio>;
+		VDDD-supply  = <&reg_vcc_1v8_audio>;
+		VDDIO-supply = <&reg_vcc_1v8_audio>;
+	};
+};
+
+/* I2S-0 = sai2 */
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+
+	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <12288000>;
+
+	fsl,sai-mclk-direction-output;
+	status = "okay";
 };
 
 &flexcan1 {
@@ -49,4 +100,13 @@ pinctrl_smarc_gpio: smarcgpiosgrp {
 			<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x19>, /* GPIO12 */
 			<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19>; /* GPIO13 */
 	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC   0xd6
+			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK    0xd6
+			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
+			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+		>;
+	};
 };
-- 
2.34.1


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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Marco Felsch]

Hi Luca,

On 23-02-22, Luca Ceresoli wrote:
> The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
> NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
> 
> This requires to:
> 
>  * add the power supplies (always on)
>  * enable sai2 with pinmuxes
>  * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
>    IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> ---
>  .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> index 470ff8e31e32..894d9809f76d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> @@ -14,6 +14,57 @@ / {
>  	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
>  		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
>  		     "fsl,imx8mp";

...

> +/* I2S-0 = sai2 */
> +&sai2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sai2>;
> +
> +	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
> +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> +	assigned-clock-rates = <12288000>;
> +
> +	fsl,sai-mclk-direction-output;
> +	status = "okay";
>  };

Do you have some downstream patches for the sai interfaces? AFAIR Marek
worked on this but the patches are not mainlien yet.

Regards,
  Marco

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Marek Vasut]

On 2/22/23 18:59, Marco Felsch wrote:
> Hi Luca,
> 
> On 23-02-22, Luca Ceresoli wrote:
>> The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
>> NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
>>
>> This requires to:
>>
>>   * add the power supplies (always on)
>>   * enable sai2 with pinmuxes
>>   * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
>>     IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
>>
>> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
>> ---
>>   .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
>>   1 file changed, 60 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
>> index 470ff8e31e32..894d9809f76d 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
>> @@ -14,6 +14,57 @@ / {
>>   	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
>>   		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
>>   		     "fsl,imx8mp";
> 
> ...
> 
>> +/* I2S-0 = sai2 */
>> +&sai2 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_sai2>;
>> +
>> +	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
>> +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
>> +	assigned-clock-rates = <12288000>;
>> +
>> +	fsl,sai-mclk-direction-output;
>> +	status = "okay";
>>   };
> 
> Do you have some downstream patches for the sai interfaces? AFAIR Marek
> worked on this but the patches are not mainlien yet.

I guess it is time to resubmit these.

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Marco Felsch]

On 23-02-22, Marek Vasut wrote:
> On 2/22/23 18:59, Marco Felsch wrote:
> > Hi Luca,
> > 
> > On 23-02-22, Luca Ceresoli wrote:
> > > The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
> > > NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
> > > 
> > > This requires to:
> > > 
> > >   * add the power supplies (always on)
> > >   * enable sai2 with pinmuxes
> > >   * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
> > >     IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
> > > 
> > > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > > ---
> > >   .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
> > >   1 file changed, 60 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > > index 470ff8e31e32..894d9809f76d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > > @@ -14,6 +14,57 @@ / {
> > >   	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
> > >   		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
> > >   		     "fsl,imx8mp";
> > 
> > ...
> > 
> > > +/* I2S-0 = sai2 */
> > > +&sai2 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_sai2>;
> > > +
> > > +	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
> > > +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> > > +	assigned-clock-rates = <12288000>;
> > > +
> > > +	fsl,sai-mclk-direction-output;
> > > +	status = "okay";
> > >   };
> > 
> > Do you have some downstream patches for the sai interfaces? AFAIR Marek
> > worked on this but the patches are not mainlien yet.
> 
> I guess it is time to resubmit these.

I would have two patches for your series first is necessary the other is
changing the sound-card to make use of the simple-audio-card.

Regards,
  Marco

8<-----------------------------------------------------------------------------------------
[1]

diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
index 2d5d8255c7fa2..32eb29ae8f71f 100644
--- a/drivers/clk/imx/clk-imx8mp-audiomix.c
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -18,7 +18,7 @@
 
 #define CLKEN0                 0x000
 #define CLKEN1                 0x004
-#define SAI_MCLK_SEL(n)                (300 + 4 * (n)) /* n in 0..5 */
+#define SAI_MCLK_SEL(n)                (0x300 + 4 * (n))       /* n in 0..5 */
 #define PDM_SEL                        0x318
 #define SAI_PLL_GNRL_CTL       0x400

8<-----------------------------------------------------------------------------------------
[2]

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 8547391d9cbbf..3b38ec7bb47be 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -47,7 +47,6 @@ reg_audio_pwr: regulator-audio-pwr {
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
-		regulator-always-on;
 	};
 
 	reg_can1_stby: regulator-can1-stby {
@@ -94,21 +93,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 		enable-active-high;
 	};
 
-	sound-wm8960 {
-		compatible = "fsl,imx-audio-wm8960";
-		model = "wm8960-audio";
-		audio-cpu = <&sai3>;
-		audio-codec = <&codec>;
-		audio-routing =
+	sound-wm8524 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "wm8960-audio";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&cpudai>;
+		simple-audio-card,bitclock-master = <&cpudai>;
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Speaker", "External Speaker",
+			"Microphone", "Mic Jack";
+		simple-audio-card,routing =
 			"Headphone Jack", "HP_L",
 			"Headphone Jack", "HP_R",
-			"Ext Spk", "SPK_LP",
-			"Ext Spk", "SPK_LN",
-			"Ext Spk", "SPK_RP",
-			"Ext Spk", "SPK_RN",
+			"External Speaker", "SPK_LP",
+			"External Speaker", "SPK_LN",
+			"External Speaker", "SPK_RP",
+			"External Speaker", "SPK_RN",
 			"LINPUT1", "Mic Jack",
 			"LINPUT3", "Mic Jack",
 			"Mic Jack", "MICB";
+
+		cpudai: simple-audio-card,cpu {
+			sound-dai = <&sai3>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8960>;
+		};
 	};
 };
 
@@ -364,7 +376,7 @@ &i2c3 {
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
 
-	codec: wm8960@1a {
+	wm8960: codec@1a {
 		compatible = "wlf,wm8960";
 		reg = <0x1a>;
 		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
@@ -373,6 +385,7 @@ codec: wm8960@1a {
 		wlf,hp-cfg = <3 2 3>;
 		wlf,gpio-cfg = <1 3>;
 		SPKVDD1-supply = <&reg_audio_pwr>;
+		#sound-dai-cells = <0>;
 	};
 
 	pca6416: gpio@20 {
8<-----------------------------------------------------------------------------------------

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Marek Vasut]

On 2/22/23 20:02, Marco Felsch wrote:

Hi,

[...]

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 8547391d9cbbf..3b38ec7bb47be 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -47,7 +47,6 @@ reg_audio_pwr: regulator-audio-pwr {
>   		regulator-max-microvolt = <3300000>;
>   		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
>   		enable-active-high;
> -		regulator-always-on;
>   	};
>   
>   	reg_can1_stby: regulator-can1-stby {
> @@ -94,21 +93,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>   		enable-active-high;
>   	};
>   
> -	sound-wm8960 {
> -		compatible = "fsl,imx-audio-wm8960";
> -		model = "wm8960-audio";
> -		audio-cpu = <&sai3>;
> -		audio-codec = <&codec>;
> -		audio-routing =
> +	sound-wm8524 {

Why WM8524 ? The MX8MP EVK I have here is populated with WM8960 chip and 
with single headphone jack, are you sure the below is correct ?

[...]

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Marco Felsch]

On 23-02-23, Marek Vasut wrote:
> On 2/22/23 20:02, Marco Felsch wrote:
> 
> Hi,
> 
> [...]
> 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index 8547391d9cbbf..3b38ec7bb47be 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -47,7 +47,6 @@ reg_audio_pwr: regulator-audio-pwr {
> >   		regulator-max-microvolt = <3300000>;
> >   		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> >   		enable-active-high;
> > -		regulator-always-on;
> >   	};
> >   	reg_can1_stby: regulator-can1-stby {
> > @@ -94,21 +93,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> >   		enable-active-high;
> >   	};
> > -	sound-wm8960 {
> > -		compatible = "fsl,imx-audio-wm8960";
> > -		model = "wm8960-audio";
> > -		audio-cpu = <&sai3>;
> > -		audio-codec = <&codec>;
> > -		audio-routing =
> > +	sound-wm8524 {
> 
> Why WM8524 ? The MX8MP EVK I have here is populated with WM8960 chip and
> with single headphone jack, are you sure the below is correct ?

Argh.. the name was copied from 8MM evk dts but the below setup is
working, at least the audio-outpath. Didn't tested the mic path.

Regards,
  Marco

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Luca Ceresoli]

Hi Marco,

On Wed, 22 Feb 2023 18:59:41 +0100
Marco Felsch <m.felsch@pengutronix.de> wrote:

> Hi Luca,
> 
> On 23-02-22, Luca Ceresoli wrote:
> > The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
> > NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
> > 
> > This requires to:
> > 
> >  * add the power supplies (always on)
> >  * enable sai2 with pinmuxes
> >  * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
> >    IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
> > 
> > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > ---
> >  .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
> >  1 file changed, 60 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > index 470ff8e31e32..894d9809f76d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> > @@ -14,6 +14,57 @@ / {
> >  	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
> >  		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
> >  		     "fsl,imx8mp";  
> 
> ...
> 
> > +/* I2S-0 = sai2 */
> > +&sai2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_sai2>;
> > +
> > +	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
> > +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> > +	assigned-clock-rates = <12288000>;
> > +
> > +	fsl,sai-mclk-direction-output;
> > +	status = "okay";
> >  };  
> 
> Do you have some downstream patches for the sai interfaces? AFAIR Marek
> worked on this but the patches are not mainlien yet.

Right, my patch is based on the v3 series by Marek, and it should be
threaded accordingly
(https://lore.kernel.org/linux-arm-kernel/20230222172552.1545519-1-luca.ceresoli@bootlin.com/),
but I realize I haven't made it 100% clear -- sorry about this.

I guess I should just resend separately with a clarifying cover letter
next time.

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[Krzysztof Kozlowski]

On 22/02/2023 18:25, Luca Ceresoli wrote:
> The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
> NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
> 
> This requires to:
> 
>  * add the power supplies (always on)
>  * enable sai2 with pinmuxes
>  * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
>    IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> ---
>  .../dts/freescale/imx8mp-msc-sm2s-ep1.dts     | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> index 470ff8e31e32..894d9809f76d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> @@ -14,6 +14,57 @@ / {
>  	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
>  		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
>  		     "fsl,imx8mp";
> +
> +	reg_vcc_3v3_audio: 3v3_audio_regulator {

No underscores in node names.

> +		compatible = "regulator-fixed";
> +		regulator-name = "VCC_3V3_AUD";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +
> +	reg_vcc_1v8_audio: 1v8_audio_regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "VCC_1V8_AUD";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +	};
> +
> +	sgtl5000-sound {

Just: sound



Best regards,
Krzysztof


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Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card

[kernel test robot]

Hi Luca,

I love your patch! Yet something to improve:

[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on krzk/for-next krzk-dt/for-next linus/master v6.2 next-20230223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Luca-Ceresoli/arm64-dts-imx8mp-msc-sm2s-Add-sound-card/20230223-012837
base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
patch link:    https://lore.kernel.org/r/20230222172552.1545519-1-luca.ceresoli%40bootlin.com
patch subject: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add sound card
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20230223/202302231533.yOY5yoeD-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/a5c4ed6f9f95285c0ec312f5293250a83ccfc5ce
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Luca-Ceresoli/arm64-dts-imx8mp-msc-sm2s-Add-sound-card/20230223-012837
        git checkout a5c4ed6f9f95285c0ec312f5293250a83ccfc5ce
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302231533.yOY5yoeD-lkp@intel.com/

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts:58.1-6 Label or path sai2 not found
>> FATAL ERROR: Syntax error parsing input tree

-- 
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https://github.com/intel/lkp-tests

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Re: [PATCH v3 6/6] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK

[Marek Vasut]

On 2/22/23 18:22, Luca Ceresoli wrote:
> Hello Marek,

Hi,

> On Sat, 25 Jun 2022 03:32:35 +0200
> Marek Vasut <marex@denx.de> wrote:
> 
>> Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
>> This is all that is needed to get analog audio output operational
>> on i.MX8MP EVK.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Abel Vesa <abel.vesa@nxp.com>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Jacky Bai <ping.bai@nxp.com>
>> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>> Cc: Lucas Stach <l.stach@pengutronix.de>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: Stephen Boyd <sboyd@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-clk@vger.kernel.org
>> Cc: linux-imx@nxp.com
> 
> I'm sending in reply to this e-mail the device tree patch I have used
> for my audio testing on the MSC SM2-MB-EP1 board. Feel free to add it to
> your series if you want, it obviously depends on it.

Lemme just mark this email locally and start with the MX8MP EVK . If the 
audio patches ever get upstream, then this one can be easily 
resubmitted. Does that work ?

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Re: [PATCH v3 6/6] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK

[Luca Ceresoli]

Hi Marek,

On Thu, 23 Feb 2023 17:24:32 +0100
Marek Vasut <marex@denx.de> wrote:

> On 2/22/23 18:22, Luca Ceresoli wrote:
> > Hello Marek,  
> 
> Hi,
> 
> > On Sat, 25 Jun 2022 03:32:35 +0200
> > Marek Vasut <marex@denx.de> wrote:
> >   
> >> Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator.
> >> This is all that is needed to get analog audio output operational
> >> on i.MX8MP EVK.
> >>
> >> Signed-off-by: Marek Vasut <marex@denx.de>
> >> Cc: Abel Vesa <abel.vesa@nxp.com>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Jacky Bai <ping.bai@nxp.com>
> >> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> >> Cc: Lucas Stach <l.stach@pengutronix.de>
> >> Cc: Michael Turquette <mturquette@baylibre.com>
> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> Cc: Stephen Boyd <sboyd@kernel.org>
> >> Cc: linux-arm-kernel@lists.infradead.org
> >> Cc: linux-clk@vger.kernel.org
> >> Cc: linux-imx@nxp.com  
> > 
> > I'm sending in reply to this e-mail the device tree patch I have used
> > for my audio testing on the MSC SM2-MB-EP1 board. Feel free to add it to
> > your series if you want, it obviously depends on it.  
> 
> Lemme just mark this email locally and start with the MX8MP EVK . If the 
> audio patches ever get upstream, then this one can be easily 
> resubmitted. Does that work ?

Sure.

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[PATCH v3 3/6] clk: imx: imx8mp: Add audiomix block control

[Shengjiu Wang]

From: Marek Vasut <marex@denx.de>

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Model it as a large static table of
gates and muxes with one exception, which is the PLL14xx . The PLL14xx
SAI PLL has to be registered separately.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
---
V2: No change
V3: - Use devm_platform_ioremap_resource
    - Use clk_hw_onecell_data instead of clk_imx8mp_audiomix_priv
    - Include mod_devicetable.h for of_device_id struct
    - Use struct clk_parent_data instead of string parent_name
---
 drivers/clk/imx/Makefile              |   2 +-
 drivers/clk/imx/clk-imx8mp-audiomix.c | 286 ++++++++++++++++++++++++++
 2 files changed, 287 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/imx/clk-imx8mp-audiomix.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 88b9b9285d22e..c4290937637eb 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
 
 obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
 obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
-obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
+obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
 obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
 
 obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
new file mode 100644
index 0000000000000..2d5d8255c7fa2
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for i.MX8M Plus Audio BLK_CTRL
+ *
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+#include "clk.h"
+
+#define CLKEN0			0x000
+#define CLKEN1			0x004
+#define SAI_MCLK_SEL(n)		(300 + 4 * (n))	/* n in 0..5 */
+#define PDM_SEL			0x318
+#define SAI_PLL_GNRL_CTL	0x400
+
+#define SAIn_MCLK1_PARENT(n)						\
+static const struct clk_parent_data					\
+clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = {			\
+	{								\
+		.fw_name = "sai"__stringify(n),				\
+		.name = "sai"__stringify(n)				\
+	}, {								\
+		.fw_name = "sai"__stringify(n)"_mclk",			\
+		.name = "sai"__stringify(n)"_mclk"			\
+	},								\
+}
+
+SAIn_MCLK1_PARENT(1);
+SAIn_MCLK1_PARENT(2);
+SAIn_MCLK1_PARENT(3);
+SAIn_MCLK1_PARENT(5);
+SAIn_MCLK1_PARENT(6);
+SAIn_MCLK1_PARENT(7);
+
+static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
+	{ .fw_name = "sai1", .name = "sai1" },
+	{ .fw_name = "sai2", .name = "sai2" },
+	{ .fw_name = "sai3", .name = "sai3" },
+	{ .name = "dummy" },
+	{ .fw_name = "sai5", .name = "sai5" },
+	{ .fw_name = "sai6", .name = "sai6" },
+	{ .fw_name = "sai7", .name = "sai7" },
+	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+	{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
+	{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
+	{ .name = "dummy" },
+	{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
+	{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
+	{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
+	{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
+	{ .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
+	{ .fw_name = "pdm", .name = "pdm" },
+	{ .name = "sai_pll_out_div2" },
+	{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
+	{ .name = "dummy" },
+};
+
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
+	{ .fw_name = "osc_24m", .name = "osc_24m" },
+	{ .name = "dummy" },
+	{ .name = "dummy" },
+	{ .name = "dummy" },
+};
+
+static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
+	{ .fw_name = "sai_pll", .name = "sai_pll" },
+	{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
+};
+
+#define CLK_GATE(gname, cname)						\
+	{								\
+		gname"_cg",						\
+		IMX8MP_CLK_AUDIOMIX_##cname,				\
+		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\

{ .fw_name = "audio_root_clk", .name = "audio_root_clk" }, NULL, 1,             \

Should be the 'audio_root_clk' better?

Then the 'clocks' and 'clock-names' can be removed in dts node?

+		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\
+		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\
+	}
+
+#define CLK_SAIn(n)							\
+	{								\
+		"sai"__stringify(n)"_mclk1_sel",			\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {},		\
+		clk_imx8mp_audiomix_sai##n##_mclk1_parents,		\
+		ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
+		SAI_MCLK_SEL(n), 1, 0					\
+	}, {								\
+		"sai"__stringify(n)"_mclk2_sel",			\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {},		\
+		clk_imx8mp_audiomix_sai_mclk2_parents,			\
+		ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents),	\
+		SAI_MCLK_SEL(n), 4, 1					\
+	}, {								\
+		"sai"__stringify(n)"_ipg_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG,			\
+		{ .fw_name = "ahb", .name = "ahb" }, NULL, 1,		\

{ .fw_name = "audio_root_clk", .name = "audio_root_clk" }, NULL, 1,             \

ditto

best regards
Wang shengjiu
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG		\
+	}, {								\
+		"sai"__stringify(n)"_mclk1_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1,			\
+		{							\
+			.fw_name = "sai"__stringify(n)"_mclk1_sel",	\
+			.name = "sai"__stringify(n)"_mclk1_sel"		\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1		\
+	}, {								\
+		"sai"__stringify(n)"_mclk2_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2,			\
+		{							\
+			.fw_name = "sai"__stringify(n)"_mclk2_sel",	\
+			.name = "sai"__stringify(n)"_mclk2_sel"		\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2		\
+	}, {								\
+		"sai"__stringify(n)"_mclk3_cg",				\
+		IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3,			\
+		{							\
+			.fw_name = "sai_pll_out_div2",			\
+			.name = "sai_pll_out_div2"			\
+		}, NULL, 1,						\
+		CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3		\
+	}
+
+#define CLK_PDM								\
+	{								\
+		"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {},		\
+		clk_imx8mp_audiomix_pdm_parents,			\
+		ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents),		\
+		PDM_SEL, 2, 0						\
+	}
+
+struct clk_imx8mp_audiomix_sel {
+	const char			*name;
+	int				clkid;
+	const struct clk_parent_data	parent;		/* For gate */
+	const struct clk_parent_data	*parents;	/* For mux */
+	int				num_parents;
+	u16				reg;
+	u8				width;
+	u8				shift;
+};
+
+static struct clk_imx8mp_audiomix_sel sels[] = {
+	CLK_GATE("asrc", ASRC_IPG),
+	CLK_GATE("pdm", PDM_IPG),
+	CLK_GATE("earc", EARC_IPG),
+	CLK_GATE("ocrama", OCRAMA_IPG),
+	CLK_GATE("aud2htx", AUD2HTX_IPG),
+	CLK_GATE("earc_phy", EARC_PHY),
+	CLK_GATE("sdma2", SDMA2_ROOT),
+	CLK_GATE("sdma3", SDMA3_ROOT),
+	CLK_GATE("spba2", SPBA2_ROOT),
+	CLK_GATE("dsp", DSP_ROOT),
+	CLK_GATE("dspdbg", DSPDBG_ROOT),
+	CLK_GATE("edma", EDMA_ROOT),
+	CLK_GATE("audpll", AUDPLL_ROOT),
+	CLK_GATE("mu2", MU2_ROOT),
+	CLK_GATE("mu3", MU3_ROOT),
+	CLK_PDM,
+	CLK_SAIn(1),
+	CLK_SAIn(2),
+	CLK_SAIn(3),
+	CLK_SAIn(5),
+	CLK_SAIn(6),
+	CLK_SAIn(7)
+};
+
+static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *priv;
+	struct device *dev = &pdev->dev;
+	void __iomem *base;
+	struct clk_hw *hw;
+	int i;
+
+	priv = devm_kzalloc(dev,
+			    struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->num = IMX8MP_CLK_AUDIOMIX_END;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	for (i = 0; i < ARRAY_SIZE(sels); i++) {
+		if (sels[i].num_parents == 1) {
+			hw = devm_clk_hw_register_gate_parent_data(dev,
+								   sels[i].name,
+								   &sels[i].parent,
+								   0,
+								   base + sels[i].reg,
+								   sels[i].shift,
+								   0, NULL);
+		} else {
+			hw = devm_clk_hw_register_mux_parent_data(dev,
+								  sels[i].name,
+								  sels[i].parents,
+								  sels[i].num_parents,
+								  0,
+								  base + sels[i].reg,
+								  sels[i].shift,
+								  sels[i].width,
+								  0, NULL);
+		}
+
+		if (IS_ERR(hw))
+			return PTR_ERR(hw);
+
+		priv->hws[sels[i].clkid] = hw;
+	}
+
+	/* SAI PLL */
+	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_ref_sel",
+						  clk_imx8mp_audiomix_pll_parents,
+						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
+						  CLK_SET_RATE_NO_REPARENT,
+						  base + SAI_PLL_GNRL_CTL,
+						  0, 2, 0, NULL);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
+
+	hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
+				    base + 0x400, &imx_1443x_pll);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
+
+	hw = devm_clk_hw_register_mux_parent_data(dev, "sai_pll_bypass",
+						  clk_imx8mp_audiomix_pll_bypass_sels,
+						  ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
+						  CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+						  base + SAI_PLL_GNRL_CTL,
+						  16, 1, 0, NULL);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
+
+	hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
+				       0, base + SAI_PLL_GNRL_CTL, 13,
+				       0, NULL);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
+
+	hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
+					       "sai_pll_out", 0, 1, 2);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+					   priv);
+}
+
+static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
+	{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
+
+static struct platform_driver clk_imx8mp_audiomix_driver = {
+	.probe	= clk_imx8mp_audiomix_probe,
+	.driver = {
+		.name = "imx8mp-audio-blk-ctrl",
+		.of_match_table = clk_imx8mp_audiomix_of_match,
+	},
+};
+
+module_platform_driver(clk_imx8mp_audiomix_driver);
+
+MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
+MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
+MODULE_LICENSE("GPL");

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Re: [PATCH v3 1/6] clk: Introduce devm_clk_hw_register_mux_parent_data()

[Richard Leitner]

Hi,

On Sat, Jun 25, 2022 at 03:32:30AM +0200, Marek Vasut wrote:
> Add an API for clock mux that uses parent_data for the parent instead of
> a string parent_name.

Just stubled across this thread while trying to bring up audio on a
i.MX8MP. The last reply in this series is from October and patch #1 & #6
doesn't apply on v6.1-rc6...
Therefore I'm curious if there is any newer version of this series I
missed? Or is there something I can help with? Especially testing?

regards;rl

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Re: [PATCH v3 1/6] clk: Introduce devm_clk_hw_register_mux_parent_data()

[Marek Vasut]

On 11/21/22 09:17, Richard Leitner wrote:
> Hi,

Hi,

> On Sat, Jun 25, 2022 at 03:32:30AM +0200, Marek Vasut wrote:
>> Add an API for clock mux that uses parent_data for the parent instead of
>> a string parent_name.
> 
> Just stubled across this thread while trying to bring up audio on a
> i.MX8MP. The last reply in this series is from October and patch #1 & #6
> doesn't apply on v6.1-rc6...
> Therefore I'm curious if there is any newer version of this series I
> missed? Or is there something I can help with? Especially testing?

Currently blocked by race conditions between clock and genpd locking, 
those need to be fixed first. See discussion in:

[PATCH 1/3] [RFC] PM: domains: Introduce .power_pre/post_on/off callbacks

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