* [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs
@ 2022-09-30 14:01 James Morse
2022-09-30 14:01 ` [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
` (37 more replies)
0 siblings, 38 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Hello!
To cleanup an erratum affecting aarch32, I wanted a mask for an id register.
This would have been quick to add, but the right thing to do is to convert
that register to automatic generation. If I was going that far, I may as
well do the lot...
I'll post this again at rc1, I've posted it now so folk can work on cleaning
up the cpufeature macro jungle! (leaving the maintainer off CC was
deliberate)
The patch that changes the size of the fields in the middle of the series
is the most interesting thing. I also discovered that the tools accept
'0b002' as a value.
This series is based on arm64/for-next/core, and can be retrieved from:
https://git.kernel.org/pub/scm/linux/kernel/git/morse/linux.git 'arm64/generated_sysreg/a32/rfc-v1
Thanks,
James Morse (38):
arm64/sysreg: Standardise naming for ID_MMFR0_EL1
arm64/sysreg: Standardise naming for ID_MMFR4_EL1
arm64/sysreg: Standardise naming for ID_MMFR5_EL1
arm64/sysreg: Standardise naming for ID_ISAR0_EL1
arm64/sysreg: Standardise naming for ID_ISAR4_EL1
arm64/sysreg: Standardise naming for ID_ISAR5_EL1
arm64/sysreg: Standardise naming for ID_ISAR6_EL1
arm64/sysreg: Standardise naming for ID_PFR0_EL1
arm64/sysreg: Standardise naming for ID_PFR1_EL1
arm64/sysreg: Standardise naming for ID_PFR2_EL1
arm64/sysreg: Standardise naming for ID_DFR0_EL1
arm64/sysreg: Standardise naming for ID_DFR1_EL1
arm64/sysreg: Standardise naming for MVFR0_EL1
arm64/sysreg: Standardise naming for MVFR1_EL1
arm64/sysreg: Standardise naming for MVFR2_EL1
arm64/sysreg: Extend the maximum width of a register and symbole name
arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
arm64/sysreg: Convert MVFR0_EL1 to automatic generation
arm64/sysreg: Convert MVFR1_EL1 to automatic generation
arm64/sysreg: Convert MVFR2_EL1 to automatic generation
arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
arch/arm64/include/asm/sysreg.h | 134 +-----
arch/arm64/kernel/cpufeature.c | 176 ++++----
arch/arm64/kvm/sys_regs.c | 4 +-
arch/arm64/tools/gen-sysreg.awk | 2 +-
arch/arm64/tools/sysreg | 754 ++++++++++++++++++++++++++++++++
5 files changed, 846 insertions(+), 224 deletions(-)
--
2.30.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1 James Morse
` (36 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates. The scripts would like to follow exactly what is in the
arm-arm, which uses lower case for some of these feature names.
Ensure symbols for the ID_MMFR0_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index debc1c0b2b7f..3e1a4592a50a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -733,14 +733,14 @@
#define ID_ISAR6_DP_SHIFT 4
#define ID_ISAR6_JSCVT_SHIFT 0
-#define ID_MMFR0_INNERSHR_SHIFT 28
-#define ID_MMFR0_FCSE_SHIFT 24
-#define ID_MMFR0_AUXREG_SHIFT 20
-#define ID_MMFR0_TCM_SHIFT 16
-#define ID_MMFR0_SHARELVL_SHIFT 12
-#define ID_MMFR0_OUTERSHR_SHIFT 8
-#define ID_MMFR0_PMSA_SHIFT 4
-#define ID_MMFR0_VMSA_SHIFT 0
+#define ID_MMFR0_EL1_InnerShr_SHIFT 28
+#define ID_MMFR0_EL1_FCSE_SHIFT 24
+#define ID_MMFR0_EL1_AuxReg_SHIFT 20
+#define ID_MMFR0_EL1_TCM_SHIFT 16
+#define ID_MMFR0_EL1_ShareLvl_SHIFT 12
+#define ID_MMFR0_EL1_OuterShr_SHIFT 8
+#define ID_MMFR0_EL1_PMSA_SHIFT 4
+#define ID_MMFR0_EL1_VMSA_SHIFT 0
#define ID_MMFR4_EVT_SHIFT 28
#define ID_MMFR4_CCIDX_SHIFT 24
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a51edf3c0214..da82a19200f2 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -402,14 +402,14 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
};
static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
- S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
- S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
+ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
+ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
2022-09-30 14:01 ` [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1 James Morse
` (35 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_MMFR4_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3e1a4592a50a..214e475f95b0 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -742,14 +742,14 @@
#define ID_MMFR0_EL1_PMSA_SHIFT 4
#define ID_MMFR0_EL1_VMSA_SHIFT 0
-#define ID_MMFR4_EVT_SHIFT 28
-#define ID_MMFR4_CCIDX_SHIFT 24
-#define ID_MMFR4_LSM_SHIFT 20
-#define ID_MMFR4_HPDS_SHIFT 16
-#define ID_MMFR4_CNP_SHIFT 12
-#define ID_MMFR4_XNX_SHIFT 8
-#define ID_MMFR4_AC2_SHIFT 4
-#define ID_MMFR4_SPECSEI_SHIFT 0
+#define ID_MMFR4_EL1_EVT_SHIFT 28
+#define ID_MMFR4_EL1_CCIDX_SHIFT 24
+#define ID_MMFR4_EL1_LSM_SHIFT 20
+#define ID_MMFR4_EL1_HPDS_SHIFT 16
+#define ID_MMFR4_EL1_CnP_SHIFT 12
+#define ID_MMFR4_EL1_XNX_SHIFT 8
+#define ID_MMFR4_EL1_AC2_SHIFT 4
+#define ID_MMFR4_EL1_SpecSEI_SHIFT 0
#define ID_MMFR5_ETS_SHIFT 0
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index da82a19200f2..d89dd8130bba 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -467,13 +467,13 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = {
};
static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
/*
* SpecSEI = 1 indicates that the PE might generate an SError on an
@@ -481,7 +481,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
* SError might be generated than it will not be. Hence it has been
* classified as FTR_HIGHER_SAFE.
*/
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
2022-09-30 14:01 ` [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1 James Morse
` (34 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_MMFR5_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 214e475f95b0..79392df1ce7e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -751,7 +751,7 @@
#define ID_MMFR4_EL1_AC2_SHIFT 4
#define ID_MMFR4_EL1_SpecSEI_SHIFT 0
-#define ID_MMFR5_ETS_SHIFT 0
+#define ID_MMFR5_EL1_ETS_SHIFT 0
#define ID_PFR0_DIT_SHIFT 24
#define ID_PFR0_CSV2_SHIFT 16
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d89dd8130bba..8aa9432e9bf0 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -498,7 +498,7 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = {
};
static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (2 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1 James Morse
` (33 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_ISAR0_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.
To functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 14 +++++++-------
arch/arm64/kernel/cpufeature.c | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 79392df1ce7e..0f3c23510ee4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -710,13 +710,13 @@
#define ID_DFR1_MTPMU_SHIFT 0
-#define ID_ISAR0_DIVIDE_SHIFT 24
-#define ID_ISAR0_DEBUG_SHIFT 20
-#define ID_ISAR0_COPROC_SHIFT 16
-#define ID_ISAR0_CMPBRANCH_SHIFT 12
-#define ID_ISAR0_BITFIELD_SHIFT 8
-#define ID_ISAR0_BITCOUNT_SHIFT 4
-#define ID_ISAR0_SWAP_SHIFT 0
+#define ID_ISAR0_EL1_Divide_SHIFT 24
+#define ID_ISAR0_EL1_Debug_SHIFT 20
+#define ID_ISAR0_EL1_Coproc_SHIFT 16
+#define ID_ISAR0_EL1_CmpBranch_SHIFT 12
+#define ID_ISAR0_EL1_BitField_SHIFT 8
+#define ID_ISAR0_EL1_BitCount_SHIFT 4
+#define ID_ISAR0_EL1_Swap_SHIFT 0
#define ID_ISAR5_RDM_SHIFT 24
#define ID_ISAR5_CRC32_SHIFT 16
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8aa9432e9bf0..4f99aa4e0f5d 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -446,13 +446,13 @@ static const struct arm64_ftr_bits ftr_gmid[] = {
};
static const struct arm64_ftr_bits ftr_id_isar0[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (3 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1 James Morse
` (32 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_ISAR4_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 18 +++++++++---------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0f3c23510ee4..24f91b84a0a9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -699,14 +699,14 @@
#define ID_DFR0_PERFMON_8_4 0x5
#define ID_DFR0_PERFMON_8_5 0x6
-#define ID_ISAR4_SWP_FRAC_SHIFT 28
-#define ID_ISAR4_PSR_M_SHIFT 24
-#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20
-#define ID_ISAR4_BARRIER_SHIFT 16
-#define ID_ISAR4_SMC_SHIFT 12
-#define ID_ISAR4_WRITEBACK_SHIFT 8
-#define ID_ISAR4_WITHSHIFTS_SHIFT 4
-#define ID_ISAR4_UNPRIV_SHIFT 0
+#define ID_ISAR4_EL1_SWP_frac_SHIFT 28
+#define ID_ISAR4_EL1_PSR_M_SHIFT 24
+#define ID_ISAR4_EL1_SynchPrim_frac_SHIFT 20
+#define ID_ISAR4_EL1_Barrier_SHIFT 16
+#define ID_ISAR4_EL1_SMC_SHIFT 12
+#define ID_ISAR4_EL1_Writeback_SHIFT 8
+#define ID_ISAR4_EL1_WithShifts_SHIFT 4
+#define ID_ISAR4_EL1_Unpriv_SHIFT 0
#define ID_DFR1_MTPMU_SHIFT 0
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 4f99aa4e0f5d..e301dffa6810 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -486,14 +486,14 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
};
static const struct arm64_ftr_bits ftr_id_isar4[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -1095,7 +1095,7 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
* EL1-dependent register fields to avoid spurious sanity check fails.
*/
if (!id_aa64pfr0_32bit_el1(pfr0)) {
- relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (4 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1 James Morse
` (31 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_ISAR5_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 12 ++++++------
arch/arm64/kernel/cpufeature.c | 22 +++++++++++-----------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 24f91b84a0a9..66851d109ed8 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -718,12 +718,12 @@
#define ID_ISAR0_EL1_BitCount_SHIFT 4
#define ID_ISAR0_EL1_Swap_SHIFT 0
-#define ID_ISAR5_RDM_SHIFT 24
-#define ID_ISAR5_CRC32_SHIFT 16
-#define ID_ISAR5_SHA2_SHIFT 12
-#define ID_ISAR5_SHA1_SHIFT 8
-#define ID_ISAR5_AES_SHIFT 4
-#define ID_ISAR5_SEVL_SHIFT 0
+#define ID_ISAR5_EL1_RDM_SHIFT 24
+#define ID_ISAR5_EL1_CRC32_SHIFT 16
+#define ID_ISAR5_EL1_SHA2_SHIFT 12
+#define ID_ISAR5_EL1_SHA1_SHIFT 8
+#define ID_ISAR5_EL1_AES_SHIFT 4
+#define ID_ISAR5_EL1_SEVL_SHIFT 0
#define ID_ISAR6_I8MM_SHIFT 24
#define ID_ISAR6_BF16_SHIFT 20
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e301dffa6810..195ea580946d 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -457,12 +457,12 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = {
};
static const struct arm64_ftr_bits ftr_id_isar5[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2818,11 +2818,11 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
- HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
- HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
- HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
- HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
- HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
+ HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
+ HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
+ HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
+ HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
+ HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
#endif
{},
};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (5 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1 James Morse
` (30 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_ISAR6_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 14 +++++++-------
arch/arm64/kernel/cpufeature.c | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 66851d109ed8..edf973413360 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -725,13 +725,13 @@
#define ID_ISAR5_EL1_AES_SHIFT 4
#define ID_ISAR5_EL1_SEVL_SHIFT 0
-#define ID_ISAR6_I8MM_SHIFT 24
-#define ID_ISAR6_BF16_SHIFT 20
-#define ID_ISAR6_SPECRES_SHIFT 16
-#define ID_ISAR6_SB_SHIFT 12
-#define ID_ISAR6_FHM_SHIFT 8
-#define ID_ISAR6_DP_SHIFT 4
-#define ID_ISAR6_JSCVT_SHIFT 0
+#define ID_ISAR6_EL1_I8MM_SHIFT 24
+#define ID_ISAR6_EL1_BF16_SHIFT 20
+#define ID_ISAR6_EL1_SPECRES_SHIFT 16
+#define ID_ISAR6_EL1_SB_SHIFT 12
+#define ID_ISAR6_EL1_FHM_SHIFT 8
+#define ID_ISAR6_EL1_DP_SHIFT 4
+#define ID_ISAR6_EL1_JSCVT_SHIFT 0
#define ID_MMFR0_EL1_InnerShr_SHIFT 28
#define ID_MMFR0_EL1_FCSE_SHIFT 24
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 195ea580946d..cd05689550f6 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -503,13 +503,13 @@ static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
};
static const struct arm64_ftr_bits ftr_id_isar6[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (6 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1 James Morse
` (29 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_PFR0_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 12 ++++++------
arch/arm64/kernel/cpufeature.c | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index edf973413360..8a718e428565 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -753,12 +753,12 @@
#define ID_MMFR5_EL1_ETS_SHIFT 0
-#define ID_PFR0_DIT_SHIFT 24
-#define ID_PFR0_CSV2_SHIFT 16
-#define ID_PFR0_STATE3_SHIFT 12
-#define ID_PFR0_STATE2_SHIFT 8
-#define ID_PFR0_STATE1_SHIFT 4
-#define ID_PFR0_STATE0_SHIFT 0
+#define ID_PFR0_EL1_DIT_SHIFT 24
+#define ID_PFR0_EL1_CSV2_SHIFT 16
+#define ID_PFR0_EL1_State3_SHIFT 12
+#define ID_PFR0_EL1_State2_SHIFT 8
+#define ID_PFR0_EL1_State1_SHIFT 4
+#define ID_PFR0_EL1_State0_SHIFT 0
#define ID_DFR0_PERFMON_SHIFT 24
#define ID_DFR0_MPROFDBG_SHIFT 20
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index cd05689550f6..be5e964cf0a6 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -514,12 +514,12 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
};
static const struct arm64_ftr_bits ftr_id_pfr0[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (7 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 James Morse
` (28 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_PFR1_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8a718e428565..f50b0d24c545 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -789,14 +789,14 @@
#define MVFR1_FPDNAN_SHIFT 4
#define MVFR1_FPFTZ_SHIFT 0
-#define ID_PFR1_GIC_SHIFT 28
-#define ID_PFR1_VIRT_FRAC_SHIFT 24
-#define ID_PFR1_SEC_FRAC_SHIFT 20
-#define ID_PFR1_GENTIMER_SHIFT 16
-#define ID_PFR1_VIRTUALIZATION_SHIFT 12
-#define ID_PFR1_MPROGMOD_SHIFT 8
-#define ID_PFR1_SECURITY_SHIFT 4
-#define ID_PFR1_PROGMOD_SHIFT 0
+#define ID_PFR1_EL1_GIC_SHIFT 28
+#define ID_PFR1_EL1_Virt_frac_SHIFT 24
+#define ID_PFR1_EL1_Sec_frac_SHIFT 20
+#define ID_PFR1_EL1_GenTimer_SHIFT 16
+#define ID_PFR1_EL1_Virtualization_SHIFT 12
+#define ID_PFR1_EL1_MProgMod_SHIFT 8
+#define ID_PFR1_EL1_Security_SHIFT 4
+#define ID_PFR1_EL1_ProgMod_SHIFT 0
#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index be5e964cf0a6..982d670ec566 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -524,14 +524,14 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = {
};
static const struct arm64_ftr_bits ftr_id_pfr1[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -1096,11 +1096,11 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
*/
if (!id_aa64pfr0_32bit_el1(pfr0)) {
relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
- relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
- relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
- relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
- relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
- relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
+ relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
}
taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
--
2.30.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (8 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1 James Morse
` (27 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_PFR2_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f50b0d24c545..ff9814290f43 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -768,8 +768,8 @@
#define ID_DFR0_COPSDBG_SHIFT 4
#define ID_DFR0_COPDBG_SHIFT 0
-#define ID_PFR2_SSBS_SHIFT 4
-#define ID_PFR2_CSV3_SHIFT 0
+#define ID_PFR2_EL1_SSBS_SHIFT 4
+#define ID_PFR2_EL1_CSV3_SHIFT 0
#define MVFR0_FPROUND_SHIFT 28
#define MVFR0_FPSHVEC_SHIFT 24
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 982d670ec566..7e3bbd2e69e3 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -536,8 +536,8 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = {
};
static const struct arm64_ftr_bits ftr_id_pfr2[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (9 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1 James Morse
` (26 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_DFR0_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.
The arm-arm has feature names for some of the ID_DFR0_EL1.PerMon encodings.
Use these feature names in preference to the '8_4' indication of the
architecture version they were introduced in.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 24 +++++++++++-------------
arch/arm64/kernel/cpufeature.c | 14 +++++++-------
arch/arm64/kvm/sys_regs.c | 4 ++--
3 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ff9814290f43..e71402738cae 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -692,12 +692,10 @@
#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
#endif
-#define ID_DFR0_PERFMON_SHIFT 24
-
-#define ID_DFR0_PERFMON_8_0 0x3
-#define ID_DFR0_PERFMON_8_1 0x4
-#define ID_DFR0_PERFMON_8_4 0x5
-#define ID_DFR0_PERFMON_8_5 0x6
+#define ID_DFR0_EL1_PerfMon_PMUv3 0x3
+#define ID_DFR0_EL1_PerfMon_PMUv3p1 0x4
+#define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5
+#define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6
#define ID_ISAR4_EL1_SWP_frac_SHIFT 28
#define ID_ISAR4_EL1_PSR_M_SHIFT 24
@@ -760,13 +758,13 @@
#define ID_PFR0_EL1_State1_SHIFT 4
#define ID_PFR0_EL1_State0_SHIFT 0
-#define ID_DFR0_PERFMON_SHIFT 24
-#define ID_DFR0_MPROFDBG_SHIFT 20
-#define ID_DFR0_MMAPTRC_SHIFT 16
-#define ID_DFR0_COPTRC_SHIFT 12
-#define ID_DFR0_MMAPDBG_SHIFT 8
-#define ID_DFR0_COPSDBG_SHIFT 4
-#define ID_DFR0_COPDBG_SHIFT 0
+#define ID_DFR0_EL1_PerfMon_SHIFT 24
+#define ID_DFR0_EL1_MProfDbg_SHIFT 20
+#define ID_DFR0_EL1_MMapTrc_SHIFT 16
+#define ID_DFR0_EL1_CopTrc_SHIFT 12
+#define ID_DFR0_EL1_MMapDbg_SHIFT 8
+#define ID_DFR0_EL1_CopSDbg_SHIFT 4
+#define ID_DFR0_EL1_CopDbg_SHIFT 0
#define ID_PFR2_EL1_SSBS_SHIFT 4
#define ID_PFR2_EL1_CSV3_SHIFT 0
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7e3bbd2e69e3..21da392a7afe 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -543,13 +543,13 @@ static const struct arm64_ftr_bits ftr_id_pfr2[] = {
static const struct arm64_ftr_bits ftr_id_dfr0[] = {
/* [31:28] TraceFilt */
- S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
+ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
ARM64_FTR_END,
};
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2ef1121ab844..5dc30c02bea6 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1122,8 +1122,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
case SYS_ID_DFR0_EL1:
/* Limit guests to PMUv3 for ARMv8.4 */
val = cpuid_feature_cap_perfmon_field(val,
- ID_DFR0_PERFMON_SHIFT,
- kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
+ ID_DFR0_EL1_PerfMon_SHIFT,
+ kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_EL1_PerfMon_PMUv3p4 : 0);
break;
}
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (10 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1 James Morse
` (25 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_DFR1_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e71402738cae..5f889f3d2c7e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -706,7 +706,7 @@
#define ID_ISAR4_EL1_WithShifts_SHIFT 4
#define ID_ISAR4_EL1_Unpriv_SHIFT 0
-#define ID_DFR1_MTPMU_SHIFT 0
+#define ID_DFR1_EL1_MTPMU_SHIFT 0
#define ID_ISAR0_EL1_Divide_SHIFT 24
#define ID_ISAR0_EL1_Debug_SHIFT 20
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 21da392a7afe..1567b32ae03e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -554,7 +554,7 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
};
static const struct arm64_ftr_bits ftr_id_dfr1[] = {
- S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
+ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (11 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1 James Morse
` (24 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR0_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 5f889f3d2c7e..60642d9bc673 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -769,14 +769,14 @@
#define ID_PFR2_EL1_SSBS_SHIFT 4
#define ID_PFR2_EL1_CSV3_SHIFT 0
-#define MVFR0_FPROUND_SHIFT 28
-#define MVFR0_FPSHVEC_SHIFT 24
-#define MVFR0_FPSQRT_SHIFT 20
-#define MVFR0_FPDIVIDE_SHIFT 16
-#define MVFR0_FPTRAP_SHIFT 12
-#define MVFR0_FPDP_SHIFT 8
-#define MVFR0_FPSP_SHIFT 4
-#define MVFR0_SIMD_SHIFT 0
+#define MVFR0_EL1_FPRound_SHIFT 28
+#define MVFR0_EL1_FPShVec_SHIFT 24
+#define MVFR0_EL1_FPSqrt_SHIFT 20
+#define MVFR0_EL1_FPDivide_SHIFT 16
+#define MVFR0_EL1_FPTrap_SHIFT 12
+#define MVFR0_EL1_FPDP_SHIFT 8
+#define MVFR0_EL1_FPSP_SHIFT 4
+#define MVFR0_EL1_SIMDReg_SHIFT 0
#define MVFR1_SIMDFMAC_SHIFT 28
#define MVFR1_FPHP_SHIFT 24
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 1567b32ae03e..b2fc4a6d738a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2816,8 +2816,8 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
- HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
- HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
+ HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
+ HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (12 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1 James Morse
` (23 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR1_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 16 ++++++++--------
arch/arm64/kernel/cpufeature.c | 8 ++++----
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 60642d9bc673..bfee59f7a3b2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -778,14 +778,14 @@
#define MVFR0_EL1_FPSP_SHIFT 4
#define MVFR0_EL1_SIMDReg_SHIFT 0
-#define MVFR1_SIMDFMAC_SHIFT 28
-#define MVFR1_FPHP_SHIFT 24
-#define MVFR1_SIMDHP_SHIFT 20
-#define MVFR1_SIMDSP_SHIFT 16
-#define MVFR1_SIMDINT_SHIFT 12
-#define MVFR1_SIMDLS_SHIFT 8
-#define MVFR1_FPDNAN_SHIFT 4
-#define MVFR1_FPFTZ_SHIFT 0
+#define MVFR1_EL1_SIMDFMAC_SHIFT 28
+#define MVFR1_EL1_FPHP_SHIFT 24
+#define MVFR1_EL1_SIMDHP_SHIFT 20
+#define MVFR1_EL1_SIMDSP_SHIFT 16
+#define MVFR1_EL1_SIMDInt_SHIFT 12
+#define MVFR1_EL1_SIMDLS_SHIFT 8
+#define MVFR1_EL1_FPDNaN_SHIFT 4
+#define MVFR1_EL1_FPFtZ_SHIFT 0
#define ID_PFR1_EL1_GIC_SHIFT 28
#define ID_PFR1_EL1_Virt_frac_SHIFT 24
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b2fc4a6d738a..5482e25b116a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2805,16 +2805,16 @@ static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
else
mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
- return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
- cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
- cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
+ return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
+ cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
+ cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
}
#endif
static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
#ifdef CONFIG_COMPAT
HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
- HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
+ HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
--
2.30.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (13 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-09-30 14:01 ` [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name James Morse
` (22 subsequent siblings)
37 siblings, 0 replies; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR2_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index bfee59f7a3b2..5c8125fd2a0e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -813,8 +813,8 @@
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
#endif
-#define MVFR2_FPMISC_SHIFT 4
-#define MVFR2_SIMDMISC_SHIFT 0
+#define MVFR2_EL1_FPMisc_SHIFT 4
+#define MVFR2_EL1_SIMDMisc_SHIFT 0
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 5482e25b116a..5a3a151784de 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -429,8 +429,8 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
};
static const struct arm64_ftr_bits ftr_mvfr2[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (14 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1 James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:30 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
` (21 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
32bit has multiple values for its id registers, as extra properties
were added to the CPUs. Some of these end up having long names, which
exceed the fixed 48 character column that the sysreg awk script generates.
For example, the ID_MMFR1_EL1.L1Hvd field has an encoding whose natural
name would be 'invalidate Iside only'. Using this causes compile errors
as the script generates the following:
#define ID_MMFR1_EL1_L1Hvd_INVALIDATE_ISIDE_ONLYUL(0b0001)
Add a few extra characters.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/tools/gen-sysreg.awk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index db461921d256..c350164a3955 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -33,7 +33,7 @@ function expect_fields(nf) {
# Print a CPP macro definition, padded with spaces so that the macro bodies
# line up in a column
function define(name, val) {
- printf "%-48s%s\n", "#define " name, val
+ printf "%-56s%s\n", "#define " name, val
}
# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field
--
2.30.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (15 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:34 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
` (20 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 -------
arch/arm64/tools/sysreg | 47 +++++++++++++++++++++++++++++++++
2 files changed, 47 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 5c8125fd2a0e..6bb53b43bf71 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -171,7 +171,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
@@ -731,15 +730,6 @@
#define ID_ISAR6_EL1_DP_SHIFT 4
#define ID_ISAR6_EL1_JSCVT_SHIFT 0
-#define ID_MMFR0_EL1_InnerShr_SHIFT 28
-#define ID_MMFR0_EL1_FCSE_SHIFT 24
-#define ID_MMFR0_EL1_AuxReg_SHIFT 20
-#define ID_MMFR0_EL1_TCM_SHIFT 16
-#define ID_MMFR0_EL1_ShareLvl_SHIFT 12
-#define ID_MMFR0_EL1_OuterShr_SHIFT 8
-#define ID_MMFR0_EL1_PMSA_SHIFT 4
-#define ID_MMFR0_EL1_VMSA_SHIFT 0
-
#define ID_MMFR4_EL1_EVT_SHIFT 28
#define ID_MMFR4_EL1_CCIDX_SHIFT 24
#define ID_MMFR4_EL1_LSM_SHIFT 20
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7f1fb36f208c..afbf7a1d0d14 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,53 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_MMFR0_EL1 3 0 0 1 4
+Res0 63:32
+Enum 31:28 InnerShr
+ 0b0000 NC
+ 0b0001 HW
+ 0b1111 IGNORED
+EndEnum
+Enum 27:24 FCSE
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 AuxReg
+ 0b0000 NI
+ 0b0001 ACTLR
+ 0b0010 AIFSR
+EndEnum
+Enum 19:16 TCM
+ 0b0000 NI
+ 0b0001 IMPDEF
+ 0b0010 TCM
+ 0b0011 TCM_DMA
+EndEnum
+Enum 15:12 ShareLvl
+ 0b0000 ONE
+ 0b0001 TWO
+EndEnum
+Enum 11:8 OuterShr
+ 0b0000 NC
+ 0b0001 HW
+ 0b1111 IGNORED
+EndEnum
+Enum 7:4 PMSA
+ 0b0000 NI
+ 0b0001 IMPDEF
+ 0b0010 PMSAv6
+ 0b0011 PMSAv7
+EndEnum
+Enum 3:0 VMSA
+ 0b0000 NI
+ 0b0001 IMPDEF
+ 0b0010 VMSAv6
+ 0b0011 VMSAv7
+ 0b0100 VMSAv7_PXN
+ 0b0101 VMSAv7_LONG
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (16 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:37 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
` (19 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 49 +++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6bb53b43bf71..9c97433c1b78 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -171,7 +171,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index afbf7a1d0d14..4aeb4fcc1ee8 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -93,6 +93,55 @@ Enum 3:0 VMSA
EndEnum
EndSysreg
+Sysreg ID_MMFR1_EL1 3 0 0 1 5
+Res0 63:32
+Enum 31:28 BPred
+ 0b0000 NI
+ 0b0001 BP_SW_MANGED
+ 0b0010 BP_ASID_AWARE
+ 0b0011 BP_NOSNOOP
+ 0b0100 BP_INVISIBLE
+EndEnum
+Enum 27:24 L1TstCln
+ 0b0000 NI
+ 0b0001 NOINVALIDATE
+ 0b0010 INVALIDATE
+EndEnum
+Enum 23:20 L1Uni
+ 0b0000 NI
+ 0b0001 INVALIDATE
+ 0b0010 CLEAN_AND_INVALIDATE
+EndEnum
+Enum 19:16 L1Hvd
+ 0b0000 NI
+ 0b0001 INVALIDATE_ISIDE_ONLY
+ 0b0010 INVALIDATE
+ 0b0011 CLEAN_AND_INVALIDATE
+EndEnum
+Enum 15:12 L1UniSW
+ 0b0000 NI
+ 0b0001 CLEAN
+ 0b0010 CLEAN_AND_INVALIDATE
+ 0b0011 INVALIDATE
+EndEnum
+Enum 11:8 L1HvdSW
+ 0b0000 NI
+ 0b0001 CLEAN_AND_INVALIDATE
+ 0b0010 INVALIDATE_DSIDE_ONLY
+ 0b0011 INVALIDATE
+EndEnum
+Enum 7:4 L1UniVA
+ 0b0000 NI
+ 0b0001 CLEAN_AND_INVALIDATE
+ 0b0010 INVALIDATE_BP
+EndEnum
+Enum 3:0 L1HvdVA
+ 0b0000 NI
+ 0b0001 CLEAN_AND_INVALIDATE
+ 0b0010 INVALIDATE_BP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (17 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:43 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
` (18 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR2_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 41 +++++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9c97433c1b78..e517cf0e6e1e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -171,7 +171,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4aeb4fcc1ee8..b4b8073cc05a 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -142,6 +142,47 @@ Enum 3:0 L1HvdVA
EndEnum
EndSysreg
+Sysreg ID_MMFR2_EL1 3 0 0 1 6
+Res0 63:32
+Enum 31:28 HWAccFlg
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 WFIStall
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 MemBarr
+ 0b0000 NI
+ 0b0001 DSB_ONLY
+ 0b0010 IMP
+EndEnum
+Enum 19:16 UniTLB
+ 0b0000 NI
+ 0b0001 BY_VA
+ 0b0010 BY_MATCH_ASID
+ 0b0011 BY_ALL_ASID
+ 0b0100 OTHER_TLBS
+ 0b0101 BROADAST
+ 0b0101 BY_IPA
+EndEnum
+Enum 15:12 HvdTLB
+ 0b0000 NI
+EndEnum
+Enum 11:8 L1HvdRnd
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 L1HvdBG
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 L1HvdFG
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (18 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:46 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
` (17 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR3_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 40 +++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e517cf0e6e1e..b4ea9e00b833 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -171,7 +171,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b4b8073cc05a..1c762ef43568 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -183,6 +183,46 @@ Enum 3:0 L1HvdFG
EndEnum
EndSysreg
+Sysreg ID_MMFR3_EL1 3 0 0 1 7
+Res0 63:32
+Enum 31:28 SuperSec
+ 0b0000 IMP
+ 0b1111 NI
+EndEnum
+Enum 27:24 CMemSz
+ 0b0000 4GB
+ 0b0001 64GB
+ 0b0010 1TB
+EndEnum
+Enum 23:20 CohWalk
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 PAN
+ 0b0000 NI
+ 0b0001 PAN
+ 0b0010 PAN2
+EndEnum
+Enum 15:12 MaintBcst
+ 0b0000 NI
+ 0b0001 NO_TLB
+ 0b0010 ALL
+EndEnum
+Enum 11:8 BPMaint
+ 0b0000 NI
+ 0b0001 ALL
+ 0b0010 BY_VA
+EndEnum
+Enum 7:4 CMaintSW
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 CMaintVA
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (19 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:48 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
` (16 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR4_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ---------
arch/arm64/tools/sysreg | 38 +++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b4ea9e00b833..ad6848f65106 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -171,7 +171,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
@@ -727,15 +726,6 @@
#define ID_ISAR6_EL1_DP_SHIFT 4
#define ID_ISAR6_EL1_JSCVT_SHIFT 0
-#define ID_MMFR4_EL1_EVT_SHIFT 28
-#define ID_MMFR4_EL1_CCIDX_SHIFT 24
-#define ID_MMFR4_EL1_LSM_SHIFT 20
-#define ID_MMFR4_EL1_HPDS_SHIFT 16
-#define ID_MMFR4_EL1_CnP_SHIFT 12
-#define ID_MMFR4_EL1_XNX_SHIFT 8
-#define ID_MMFR4_EL1_AC2_SHIFT 4
-#define ID_MMFR4_EL1_SpecSEI_SHIFT 0
-
#define ID_MMFR5_EL1_ETS_SHIFT 0
#define ID_PFR0_EL1_DIT_SHIFT 24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1c762ef43568..5a311310a6c7 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -223,6 +223,44 @@ Enum 3:0 CMaintVA
EndEnum
EndSysreg
+Sysreg ID_MMFR4_EL1 3 0 0 2 6
+Res0 63:32
+Enum 31:28 EVT
+ 0b0000 NI
+ 0b0001 NO_TLBIS
+ 0b0010 TLBIS
+EndEnum
+Enum 27:24 CCIDX
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 LSM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 HPDS
+ 0b0000 NI
+ 0b0001 AA32HPD
+ 0b0010 HPDS2
+EndEnum
+Enum 15:12 CnP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 XNX
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 AC2
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 SpecSEI
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (20 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:51 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
` (15 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 9 ---------
arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ad6848f65106..77689226b391 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
@@ -703,14 +702,6 @@
#define ID_DFR1_EL1_MTPMU_SHIFT 0
-#define ID_ISAR0_EL1_Divide_SHIFT 24
-#define ID_ISAR0_EL1_Debug_SHIFT 20
-#define ID_ISAR0_EL1_Coproc_SHIFT 16
-#define ID_ISAR0_EL1_CmpBranch_SHIFT 12
-#define ID_ISAR0_EL1_BitField_SHIFT 8
-#define ID_ISAR0_EL1_BitCount_SHIFT 4
-#define ID_ISAR0_EL1_Swap_SHIFT 0
-
#define ID_ISAR5_EL1_RDM_SHIFT 24
#define ID_ISAR5_EL1_CRC32_SHIFT 16
#define ID_ISAR5_EL1_SHA2_SHIFT 12
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 5a311310a6c7..5b51a99b0e90 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -223,6 +223,42 @@ Enum 3:0 CMaintVA
EndEnum
EndSysreg
+Sysreg ID_ISAR0_EL1 3 0 0 2 0
+Res0 63:28
+Enum 27:24 Divide
+ 0b0000 NI
+ 0b0001 xDIV_T32
+ 0b0010 xDIV_A32
+EndEnum
+Enum 23:20 Debug
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 Coproc
+ 0b0000 NI
+ 0b0001 MRC
+ 0b0010 MRC2
+ 0b0011 MRRC
+ 0b0100 MRRC2
+EndEnum
+Enum 15:12 CmpBranch
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 BitField
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 BitCount
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 Swap
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (21 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:53 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
` (14 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 77689226b391..c0702869dba4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 5b51a99b0e90..8173856a8aaf 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -259,6 +259,45 @@ Enum 3:0 Swap
EndEnum
EndSysreg
+Sysreg ID_ISAR1_EL1 3 0 0 2 1
+Res0 63:32
+Enum 31:28 Jazelle
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 Interwork
+ 0b0000 NI
+ 0b0001 BX
+ 0b0010 BLX
+ 0b0011 A32_BX
+EndEnum
+Enum 23:20 Immediate
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 IfThen
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 Extend
+ 0b0000 NI
+ 0b0001 SXTB
+ 0b0010 SXTB16
+EndEnum
+Enum 11:8 Except_AR
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 Except
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 Endian
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (22 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 15:58 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
` (13 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR2_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 46 +++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c0702869dba4..9455122d3018 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8173856a8aaf..c2f2ca63f1ca 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -298,6 +298,52 @@ Enum 3:0 Endian
EndEnum
EndSysreg
+Sysreg ID_ISAR2_EL1 3 0 0 2 2
+Res0 63:32
+Enum 31:28 Reversal
+ 0b0000 NI
+ 0b0001 REV
+ 0b0010 RBIT
+EndEnum
+Enum 27:24 PSR_AR
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 MultU
+ 0b0000 NI
+ 0b0001 UMULL
+ 0b0010 UMAAL
+EndEnum
+Enum 19:16 MultS
+ 0b0000 NI
+ 0b0001 SMULL
+ 0b0010 SMLABB
+ 0b0011 SMLAD
+EndEnum
+Enum 15:12 Mult
+ 0b0000 NI
+ 0b0001 MLA
+ 0b0010 MLS
+EndEnum
+Enum 11:8 MultiAccessInt
+ 0b0000 NI
+ 0b0001 RESTARTABLE
+ 0b0010 CONTINUABLE
+EndEnum
+Enum 7:4 MemHint
+ 0b0000 NI
+ 0b0001 PLD
+ 0b0010 PLD2
+ 0b0011 PLDI
+ 0b0100 PLDW
+EndEnum
+Enum 3:0 LoadStore
+ 0b0000 NI
+ 0b0001 DOUBLE
+ 0b0010 ACQUIRE
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (23 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 16:04 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
` (12 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR3_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 38 +++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9455122d3018..1d60405f0686 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c2f2ca63f1ca..3d9a749af24b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -344,6 +344,44 @@ Enum 3:0 LoadStore
EndEnum
EndSysreg
+Sysreg ID_ISAR3_EL1 3 0 0 2 3
+Res0 63:32
+Enum 31:28 T32EE
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 TrueNOP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 T32Copy
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 TabBranch
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SynchPrim
+ 0b0000 NI
+ 0b0001 EXCLUSIVE
+ 0b0010 DOUBLE
+EndEnum
+Enum 11:8 SVC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 SIMD
+ 0b0000 NI
+ 0b0001 SSAT
+ 0b0011 PKHBT
+EndEnum
+Enum 3:0 Saturate
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (24 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
@ 2022-09-30 14:01 ` James Morse
2022-10-03 16:07 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
` (11 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:01 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR4_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ---------
arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 1d60405f0686..2faa339a8aae 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
@@ -688,15 +687,6 @@
#define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5
#define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6
-#define ID_ISAR4_EL1_SWP_frac_SHIFT 28
-#define ID_ISAR4_EL1_PSR_M_SHIFT 24
-#define ID_ISAR4_EL1_SynchPrim_frac_SHIFT 20
-#define ID_ISAR4_EL1_Barrier_SHIFT 16
-#define ID_ISAR4_EL1_SMC_SHIFT 12
-#define ID_ISAR4_EL1_Writeback_SHIFT 8
-#define ID_ISAR4_EL1_WithShifts_SHIFT 4
-#define ID_ISAR4_EL1_Unpriv_SHIFT 0
-
#define ID_DFR1_EL1_MTPMU_SHIFT 0
#define ID_ISAR5_EL1_RDM_SHIFT 24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 3d9a749af24b..8d85b88c4f6e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -382,6 +382,45 @@ Enum 3:0 Saturate
EndEnum
EndSysreg
+Sysreg ID_ISAR4_EL1 3 0 0 2 4
+Res0 63:32
+Enum 31:28 SWP_frac
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 PSR_M
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 SynchPrim_frac
+ 0b0000 NI
+ 0b0011 IMP
+EndEnum
+Enum 19:16 Barrier
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SMC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 Writeback
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 WithShifts
+ 0b0000 NI
+ 0b0001 LSL3
+ 0b0011 LS
+ 0b0100 REG
+EndEnum
+Enum 3:0 Unpriv
+ 0b0000 NI
+ 0b0001 REG_BYTE
+ 0b0010 SIGNED_HALFWORD
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (25 preceding siblings ...)
2022-09-30 14:01 ` [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:10 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
` (10 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR5_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 8 --------
arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2faa339a8aae..36a01baec0c6 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
@@ -689,13 +688,6 @@
#define ID_DFR1_EL1_MTPMU_SHIFT 0
-#define ID_ISAR5_EL1_RDM_SHIFT 24
-#define ID_ISAR5_EL1_CRC32_SHIFT 16
-#define ID_ISAR5_EL1_SHA2_SHIFT 12
-#define ID_ISAR5_EL1_SHA1_SHIFT 8
-#define ID_ISAR5_EL1_AES_SHIFT 4
-#define ID_ISAR5_EL1_SEVL_SHIFT 0
-
#define ID_ISAR6_EL1_I8MM_SHIFT 24
#define ID_ISAR6_EL1_BF16_SHIFT 20
#define ID_ISAR6_EL1_SPECRES_SHIFT 16
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8d85b88c4f6e..1d7885130514 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -421,6 +421,39 @@ Enum 3:0 Unpriv
EndEnum
EndSysreg
+Sysreg ID_ISAR5_EL1 3 0 0 2 5
+Res0 63:32
+Enum 31:28 VCMA
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 RDM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 23:20
+Enum 19:16 CRC32
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SHA2
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 SHA1
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 AES
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 SEVL
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (26 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:11 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
` (9 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_ISAR6_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ----------
arch/arm64/tools/sysreg | 32 ++++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 36a01baec0c6..4e9cb26bd60a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -173,8 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
-
#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
@@ -688,14 +686,6 @@
#define ID_DFR1_EL1_MTPMU_SHIFT 0
-#define ID_ISAR6_EL1_I8MM_SHIFT 24
-#define ID_ISAR6_EL1_BF16_SHIFT 20
-#define ID_ISAR6_EL1_SPECRES_SHIFT 16
-#define ID_ISAR6_EL1_SB_SHIFT 12
-#define ID_ISAR6_EL1_FHM_SHIFT 8
-#define ID_ISAR6_EL1_DP_SHIFT 4
-#define ID_ISAR6_EL1_JSCVT_SHIFT 0
-
#define ID_MMFR5_EL1_ETS_SHIFT 0
#define ID_PFR0_EL1_DIT_SHIFT 24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1d7885130514..eba4bf0d1479 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -454,6 +454,38 @@ Enum 3:0 SEVL
EndEnum
EndSysreg
+Sysreg ID_ISAR6_EL1 3 0 0 2 7
+Res0 63:28
+Enum 27:24 I8MM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 BF16
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 SPECRES
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SB
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 FHM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 DP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 JSCVT
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (27 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:14 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
` (8 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_PFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 8 -------
arch/arm64/tools/sysreg | 41 +++++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4e9cb26bd60a..83f46c130fb3 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
-#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
@@ -688,13 +687,6 @@
#define ID_MMFR5_EL1_ETS_SHIFT 0
-#define ID_PFR0_EL1_DIT_SHIFT 24
-#define ID_PFR0_EL1_CSV2_SHIFT 16
-#define ID_PFR0_EL1_State3_SHIFT 12
-#define ID_PFR0_EL1_State2_SHIFT 8
-#define ID_PFR0_EL1_State1_SHIFT 4
-#define ID_PFR0_EL1_State0_SHIFT 0
-
#define ID_DFR0_EL1_PerfMon_SHIFT 24
#define ID_DFR0_EL1_MProfDbg_SHIFT 20
#define ID_DFR0_EL1_MMapTrc_SHIFT 16
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index eba4bf0d1479..9403549b1458 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,47 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_PFR0_EL1 3 0 0 1 0
+Res0 63:32
+Enum 31:28 RAS
+ 0b0000 NI
+ 0b0001 RAS
+ 0b0010 RASv1p1
+EndEnum
+Enum 27:24 DIT
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 AMU
+ 0b0000 NI
+ 0b0001 AMUv1
+ 0b0010 AMUv1p1
+EndEnum
+Enum 19:16 CSV2
+ 0b0000 NI
+ 0b0001 CSV2p1
+ 0b0010 CSV2p2
+EndEnum
+Enum 15:12 State3
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 State2
+ 0b0000 NI
+ 0b0001 NO_CV
+ 0b0010 CV
+EndEnum
+Enum 7:4 State1
+ 0b0000 NI
+ 0b0001 THUMB
+ 0b0010 THUMB2
+EndEnum
+Enum 3:0 State0
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR0_EL1 3 0 0 1 4
Res0 63:32
Enum 31:28 InnerShr
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (28 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:16 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
` (7 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_PFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ---------
arch/arm64/tools/sysreg | 40 +++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 83f46c130fb3..94cc887c9e9b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
-#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
@@ -716,15 +715,6 @@
#define MVFR1_EL1_FPDNaN_SHIFT 4
#define MVFR1_EL1_FPFtZ_SHIFT 0
-#define ID_PFR1_EL1_GIC_SHIFT 28
-#define ID_PFR1_EL1_Virt_frac_SHIFT 24
-#define ID_PFR1_EL1_Sec_frac_SHIFT 20
-#define ID_PFR1_EL1_GenTimer_SHIFT 16
-#define ID_PFR1_EL1_Virtualization_SHIFT 12
-#define ID_PFR1_EL1_MProgMod_SHIFT 8
-#define ID_PFR1_EL1_Security_SHIFT 4
-#define ID_PFR1_EL1_ProgMod_SHIFT 0
-
#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 9403549b1458..7aa971ba8aa0 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -87,6 +87,46 @@ Enum 3:0 State0
EndEnum
EndSysreg
+Sysreg ID_PFR1_EL1 3 0 0 1 1
+Res0 63:32
+Enum 31:28 GIC
+ 0b0000 NI
+ 0b0001 GICv3
+ 0b0010 GICv4p1
+EndEnum
+Enum 27:24 Virt_frac
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 Sec_frac
+ 0b0000 NI
+ 0b0001 WALK_DISABLE
+ 0b0010 SECURE_MEMORY
+EndEnum
+Enum 19:16 GenTimer
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 ECV
+EndEnum
+Enum 15:12 Virtualization
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 MProgMod
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 Security
+ 0b0000 NI
+ 0b0001 EL3
+ 0b0001 NSACR_RFR
+EndEnum
+Enum 3:0 ProgMod
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR0_EL1 3 0 0 1 4
Res0 63:32
Enum 31:28 InnerShr
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (29 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:17 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
` (6 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_PFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ----
arch/arm64/tools/sysreg | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 94cc887c9e9b..4fd4dfd0c32b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
-#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
@@ -694,9 +693,6 @@
#define ID_DFR0_EL1_CopSDbg_SHIFT 4
#define ID_DFR0_EL1_CopDbg_SHIFT 0
-#define ID_PFR2_EL1_SSBS_SHIFT 4
-#define ID_PFR2_EL1_CSV3_SHIFT 0
-
#define MVFR0_EL1_FPRound_SHIFT 28
#define MVFR0_EL1_FPShVec_SHIFT 24
#define MVFR0_EL1_FPSqrt_SHIFT 20
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7aa971ba8aa0..7259fdf09e4b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -605,6 +605,22 @@ Enum 3:0 SpecSEI
EndEnum
EndSysreg
+Sysreg ID_PFR2_EL1 3 0 0 3 4
+Res0 63:12
+Enum 11:8 RAS_frac
+ 0b0000 NI
+ 0b0001 RASv1p1
+EndEnum
+Enum 7:4 SSBS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 CSV3
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (30 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:19 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
` (5 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert MVFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ---------
arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4fd4dfd0c32b..d3ff4a1aa805 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,7 +170,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
@@ -693,15 +692,6 @@
#define ID_DFR0_EL1_CopSDbg_SHIFT 4
#define ID_DFR0_EL1_CopDbg_SHIFT 0
-#define MVFR0_EL1_FPRound_SHIFT 28
-#define MVFR0_EL1_FPShVec_SHIFT 24
-#define MVFR0_EL1_FPSqrt_SHIFT 20
-#define MVFR0_EL1_FPDivide_SHIFT 16
-#define MVFR0_EL1_FPTrap_SHIFT 12
-#define MVFR0_EL1_FPDP_SHIFT 8
-#define MVFR0_EL1_FPSP_SHIFT 4
-#define MVFR0_EL1_SIMDReg_SHIFT 0
-
#define MVFR1_EL1_SIMDFMAC_SHIFT 28
#define MVFR1_EL1_FPHP_SHIFT 24
#define MVFR1_EL1_SIMDHP_SHIFT 20
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7259fdf09e4b..f69bdb1d1ee4 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -605,6 +605,45 @@ Enum 3:0 SpecSEI
EndEnum
EndSysreg
+Sysreg MVFR0_EL1 3 0 0 3 0
+Res0 63:32
+Enum 31:28 FPRound
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 FPShVec
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 FPSqrt
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 FPDivide
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 FPTrap
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 FPDP
+ 0b0000 NI
+ 0b0001 VFPv2
+ 0b0001 VFPv3
+EndEnum
+Enum 7:4 FPSP
+ 0b0000 NI
+ 0b0001 VFPv2
+ 0b0001 VFPv3
+EndEnum
+Enum 3:0 SIMDReg
+ 0b0000 NI
+ 0b0001 IMP_16x64
+ 0b0001 IMP_32x64
+EndEnum
+EndSysreg
+
Sysreg ID_PFR2_EL1 3 0 0 3 4
Res0 63:12
Enum 11:8 RAS_frac
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (31 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:21 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
` (4 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert MVFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 10 ---------
arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d3ff4a1aa805..055beb7b1bcc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,7 +170,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
@@ -692,15 +691,6 @@
#define ID_DFR0_EL1_CopSDbg_SHIFT 4
#define ID_DFR0_EL1_CopDbg_SHIFT 0
-#define MVFR1_EL1_SIMDFMAC_SHIFT 28
-#define MVFR1_EL1_FPHP_SHIFT 24
-#define MVFR1_EL1_SIMDHP_SHIFT 20
-#define MVFR1_EL1_SIMDSP_SHIFT 16
-#define MVFR1_EL1_SIMDInt_SHIFT 12
-#define MVFR1_EL1_SIMDLS_SHIFT 8
-#define MVFR1_EL1_FPDNaN_SHIFT 4
-#define MVFR1_EL1_FPFtZ_SHIFT 0
-
#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index f69bdb1d1ee4..c4d20f12c277 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -644,6 +644,45 @@ Enum 3:0 SIMDReg
EndEnum
EndSysreg
+Sysreg MVFR1_EL1 3 0 0 3 1
+Res0 63:32
+Enum 31:28 SIMDFMAC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 FPHP
+ 0b0000 NI
+ 0b0001 FPHP
+ 0b0010 FPHP_CONV
+ 0b0011 FP16
+EndEnum
+Enum 23:20 SIMDHP
+ 0b0000 NI
+ 0b0001 SIMDHP
+ 0b0001 SIMDHP_FLOAT
+EndEnum
+Enum 19:16 SIMDSP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SIMDInt
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 SIMDLS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 FPDNaN
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 FPFtZ
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_PFR2_EL1 3 0 0 3 4
Res0 63:12
Enum 11:8 RAS_frac
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (32 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:25 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
` (3 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert MVFR2_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 5 -----
arch/arm64/tools/sysreg | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 055beb7b1bcc..7a849cfe201f 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,8 +170,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
-
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
@@ -708,9 +706,6 @@
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
#endif
-#define MVFR2_EL1_FPMisc_SHIFT 4
-#define MVFR2_EL1_SIMDMisc_SHIFT 0
-
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c4d20f12c277..fdace903b94e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -683,6 +683,24 @@ Enum 3:0 FPFtZ
EndEnum
EndSysreg
+Sysreg MVFR2_EL1 3 0 0 3 2
+Res0 63:8
+Enum 7:4 FPMisc
+ 0b0000 NI
+ 0b0001 FP
+ 0b0010 FP_DIRECTED_ROUNDING
+ 0b0011 FP_ROUNDING
+ 0b0100 FP_MAX_MIN
+EndEnum
+Enum 3:0 SIMDMisc
+ 0b0000 NI
+ 0b0001 SIMD
+ 0b0010 SIMD_DIRECTED_ROUNDING
+ 0b0011 SIMD_ROUNDING
+ 0b0100 SIMD_MAX_MIN
+EndEnum
+EndSysreg
+
Sysreg ID_PFR2_EL1 3 0 0 3 4
Res0 63:12
Enum 11:8 RAS_frac
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (33 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:27 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
` (2 subsequent siblings)
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_MMFR5_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 3 ---
arch/arm64/tools/sysreg | 12 ++++++++++++
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7a849cfe201f..7dbf86a07735 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -168,7 +168,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
@@ -679,8 +678,6 @@
#define ID_DFR1_EL1_MTPMU_SHIFT 0
-#define ID_MMFR5_EL1_ETS_SHIFT 0
-
#define ID_DFR0_EL1_PerfMon_SHIFT 24
#define ID_DFR0_EL1_MProfDbg_SHIFT 20
#define ID_DFR0_EL1_MMapTrc_SHIFT 16
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index fdace903b94e..a0263a22fc07 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -717,6 +717,18 @@ Enum 3:0 CSV3
EndEnum
EndSysreg
+Sysreg ID_MMFR5_EL1 3 0 0 3 6
+Res0 63:8
+Enum 7:4 nTLBPA
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 ETS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
--
2.30.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (34 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:28 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
2022-09-30 14:02 ` [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_AFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 8 ++++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7dbf86a07735..4b531890e149 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -167,7 +167,6 @@
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
-#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a0263a22fc07..0225efb91cf5 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -127,6 +127,14 @@ Enum 3:0 ProgMod
EndEnum
EndSysreg
+Sysreg ID_AFR0_EL1 3 0 0 1 3
+Res0 63:16
+Field 15:12 IMPDEF3
+Field 11:8 IMPDEF2
+Field 7:4 IMPDEF1
+Field 3:0 IMPDEF0
+EndSysreg
+
Sysreg ID_MMFR0_EL1 3 0 0 1 4
Res0 63:32
Enum 31:28 InnerShr
--
2.30.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (35 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:30 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_DFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 14 ---------
arch/arm64/tools/sysreg | 50 +++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4b531890e149..2c37c861c371 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
-#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
@@ -670,21 +669,8 @@
#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
#endif
-#define ID_DFR0_EL1_PerfMon_PMUv3 0x3
-#define ID_DFR0_EL1_PerfMon_PMUv3p1 0x4
-#define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5
-#define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6
-
#define ID_DFR1_EL1_MTPMU_SHIFT 0
-#define ID_DFR0_EL1_PerfMon_SHIFT 24
-#define ID_DFR0_EL1_MProfDbg_SHIFT 20
-#define ID_DFR0_EL1_MMapTrc_SHIFT 16
-#define ID_DFR0_EL1_CopTrc_SHIFT 12
-#define ID_DFR0_EL1_MMapDbg_SHIFT 8
-#define ID_DFR0_EL1_CopSDbg_SHIFT 4
-#define ID_DFR0_EL1_CopDbg_SHIFT 0
-
#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 0225efb91cf5..785c012fa154 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -127,6 +127,56 @@ Enum 3:0 ProgMod
EndEnum
EndSysreg
+Sysreg ID_DFR0_EL1 3 0 0 1 2
+Res0 63:32
+Enum 31:28 TraceFilt
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 PerfMon
+ 0b0000 NI
+ 0b0001 PMUv1
+ 0b0010 PMUv2
+ 0b0011 PMUv3
+ 0b0100 PMUv3p1
+ 0b0101 PMUv3p4
+ 0b0110 PMUv3p5
+ 0b0111 PMUv3p7
+ 0b1000 PMUv3p8
+ 0b1111 IMPDEF
+EndEnum
+Enum 23:20 MProfDbg
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 MMapTrc
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 CopTrc
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 MMapDbg
+ 0b0000 NI
+ 0b0100 Armv7
+ 0b0101 Arm7p1
+EndEnum
+Field 7:4 CopSDbg
+Enum 3:0 CopDbg
+ 0b0000 NI
+ 0b0010 Armv6
+ 0b0011 Armv6p1
+ 0b0100 Armv7
+ 0b0101 Arm7p1
+ 0b0110 Arm8
+ 0b0111 VHE
+ 0b1000 Debug8p2
+ 0b1001 Debug8p4
+ 0b1010 Debug8p8
+EndEnum
+EndSysreg
+
Sysreg ID_AFR0_EL1 3 0 0 1 3
Res0 63:16
Field 15:12 IMPDEF3
--
2.30.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
` (36 preceding siblings ...)
2022-09-30 14:02 ` [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
@ 2022-09-30 14:02 ` James Morse
2022-10-03 16:32 ` Mark Brown
37 siblings, 1 reply; 62+ messages in thread
From: James Morse @ 2022-09-30 14:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Brown, james.morse
Convert ID_AFR0_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 13 +++++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2c37c861c371..37062a878394 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,8 +165,6 @@
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
-#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
-
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 785c012fa154..7c926fa1a33b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -775,6 +775,19 @@ Enum 3:0 CSV3
EndEnum
EndSysreg
+Sysreg ID_DFR1_EL1 3 0 0 3 5
+Res0 63:8
+Enum 7:4 HPMN0
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 MTPMU
+ 0b0000 IMPDEF
+ 0b0001 IMP
+ 0b1111 NI
+EndEnum
+EndSysreg
+
Sysreg ID_MMFR5_EL1 3 0 0 3 6
Res0 63:8
Enum 7:4 nTLBPA
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name
2022-09-30 14:01 ` [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name James Morse
@ 2022-10-03 15:30 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:30 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 326 bytes --]
On Fri, Sep 30, 2022 at 03:01:49PM +0100, James Morse wrote:
> 32bit has multiple values for its id registers, as extra properties
> were added to the CPUs. Some of these end up having long names, which
> exceed the fixed 48 character column that the sysreg awk script generates.
Reviewed-by: Mark Brown <broonie@kernel.org>
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
@ 2022-10-03 15:34 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:34 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 379 bytes --]
On Fri, Sep 30, 2022 at 03:01:50PM +0100, James Morse wrote:
> Convert ID_MMFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
We now have DDI0487I.a (I assume the 1 is a typo) - I'll review these
against that rather than H.a, hopefully the 32 bit ID registers are not
evolving particularly quickly.
Reviewed-by: Mark Brown <broonie@kernel.org>
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
@ 2022-10-03 15:37 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:37 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 205 bytes --]
On Fri, Sep 30, 2022 at 03:01:51PM +0100, James Morse wrote:
> Convert ID_MMFR1_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
@ 2022-10-03 15:43 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:43 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 523 bytes --]
On Fri, Sep 30, 2022 at 03:01:52PM +0100, James Morse wrote:
> Convert ID_MMFR2_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
> +Enum 19:16 UniTLB
> + 0b0000 NI
> + 0b0001 BY_VA
> + 0b0010 BY_MATCH_ASID
> + 0b0011 BY_ALL_ASID
> + 0b0100 OTHER_TLBS
> + 0b0101 BROADAST
BROADCAST?
> + 0b0101 BY_IPA
> +EndEnum
DDI0487I.a adds a value 0b0110 which I didn't spend enough time to
figure out a sensible name for.
> +Enum 15:12 HvdTLB
> + 0b0000 NI
> +EndEnum
> +Enum 11:8 L1HvdRnd
L1HdvRng
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
@ 2022-10-03 15:46 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:46 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:01:53PM +0100, James Morse wrote:
> Convert ID_MMFR3_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
> +Res0 63:32
> +Enum 31:28 SuperSec
> + 0b0000 IMP
> + 0b1111 NI
> +EndEnum
DDI0487I.a has this as just plain Supersec. I don't know that it makes
a difference.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
@ 2022-10-03 15:48 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:48 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 206 bytes --]
On Fri, Sep 30, 2022 at 03:01:54PM +0100, James Morse wrote:
> Convert ID_MMFR4_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
@ 2022-10-03 15:51 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:51 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:01:55PM +0100, James Morse wrote:
> Convert ID_ISAR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
@ 2022-10-03 15:53 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:53 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:01:56PM +0100, James Morse wrote:
> Convert ID_ISAR1_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
@ 2022-10-03 15:58 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 15:58 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:01:57PM +0100, James Morse wrote:
> Convert ID_ISAR2_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
> +Enum 7:4 MemHint
> + 0b0000 NI
> + 0b0001 PLD
> + 0b0010 PLD2
Yay!
> + 0b0011 PLDI
Should that be PLI? Could be either.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
@ 2022-10-03 16:04 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:04 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 206 bytes --]
On Fri, Sep 30, 2022 at 03:01:58PM +0100, James Morse wrote:
> Convert ID_ISAR3_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
2022-09-30 14:01 ` [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
@ 2022-10-03 16:07 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:07 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:01:59PM +0100, James Morse wrote:
> Convert ID_ISAR4_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
@ 2022-10-03 16:10 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:10 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:00PM +0100, James Morse wrote:
> Convert ID_ISAR5_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
> +Enum 7:4 AES
> + 0b0000 NI
> + 0b0001 IMP
> +EndEnum
DDI0487I.a has
0b0010 VMULL
as well.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
@ 2022-10-03 16:11 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:11 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:01PM +0100, James Morse wrote:
> Convert ID_ISAR6_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
@ 2022-10-03 16:14 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:14 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:02PM +0100, James Morse wrote:
> Convert ID_PFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
> +Enum 19:16 CSV2
> + 0b0000 NI
> + 0b0001 CSV2p1
> + 0b0010 CSV2p2
> +EndEnum
DDI0487I.a says that 0b0001 implies that FEAT_CSV2 is implemented but
not FEAT_CS2p1 and I can't see a reference to a p2 so the last two
should be
0b0001 IMP
0b0010 CSV2p1
AFAICT.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
@ 2022-10-03 16:16 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:16 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:03PM +0100, James Morse wrote:
> Convert ID_PFR1_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
@ 2022-10-03 16:17 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:17 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:04PM +0100, James Morse wrote:
> Convert ID_PFR1_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
This actually converts ID_PFR2_EL1 as per DDI0487I.a but otherwise
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
@ 2022-10-03 16:19 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:19 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:05PM +0100, James Morse wrote:
> Convert MVFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
@ 2022-10-03 16:21 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:21 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:06PM +0100, James Morse wrote:
> Convert MVFR1_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
@ 2022-10-03 16:25 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:25 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:07PM +0100, James Morse wrote:
> Convert MVFR2_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
> +Enum 3:0 SIMDMisc
> + 0b0000 NI
> + 0b0001 SIMD
This should be SIMD_DIRECTED_ROUNDING.
> + 0b0010 SIMD_DIRECTED_ROUNDING
This should *probably* be SIMD_ROUNDING.
> + 0b0011 SIMD_ROUNDING
This should be SIMD_MIN_MAX.
> + 0b0100 SIMD_MAX_MIN
> +EndEnum
DDI0487I.a does not appear to have 0b0100.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
@ 2022-10-03 16:27 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:27 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 206 bytes --]
On Fri, Sep 30, 2022 at 03:02:08PM +0100, James Morse wrote:
> Convert ID_MMFR5_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
@ 2022-10-03 16:28 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:28 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 205 bytes --]
On Fri, Sep 30, 2022 at 03:02:09PM +0100, James Morse wrote:
> Convert ID_AFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
@ 2022-10-03 16:30 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:30 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
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On Fri, Sep 30, 2022 at 03:02:10PM +0100, James Morse wrote:
> Convert ID_DFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
> +Field 7:4 CopSDbg
> +Enum 3:0 CopDbg
> + 0b0000 NI
> + 0b0010 Armv6
> + 0b0011 Armv6p1
> + 0b0100 Armv7
> + 0b0101 Arm7p1
Armv7p1?
> + 0b0110 Arm8
Armv8?
> + 0b1000 Debug8p2
> + 0b1001 Debug8p4
> + 0b1010 Debug8p8
Similarly a missing v for these?
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
2022-09-30 14:02 ` [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
@ 2022-10-03 16:32 ` Mark Brown
0 siblings, 0 replies; 62+ messages in thread
From: Mark Brown @ 2022-10-03 16:32 UTC (permalink / raw)
To: James Morse; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 244 bytes --]
On Fri, Sep 30, 2022 at 03:02:11PM +0100, James Morse wrote:
> Convert ID_AFR0_EL1 to be automatically generated as per DDI04187H.a,
> no functional changes.
ID_DFR1_EL1 and DDI0487I.a. Otherwise
Reviewed-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 62+ messages in thread
end of thread, other threads:[~2022-10-03 16:33 UTC | newest]
Thread overview: 62+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
2022-09-30 14:01 ` [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name James Morse
2022-10-03 15:30 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
2022-10-03 15:34 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
2022-10-03 15:37 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
2022-10-03 15:43 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
2022-10-03 15:46 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
2022-10-03 15:48 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
2022-10-03 15:51 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
2022-10-03 15:53 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
2022-10-03 15:58 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
2022-10-03 16:04 ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
2022-10-03 16:07 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
2022-10-03 16:10 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
2022-10-03 16:11 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
2022-10-03 16:14 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
2022-10-03 16:16 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
2022-10-03 16:17 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
2022-10-03 16:19 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
2022-10-03 16:21 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
2022-10-03 16:25 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
2022-10-03 16:27 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
2022-10-03 16:28 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
2022-10-03 16:30 ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
2022-10-03 16:32 ` Mark Brown
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