[PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Sherry Sun]

The two patches fix some issues for V3.X Synopsys EDAC DDR in synopsys_edac.c.
For the details, please check the patch commit log. This has been verified on
i.MX8MP platform.

Sherry Sun (2):
  EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
  EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X
    Synopsys EDAC DDR

 drivers/edac/synopsys_edac.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

-- 
2.17.1


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[PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

[Sherry Sun]

V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
to change to use the ECC Clear Register to disable the interrupts.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 drivers/edac/synopsys_edac.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index f05ff02c0656..1b630f0be119 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
 static void disable_intr(struct synps_edac_priv *priv)
 {
 	/* Disable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 }
 
 static int setup_irq(struct mem_ctl_info *mci,
-- 
2.17.1


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Re: [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

[Michal Simek]

On 3/18/22 12:17, Sherry Sun wrote:
> V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
> to change to use the ECC Clear Register to disable the interrupts.
> 
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>   drivers/edac/synopsys_edac.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index f05ff02c0656..1b630f0be119 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
>   static void disable_intr(struct synps_edac_priv *priv)
>   {
>   	/* Disable UE/CE Interrupts */
> -	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> -			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> +	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
> +		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
> +	else
> +		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> +		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
>   }
>   
>   static int setup_irq(struct mem_ctl_info *mci,

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

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[PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR

[Sherry Sun]

Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
interrupt handler will be called only once, so need to re-enable the
interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 drivers/edac/synopsys_edac.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 1b630f0be119..3a1db34a8546 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
 	memset(p, 0, sizeof(*p));
 }
 
+static void enable_intr(struct synps_edac_priv *priv);
+
 /**
  * intr_handler - Interrupt Handler for ECC interrupts.
  * @irq:        IRQ number.
@@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
 	/* v3.0 of the controller does not have this register */
 	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
 		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+	else
+		enable_intr(priv);
 	return IRQ_HANDLED;
 }
 
-- 
2.17.1


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Re: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR

[Michal Simek]

On 3/18/22 12:17, Sherry Sun wrote:
> Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
> end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
> the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
> interrupt handler will be called only once, so need to re-enable the
> interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
> 
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>   drivers/edac/synopsys_edac.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index 1b630f0be119..3a1db34a8546 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
>   	memset(p, 0, sizeof(*p));
>   }
>   
> +static void enable_intr(struct synps_edac_priv *priv);
> +
>   /**
>    * intr_handler - Interrupt Handler for ECC interrupts.
>    * @irq:        IRQ number.
> @@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
>   	/* v3.0 of the controller does not have this register */
>   	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
>   		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
> +	else
> +		enable_intr(priv);

nit: newline here would be good.

>   	return IRQ_HANDLED;
>   }
>   

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

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RE: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR

[Sherry Sun]

> > Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
> > end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
> > the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
> > interrupt handler will be called only once, so need to re-enable the
> > interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> >   drivers/edac/synopsys_edac.c | 4 ++++
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> > index 1b630f0be119..3a1db34a8546 100644
> > --- a/drivers/edac/synopsys_edac.c
> > +++ b/drivers/edac/synopsys_edac.c
> > @@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci,
> struct synps_ecc_status *p)
> >   	memset(p, 0, sizeof(*p));
> >   }
> >
> > +static void enable_intr(struct synps_edac_priv *priv);
> > +
> >   /**
> >    * intr_handler - Interrupt Handler for ECC interrupts.
> >    * @irq:        IRQ number.
> > @@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
> >   	/* v3.0 of the controller does not have this register */
> >   	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
> >   		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
> > +	else
> > +		enable_intr(priv);
> 
> nit: newline here would be good.

Hi Michal, thanks for your comments, I will add the newline here in V2.

Best regards
Sherry
> 
> >   	return IRQ_HANDLED;
> >   }
> >
> 
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> Thanks,
> Michal
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Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Michal Simek]

+Shubhrajyoti.

On 3/18/22 12:17, Sherry Sun wrote:
> The two patches fix some issues for V3.X Synopsys EDAC DDR in synopsys_edac.c.
> For the details, please check the patch commit log. This has been verified on
> i.MX8MP platform.
> 
> Sherry Sun (2):
>    EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
>    EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X
>      Synopsys EDAC DDR
> 
>   drivers/edac/synopsys_edac.c | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
> 

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RE: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Shubhrajyoti Datta]

> -----Original Message-----
> From: Michal Simek <michal.simek@xilinx.com>
> Sent: Friday, March 18, 2022 5:00 PM
> To: Sherry Sun <sherry.sun@nxp.com>; bp@alien8.de;
> mchehab@kernel.org; Michal Simek <michals@xilinx.com>;
> tony.luck@intel.com; james.morse@arm.com; rric@kernel.org;
> Shubhrajyoti Datta <shubhraj@xilinx.com>
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-imx@nxp.com
> Subject: Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver
> 
> +Shubhrajyoti.
> 
> On 3/18/22 12:17, Sherry Sun wrote:
> > The two patches fix some issues for V3.X Synopsys EDAC DDR in
> synopsys_edac.c.
> > For the details, please check the patch commit log. This has been
> > verified on i.MX8MP platform.
> >
The changes look good to me .

Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>

> > Sherry Sun (2):
> >    EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
> >    EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X
> >      Synopsys EDAC DDR
> >
> >   drivers/edac/synopsys_edac.c | 11 +++++++++--
> >   1 file changed, 9 insertions(+), 2 deletions(-)
> >
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RE: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Sherry Sun]

Gentle ping...

> -----Original Message-----
> From: Sherry Sun
> Sent: 2022年3月18日 19:20
> To: bp@alien8.de; mchehab@kernel.org; michal.simek@xilinx.com;
> tony.luck@intel.com; james.morse@arm.com; rric@kernel.org
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver
> 
> The two patches fix some issues for V3.X Synopsys EDAC DDR in
> synopsys_edac.c.
> For the details, please check the patch commit log. This has been verified on
> i.MX8MP platform.
> 
> Sherry Sun (2):
>   EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
>   EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X
>     Synopsys EDAC DDR
> 
>  drivers/edac/synopsys_edac.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> --
> 2.17.1

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RE: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Sherry Sun]

Hi Borislav, do you have any comments regarding this patch set?

Best regards
Sherry
> -----Original Message-----
> From: Sherry Sun
> Sent: 2022年3月18日 19:20
> To: bp@alien8.de; mchehab@kernel.org; michal.simek@xilinx.com;
> tony.luck@intel.com; james.morse@arm.com; rric@kernel.org
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver
> 
> The two patches fix some issues for V3.X Synopsys EDAC DDR in
> synopsys_edac.c.
> For the details, please check the patch commit log. This has been verified on
> i.MX8MP platform.
> 
> Sherry Sun (2):
>   EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
>   EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X
>     Synopsys EDAC DDR
> 
>  drivers/edac/synopsys_edac.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> --
> 2.17.1

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Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Borislav Petkov]

On Mon, Apr 18, 2022 at 02:27:21AM +0000, Sherry Sun wrote:
> Hi Borislav, do you have any comments regarding this patch set?

Yes, for EDAC drivers which have designated maintainers, I usually wait
first for them to have a look. In this case, Michal.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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RE: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Sherry Sun]

Hi Borislav, thanks for the info. Hi Michal, would you please help review the patch set? Thanks a lot!

Best regards
Sherry

> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: 2022年4月18日 16:35
> To: Sherry Sun <sherry.sun@nxp.com>; michal.simek@xilinx.com
> Cc: mchehab@kernel.org; tony.luck@intel.com; james.morse@arm.com;
> rric@kernel.org; linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver
> 
> On Mon, Apr 18, 2022 at 02:27:21AM +0000, Sherry Sun wrote:
> > Hi Borislav, do you have any comments regarding this patch set?
> 
> Yes, for EDAC drivers which have designated maintainers, I usually wait first
> for them to have a look. In this case, Michal.
> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeopl
> e.kernel.org%2Ftglx%2Fnotes-about-
> netiquette&amp;data=04%7C01%7Csherry.sun%40nxp.com%7Ccea2785e929
> f44e59a4b08da211652b6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
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Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Borislav Petkov]

On Mon, Apr 18, 2022 at 10:12:14AM +0000, Sherry Sun wrote:
> Hi Borislav, thanks for the info.

You're welcome.

I'd appreciate it, though, if you do not top-post on public mailing
lists but reply underneath the text you're quoting, just like I did.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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RE: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver

[Sherry Sun]

> Subject: Re: [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver
> 
> On Mon, Apr 18, 2022 at 10:12:14AM +0000, Sherry Sun wrote:
> > Hi Borislav, thanks for the info.
> 
> You're welcome.
> 
> I'd appreciate it, though, if you do not top-post on public mailing lists but
> reply underneath the text you're quoting, just like I did.

Hi Borislav, sorry for the inconvenience, got it now. ^_^ 

Best regards
Sherry

> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeopl
> e.kernel.org%2Ftglx%2Fnotes-about-
> netiquette&data=04%7C01%7Csherry.sun%40nxp.com%7Cf6fc1ba92cd
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> jAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp
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