From: "Leizhen (ThunderTown)" <thunder.leizhen@huawei.com>
To: Russell King - ARM Linux admin <linux@armlinux.org.uk>,
Arnd Bergmann <arnd@kernel.org>
Cc: devicetree <devicetree@vger.kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
Date: Sat, 30 Jan 2021 10:51:12 +0800 [thread overview]
Message-ID: <b236bcbc-8610-dfc4-50f2-a4b71162735d@huawei.com> (raw)
In-Reply-To: <20210129103340.GW1551@shell.armlinux.org.uk>
On 2021/1/29 18:33, Russell King - ARM Linux admin wrote:
> On Fri, Jan 29, 2021 at 11:26:38AM +0100, Arnd Bergmann wrote:
>> Another clarification, as there are actually two independent
>> points here:
>>
>> * if you can completely remove the readl() above and just write a
>> hardcoded value into the register, or perhaps read the original
>> value once at boot time, that is probably a win because it
>> avoids one of the barriers in the beginning. The datasheet should
>> tell you if there are any bits in the register that have to be
>> preserved
>>
>> * Regarding the _relaxed() accessors, it's a lot harder to know
>> whether that is safe, as you first have to show, in particular in case
>> any of the accesses stop being guarded by the spinlock in that
>> case, and whether there may be a case where you have to
>> serialize the memory access against accesses that are still in the
>> store queue or prefetched.
>>
>> Whether this matters at all depends mostly on the type of devices
>> you are driving on your SoC. If you have any high-speed network
>> interfaces that are unable to do cache coherent DMA, any extra
>> instruction here may impact the number of packets you can transfer,
>> but if all your high-speed devices are connected to a coherent
>> interconnect, I would just go with the obvious approach and use
>> the safe MMIO accessors everywhere.
>
> For L2 cache code, I would say the opposite, actually, because it is
> all too easy to get into a deadlock otherwise.
>
> If you implement the sync callback, that will be called from every
> non-relaxed accessor, which means if you need to take some kind of
> lock in the sync callback and elsewhere in the L2 cache code, you will
> definitely deadlock.
>
> It is safer to put explicit barriers where it is necessary.
>
> Also remember that the barrier in readl() etc is _after_ the read, not
> before, and the barrier in writel() is _before_ the write, not after.
> The point is to ensure that DMA memory accesses are properly ordered
> with the IO-accessing instructions.
Yes, I known it. writel() must be used for the write operations that control
"start/stop" or "enable/disable" function, to ensure that the data of previous
write operations reaches the target. I've met this kind of problem before.
>
> So, using readl_relaxed() with a read-modify-write is entirely sensible
> provided you do not access DMA memory inbetween.
Actually, I don't think this register is that complicated. I copied the code
back below. All the bits of L3_MAINT_CTRL are not affected by DMA access operations.
The software change the "range | op_type" to specify the operation type and scope,
the set the bit "L3_MAINT_STATUS_START" to start the operation. Then wait for that
bit to change from 1 to 0 by hardware.
+ reg = readl(l3_ctrl_base + L3_MAINT_CTRL);
+ reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK);
+ reg |= range | op_type;
+ reg |= L3_MAINT_STATUS_START;
+ writel(reg, l3_ctrl_base + L3_MAINT_CTRL);
+
+ /* Wait until the hardware maintenance operation is complete. */
+ do {
+ cpu_relax();
+ reg = readl(l3_ctrl_base + L3_MAINT_CTRL);
+ } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END);
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-30 2:53 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-16 3:27 [PATCH v5 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Zhen Lei
2021-01-16 3:27 ` [PATCH v5 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Zhen Lei
2021-01-28 14:29 ` Arnd Bergmann
2021-01-16 3:27 ` [PATCH v5 2/4] ARM: hisi: add support for Kunpeng50x SoC Zhen Lei
2021-01-28 14:28 ` Arnd Bergmann
2021-01-29 8:09 ` Leizhen (ThunderTown)
2021-01-16 3:27 ` [PATCH v5 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller Zhen Lei
2021-01-28 14:25 ` Arnd Bergmann
2021-01-16 3:27 ` [PATCH v5 4/4] ARM: Add support for Hisilicon " Zhen Lei
2021-01-28 14:24 ` Arnd Bergmann
2021-01-29 7:23 ` Leizhen (ThunderTown)
2021-01-29 8:16 ` Arnd Bergmann
2021-01-29 10:26 ` Arnd Bergmann
2021-01-29 10:33 ` Russell King - ARM Linux admin
2021-01-29 10:53 ` Arnd Bergmann
2021-01-29 11:11 ` Russell King - ARM Linux admin
2021-01-30 2:51 ` Leizhen (ThunderTown) [this message]
2021-01-29 13:54 ` Leizhen (ThunderTown)
2021-01-30 3:00 ` Leizhen (ThunderTown)
2021-01-29 13:33 ` Leizhen (ThunderTown)
2021-01-29 10:12 ` Russell King - ARM Linux admin
2021-01-29 13:33 ` Leizhen (ThunderTown)
2021-01-28 1:30 ` [PATCH v5 0/4] " Leizhen (ThunderTown)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b236bcbc-8610-dfc4-50f2-a4b71162735d@huawei.com \
--to=thunder.leizhen@huawei.com \
--cc=arnd@arndb.de \
--cc=arnd@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=haojian.zhuang@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=robh+dt@kernel.org \
--cc=will.deacon@arm.com \
--cc=xuwei5@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).