[PATCH 0/2] enable flexspi support on imx8mp

[PATCH 0/2] enable flexspi support on imx8mp

[Heiko Schocher]

This series enables support for the SPI NOR on the
imx8mp based phyboard-pollux-rdk board.



Heiko Schocher (2):
  arm64: dts: imx8mp: add flexspi node
  arm64: imx8mp: imx8mp-phycore-som enable spi nor

 .../dts/freescale/imx8mp-phycore-som.dtsi     | 27 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 16 +++++++++++
 2 files changed, 43 insertions(+)

-- 
2.29.2


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[PATCH 1/2] arm64: dts: imx8mp: add flexspi node

[Heiko Schocher]

add node for the flexspi modul on imx8mp.

Signed-off-by: Heiko Schocher <hs@denx.de>

---

 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c7523fd4eae9b..086cfbbef43d7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -36,6 +36,7 @@ aliases {
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
+		spi0 = &flexspi;
 	};
 
 	cpus {
@@ -744,6 +745,21 @@ usdhc3: mmc@30b60000 {
 				status = "disabled";
 			};
 
+			flexspi: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+					 <&clk IMX8MP_CLK_QSPI_ROOT>;
+				clock-names = "fspi", "fspi_en";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+				status = "disabled";
+			};
+
 			sdma1: dma-controller@30bd0000 {
 				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 				reg = <0x30bd0000 0x10000>;
-- 
2.29.2


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[PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Heiko Schocher]

enable the mt25qu256aba spi nor on the imx8mp-phycore-som.

Signed-off-by: Heiko Schocher <hs@denx.de>
---

 .../dts/freescale/imx8mp-phycore-som.dtsi     | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 44a8c2337cee4..0284e7a5c6bba 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
 	};
 };
 
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt25qu256aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x11
 		>;
 	};
 
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
-- 
2.29.2


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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Teresa Remmet]

Hello Heiko,

first thanks for the patch :).

Am Montag, den 08.03.2021, 07:40 +0100 schrieb Heiko Schocher:
> enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> 
>  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
> +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 44a8c2337cee4..0284e7a5c6bba 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
>  	};
>  };
>  
> +&flexspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexspi0>;
> +	status = "okay";
> +
> +	flash0: mt25qu256aba@0 {

you can remove the label. As it is not used here right now.
Also rename the node name to device type like "flash" maybe.

I will try to test this soon.

Thanks,
Teresa


> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		spi-max-frequency = <80000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <400000>;
>  	pinctrl-names = "default";
> @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		
> 0x11
>  		>;
>  	};
>  
> +	pinctrl_flexspi0: flexspi0grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		
> 0x1c2
> +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
> +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	
> 0x82
> +		>;
> +	};
> +
>  	pinctrl_i2c1: i2c1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400
> 001c3
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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Marco Felsch]

Hi Teresa, Heiko,

On 21-03-08 07:46, Teresa Remmet wrote:
> Hello Heiko,
> 
> first thanks for the patch :).
> 
> Am Montag, den 08.03.2021, 07:40 +0100 schrieb Heiko Schocher:
> > enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> > 
> > Signed-off-by: Heiko Schocher <hs@denx.de>
> > ---
> > 
> >  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
> > +++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > index 44a8c2337cee4..0284e7a5c6bba 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
> >  	};
> >  };
> >  
> > +&flexspi {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexspi0>;
> > +	status = "okay";
> > +
> > +	flash0: mt25qu256aba@0 {
> 
> you can remove the label. As it is not used here right now.

I would keep the label since most the time the bootloaders will fixup
the device tree because they adding a of-partition to it. It's mostly
just a matter of time.

> Also rename the node name to device type like "flash" maybe.

+1

I would name it 'som_flash: flash@0 { }'

Regards,
  Marco

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Re: [PATCH 1/2] arm64: dts: imx8mp: add flexspi node

[Marco Felsch]

Hi Heiko,

On 21-03-08 07:40, Heiko Schocher wrote:
> add node for the flexspi modul on imx8mp.
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> 
> ---
> 
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index c7523fd4eae9b..086cfbbef43d7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -36,6 +36,7 @@ aliases {
>  		serial1 = &uart2;
>  		serial2 = &uart3;
>  		serial3 = &uart4;
> +		spi0 = &flexspi;
>  	};
>  
>  	cpus {
> @@ -744,6 +745,21 @@ usdhc3: mmc@30b60000 {
>  				status = "disabled";
>  			};
>  
> +			flexspi: spi@30bb0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;

This properties can moved to end just in front of the status property
which should be the last one.

> +				compatible = "nxp,imx8mm-fspi";

Please add a own compatible "nxp,imx8mp-fspi" to the driver which should
be the first patch in your series.

Also the compatible is always the first property.

Regards,
  Marco

> +				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
> +				reg-names = "fspi_base", "fspi_mmap";
> +				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
> +					 <&clk IMX8MP_CLK_QSPI_ROOT>;
> +				clock-names = "fspi", "fspi_en";
> +				assigned-clock-rates = <80000000>;
> +				assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
> +				status = "disabled";
> +			};
> +
>  			sdma1: dma-controller@30bd0000 {
>  				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
>  				reg = <0x30bd0000 0x10000>;
> -- 
> 2.29.2
> 
> 
> 

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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Marco Felsch]

On 21-03-08 07:40, Heiko Schocher wrote:
> enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> 
>  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 44a8c2337cee4..0284e7a5c6bba 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
>  	};
>  };
>  
> +&flexspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexspi0>;
> +	status = "okay";
> +
> +	flash0: mt25qu256aba@0 {
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";

Please make the compatible the first property followed by the reg
property. Also you don't need to add the #size-cells and #address-cells
now since you don't add a child node.

Regards,
  Marco

> +		spi-max-frequency = <80000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <400000>;
>  	pinctrl-names = "default";
> @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x11
>  		>;
>  	};
>  
> +	pinctrl_flexspi0: flexspi0grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
> +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
> +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
> +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
> +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
> +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
> +		>;
> +	};
> +
>  	pinctrl_i2c1: i2c1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
> -- 
> 2.29.2
> 
> 
> 

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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Teresa Remmet]

Hello Marco,

Am Montag, den 08.03.2021, 09:40 +0100 schrieb Marco Felsch:
> On 21-03-08 07:40, Heiko Schocher wrote:
> > enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> > 
> > Signed-off-by: Heiko Schocher <hs@denx.de>
> > ---
> > 
> >  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
> > +++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > index 44a8c2337cee4..0284e7a5c6bba 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
> >  	};
> >  };
> >  
> > +&flexspi {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexspi0>;
> > +	status = "okay";
> > +
> > +	flash0: mt25qu256aba@0 {
> > +		reg = <0>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "jedec,spi-nor";
> 
> Please make the compatible the first property followed by the reg
> property. Also you don't need to add the #size-cells and #address-
> cells
> now since you don't add a child node.

but is this not similar to the label here? If you add partitions in the
bootloader you need the cells properties?

Teresa

> 
> Regards,
>   Marco
> 
> > +		spi-max-frequency = <80000000>;
> > +		spi-tx-bus-width = <4>;
> > +		spi-rx-bus-width = <4>;
> > +	};
> > +};
> > +
> >  &i2c1 {
> >  	clock-frequency = <400000>;
> >  	pinctrl-names = "default";
> > @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		
> > 0x11
> >  		>;
> >  	};
> >  
> > +	pinctrl_flexspi0: flexspi0grp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		
> > 0x1c2
> > +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x8
> > 2
> > +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x8
> > 2
> > +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x8
> > 2
> > +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x8
> > 2
> > +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x8
> > 2
> > +		>;
> > +	};
> > +
> >  	pinctrl_i2c1: i2c1grp {
> >  		fsl,pins = <
> >  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x4
> > 00001c3
> > -- 
> > 2.29.2
> > 
> > 
> > 
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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Marco Felsch]

On 21-03-08 08:52, Teresa Remmet wrote:
> Hello Marco,
> 
> Am Montag, den 08.03.2021, 09:40 +0100 schrieb Marco Felsch:
> > On 21-03-08 07:40, Heiko Schocher wrote:
> > > enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> > > 
> > > Signed-off-by: Heiko Schocher <hs@denx.de>
> > > ---
> > > 
> > >  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
> > > +++++++++++++++++++
> > >  1 file changed, 27 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > index 44a8c2337cee4..0284e7a5c6bba 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
> > >  	};
> > >  };
> > >  
> > > +&flexspi {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_flexspi0>;
> > > +	status = "okay";
> > > +
> > > +	flash0: mt25qu256aba@0 {
> > > +		reg = <0>;
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		compatible = "jedec,spi-nor";
> > 
> > Please make the compatible the first property followed by the reg
> > property. Also you don't need to add the #size-cells and #address-
> > cells
> > now since you don't add a child node.
> 
> but is this not similar to the label here? If you add partitions in the
> bootloader you need the cells properties?

If the bootloader will add partitions the bootloader can add the
size/address-cells too using the phandle. But this is more a nit.

Regards,
  Marco

> Teresa
> 
> > 
> > Regards,
> >   Marco
> > 
> > > +		spi-max-frequency = <80000000>;
> > > +		spi-tx-bus-width = <4>;
> > > +		spi-rx-bus-width = <4>;
> > > +	};
> > > +};
> > > +
> > >  &i2c1 {
> > >  	clock-frequency = <400000>;
> > >  	pinctrl-names = "default";
> > > @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		
> > > 0x11
> > >  		>;
> > >  	};
> > >  
> > > +	pinctrl_flexspi0: flexspi0grp {
> > > +		fsl,pins = <
> > > +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		
> > > 0x1c2
> > > +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x8
> > > 2
> > > +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x8
> > > 2
> > > +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x8
> > > 2
> > > +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x8
> > > 2
> > > +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x8
> > > 2
> > > +		>;
> > > +	};
> > > +
> > >  	pinctrl_i2c1: i2c1grp {
> > >  		fsl,pins = <
> > >  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x4
> > > 00001c3
> > > -- 
> > > 2.29.2
> > > 
> > > 
> > > 

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Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

[Heiko Schocher]

Hello Marco,

On 08.03.21 10:28, Marco Felsch wrote:
> On 21-03-08 08:52, Teresa Remmet wrote:
>> Hello Marco,
>>
>> Am Montag, den 08.03.2021, 09:40 +0100 schrieb Marco Felsch:
>>> On 21-03-08 07:40, Heiko Schocher wrote:
>>>> enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
>>>>
>>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>>> ---
>>>>
>>>>  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
>>>> +++++++++++++++++++
>>>>  1 file changed, 27 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
>>>> b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
>>>> index 44a8c2337cee4..0284e7a5c6bba 100644
>>>> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
>>>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
>>>> @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
>>>>  	};
>>>>  };
>>>>  
>>>> +&flexspi {
>>>> +	pinctrl-names = "default";
>>>> +	pinctrl-0 = <&pinctrl_flexspi0>;
>>>> +	status = "okay";
>>>> +
>>>> +	flash0: mt25qu256aba@0 {
>>>> +		reg = <0>;
>>>> +		#address-cells = <1>;
>>>> +		#size-cells = <1>;
>>>> +		compatible = "jedec,spi-nor";
>>>
>>> Please make the compatible the first property followed by the reg
>>> property. Also you don't need to add the #size-cells and #address-
>>> cells
>>> now since you don't add a child node.
>>
>> but is this not similar to the label here? If you add partitions in the
>> bootloader you need the cells properties?
> 
> If the bootloader will add partitions the bootloader can add the
> size/address-cells too using the phandle. But this is more a nit.

Yes. I personally prefer to pass mtd partitions through kernel commandline.

I will work in your and Teresas comment, thanks!

bye,
Heiko
> 
> Regards,
>   Marco
> 
>> Teresa
>>
>>>
>>> Regards,
>>>   Marco
>>>
>>>> +		spi-max-frequency = <80000000>;
>>>> +		spi-tx-bus-width = <4>;
>>>> +		spi-rx-bus-width = <4>;
>>>> +	};
>>>> +};
>>>> +
>>>>  &i2c1 {
>>>>  	clock-frequency = <400000>;
>>>>  	pinctrl-names = "default";
>>>> @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		
>>>> 0x11
>>>>  		>;
>>>>  	};
>>>>  
>>>> +	pinctrl_flexspi0: flexspi0grp {
>>>> +		fsl,pins = <
>>>> +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		
>>>> 0x1c2
>>>> +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x8
>>>> 2
>>>> +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x8
>>>> 2
>>>> +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x8
>>>> 2
>>>> +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x8
>>>> 2
>>>> +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x8
>>>> 2
>>>> +		>;
>>>> +	};
>>>> +
>>>>  	pinctrl_i2c1: i2c1grp {
>>>>  		fsl,pins = <
>>>>  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x4
>>>> 00001c3
>>>> -- 
>>>> 2.29.2
>>>>
>>>>
>>>>
> 

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