* [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor()
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-29 21:55 ` abhinavk
2021-03-27 11:02 ` [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov
` (23 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk, Daniel Palmer
From: Daniel Palmer <daniel@0x0f.com>
Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally
register fixed factor clocks for things like dividers don't need to manually unregister
them on remove or if probe fails.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------
include/linux/clk-provider.h | 4 +++-
2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 910e6e74ae90..4f7bf3929d6d 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = {
};
EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
+static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res)
+{
+ clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor *)res)->hw);
+}
+
static struct clk_hw *
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
const char *name, const char *parent_name, int index,
- unsigned long flags, unsigned int mult, unsigned int div)
+ unsigned long flags, unsigned int mult, unsigned int div,
+ bool devm)
{
struct clk_fixed_factor *fix;
struct clk_init_data init = { };
@@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
struct clk_hw *hw;
int ret;
- fix = kmalloc(sizeof(*fix), GFP_KERNEL);
+ /* You can't use devm without a dev */
+ if (devm && !dev)
+ return ERR_PTR(-EINVAL);
+
+ if (devm)
+ fix = devres_alloc(devm_clk_hw_register_fixed_factor_release,
+ sizeof(*fix), GFP_KERNEL);
+ else
+ fix = kmalloc(sizeof(*fix), GFP_KERNEL);
if (!fix)
return ERR_PTR(-ENOMEM);
@@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
else
ret = of_clk_hw_register(np, hw);
if (ret) {
- kfree(fix);
+ if (devm)
+ devres_free(fix);
+ else
+ kfree(fix);
hw = ERR_PTR(ret);
- }
+ } else if (devm)
+ devres_add(dev, fix);
return hw;
}
@@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
unsigned int mult, unsigned int div)
{
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
- flags, mult, div);
+ flags, mult, div, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
@@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
+struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div)
+{
+ return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
+ flags, mult, div, true);
+}
+EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
+
#ifdef CONFIG_OF
static const struct of_device_id set_rate_parent_matches[] = {
{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
@@ -185,7 +212,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
flags |= CLK_SET_RATE_PARENT;
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
- flags, mult, div);
+ flags, mult, div, false);
if (IS_ERR(hw)) {
/*
* Clear OF_POPULATED flag so that clock registration can be
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index e4316890661a..58f6fe866ae9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
-
+struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div);
/**
* struct clk_fractional_divider - adjustable fractional divider clock
*
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor()
2021-03-27 11:02 ` [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Dmitry Baryshkov
@ 2021-03-29 21:55 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-29 21:55 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, Daniel Palmer, dri-devel,
David Airlie, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> From: Daniel Palmer <daniel@0x0f.com>
>
> Add a devm helper for clk_hw_register_fixed_factor() so that drivers
> that internally
> register fixed factor clocks for things like dividers don't need to
> manually unregister
> them on remove or if probe fails.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> Link:
> https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com
> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------
> include/linux/clk-provider.h | 4 +++-
> 2 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-factor.c
> b/drivers/clk/clk-fixed-factor.c
> index 910e6e74ae90..4f7bf3929d6d 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
>
> +static void devm_clk_hw_register_fixed_factor_release(struct device
> *dev, void *res)
> +{
> + clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor
> *)res)->hw);
> +}
> +
> static struct clk_hw *
> __clk_hw_register_fixed_factor(struct device *dev, struct device_node
> *np,
> const char *name, const char *parent_name, int index,
> - unsigned long flags, unsigned int mult, unsigned int div)
> + unsigned long flags, unsigned int mult, unsigned int div,
> + bool devm)
> {
> struct clk_fixed_factor *fix;
> struct clk_init_data init = { };
> @@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev,
> struct device_node *np,
> struct clk_hw *hw;
> int ret;
>
> - fix = kmalloc(sizeof(*fix), GFP_KERNEL);
> + /* You can't use devm without a dev */
> + if (devm && !dev)
> + return ERR_PTR(-EINVAL);
> +
> + if (devm)
> + fix = devres_alloc(devm_clk_hw_register_fixed_factor_release,
> + sizeof(*fix), GFP_KERNEL);
> + else
> + fix = kmalloc(sizeof(*fix), GFP_KERNEL);
> if (!fix)
> return ERR_PTR(-ENOMEM);
>
> @@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev,
> struct device_node *np,
> else
> ret = of_clk_hw_register(np, hw);
> if (ret) {
> - kfree(fix);
> + if (devm)
> + devres_free(fix);
> + else
> + kfree(fix);
> hw = ERR_PTR(ret);
> - }
> + } else if (devm)
> + devres_add(dev, fix);
>
> return hw;
> }
> @@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct
> device *dev,
> unsigned int mult, unsigned int div)
> {
> return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name,
> -1,
> - flags, mult, div);
> + flags, mult, div, false);
> }
> EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
>
> @@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw
> *hw)
> }
> EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
>
> +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
> + const char *name, const char *parent_name, unsigned long flags,
> + unsigned int mult, unsigned int div)
> +{
> + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name,
> -1,
> + flags, mult, div, true);
> +}
> +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
> +
> #ifdef CONFIG_OF
> static const struct of_device_id set_rate_parent_matches[] = {
> { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
> @@ -185,7 +212,7 @@ static struct clk_hw
> *_of_fixed_factor_clk_setup(struct device_node *node)
> flags |= CLK_SET_RATE_PARENT;
>
> hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
> - flags, mult, div);
> + flags, mult, div, false);
> if (IS_ERR(hw)) {
> /*
> * Clear OF_POPULATED flag so that clock registration can be
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h
> index e4316890661a..58f6fe866ae9 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct
> device *dev,
> const char *name, const char *parent_name, unsigned long flags,
> unsigned int mult, unsigned int div);
> void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
> -
> +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
> + const char *name, const char *parent_name, unsigned long flags,
> + unsigned int mult, unsigned int div);
> /**
> * struct clk_fractional_divider - adjustable fractional divider clock
> *
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux()
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 0:46 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov
` (22 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Add devm_clk_hw_register_mux() - devres-managed version of
clk_hw_register_mux().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/clk/clk-mux.c | 35 +++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 13 +++++++++++++
2 files changed, 48 insertions(+)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index e54e79714818..20582aae7a35 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -8,6 +8,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
@@ -206,6 +207,40 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
}
EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
+static void devm_clk_hw_release_mux(struct device *dev, void *res)
+{
+ clk_hw_unregister_mux(*(struct clk_hw **)res);
+}
+
+struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
+ const char *name, u8 num_parents,
+ const char * const *parent_names,
+ const struct clk_hw **parent_hws,
+ const struct clk_parent_data *parent_data,
+ unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table, spinlock_t *lock)
+{
+ struct clk_hw **ptr, *hw;
+
+ ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, parent_hws,
+ parent_data, flags, reg, shift, mask,
+ clk_mux_flags, table, lock);
+
+ if (!IS_ERR(hw)) {
+ *ptr = hw;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return hw;
+}
+EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux);
+
struct clk *clk_register_mux_table(struct device *dev, const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 58f6fe866ae9..3eb15e0262f5 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -868,6 +868,13 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
const struct clk_parent_data *parent_data,
unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
+struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
+ const char *name, u8 num_parents,
+ const char * const *parent_names,
+ const struct clk_hw **parent_hws,
+ const struct clk_parent_data *parent_data,
+ unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table, spinlock_t *lock);
struct clk *clk_register_mux_table(struct device *dev, const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
@@ -902,6 +909,12 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
(parent_data), (flags), (reg), (shift), \
BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
+#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
+ shift, width, clk_mux_flags, lock) \
+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
+ (parent_names), NULL, NULL, (flags), (reg), \
+ (shift), BIT((width)) - 1, (clk_mux_flags), \
+ NULL, (lock))
int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
unsigned int val);
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux()
2021-03-27 11:02 ` [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov
@ 2021-03-30 0:46 ` Stephen Boyd
0 siblings, 0 replies; 50+ messages in thread
From: Stephen Boyd @ 2021-03-30 0:46 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Jonathan Marek,
Michael Turquette, Rob Clark, Sean Paul
Cc: David Airlie, Daniel Vetter, linux-arm-msm, dri-devel, freedreno,
linux-clk
Quoting Dmitry Baryshkov (2021-03-27 04:02:42)
> Add devm_clk_hw_register_mux() - devres-managed version of
> clk_hw_register_mux().
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 0:46 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 04/25] drm/msm/dsi: replace PHY's init callback with configurable data Dmitry Baryshkov
` (21 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Add devm_clk_hw_register_divider() - devres version of
clk_hw_register_divider().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
include/linux/clk-provider.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 3eb15e0262f5..162a2e5546a3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -785,6 +785,23 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
(parent_data), (flags), (reg), (shift), \
(width), (clk_divider_flags), (table), \
(lock))
+/**
+ * devm_clk_hw_register_divider - register a divider clock with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
+ width, clk_divider_flags, lock) \
+ __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
+ NULL, (flags), (reg), (shift), (width), \
+ (clk_divider_flags), NULL, (lock))
/**
* devm_clk_hw_register_divider_table - register a table based divider clock
* with the clock framework (devres variant)
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider
2021-03-27 11:02 ` [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov
@ 2021-03-30 0:46 ` Stephen Boyd
0 siblings, 0 replies; 50+ messages in thread
From: Stephen Boyd @ 2021-03-30 0:46 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Jonathan Marek,
Michael Turquette, Rob Clark, Sean Paul
Cc: David Airlie, Daniel Vetter, linux-arm-msm, dri-devel, freedreno,
linux-clk
Quoting Dmitry Baryshkov (2021-03-27 04:02:43)
> Add devm_clk_hw_register_divider() - devres version of
> clk_hw_register_divider().
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 04/25] drm/msm/dsi: replace PHY's init callback with configurable data
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (2 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 06/25] drm/msm/dsi: drop multiple pll enable_seq support Dmitry Baryshkov
` (20 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane
depending on the PHY type. Replace those callbacks with configuration
options governing mapping those regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 42 ++++++++-----------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 19 +--------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 19 +--------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 +--
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 19 +--------
8 files changed, 31 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index e8c1a727179c..83eb0a630443 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -637,24 +637,6 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
return -EINVAL;
}
-int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
-{
- struct platform_device *pdev = phy->pdev;
- int ret = 0;
-
- phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
- "DSI_PHY_REG");
- if (IS_ERR(phy->reg_base)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
- __func__);
- ret = -ENOMEM;
- goto fail;
- }
-
-fail:
- return ret;
-}
-
static int dsi_phy_driver_probe(struct platform_device *pdev)
{
struct msm_dsi_phy *phy;
@@ -691,6 +673,24 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail;
}
+ if (phy->cfg->has_phy_lane) {
+ phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
+ if (IS_ERR(phy->lane_base)) {
+ DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+
+ if (phy->cfg->has_phy_regulator) {
+ phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
+ if (IS_ERR(phy->reg_base)) {
+ DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+
ret = dsi_phy_regulator_init(phy);
if (ret)
goto fail;
@@ -702,12 +702,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail;
}
- if (phy->cfg->ops.init) {
- ret = phy->cfg->ops.init(phy);
- if (ret)
- goto fail;
- }
-
/* PLL init will call into clk_register which requires
* register access, so we need to enable power and ahb clock.
*/
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index d2bd74b6f357..03dfb08e7128 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -17,7 +17,6 @@
#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
struct msm_dsi_phy_ops {
- int (*init) (struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_phy_clk_request *clk_req);
void (*disable)(struct msm_dsi_phy *phy);
@@ -37,6 +36,8 @@ struct msm_dsi_phy_cfg {
const resource_size_t io_start[DSI_MAX];
const int num_dsi_phy;
const int quirks;
+ bool has_phy_regulator;
+ bool has_phy_lane;
};
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
@@ -106,7 +107,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask);
-int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
#endif /* __DSI_PHY_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index d1b92d4dc197..655fa17a0452 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -216,24 +216,10 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
DBG("DSI%d PHY disabled", phy->id);
}
-static int dsi_10nm_phy_init(struct msm_dsi_phy *phy)
-{
- struct platform_device *pdev = phy->pdev;
-
- phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
- "DSI_PHY_LANE");
- if (IS_ERR(phy->lane_base)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
- __func__);
- return -ENOMEM;
- }
-
- return 0;
-}
-
const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -243,7 +229,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.ops = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
- .init = dsi_10nm_phy_init,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
@@ -252,6 +237,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -261,7 +247,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.ops = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
- .init = dsi_10nm_phy_init,
},
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 519400501bcd..6989730b5fbd 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -129,24 +129,10 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
wmb();
}
-static int dsi_14nm_phy_init(struct msm_dsi_phy *phy)
-{
- struct platform_device *pdev = phy->pdev;
-
- phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
- "DSI_PHY_LANE");
- if (IS_ERR(phy->lane_base)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
- __func__);
- return -ENOMEM;
- }
-
- return 0;
-}
-
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -156,7 +142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
- .init = dsi_14nm_phy_init,
},
.io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2,
@@ -165,6 +150,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -174,7 +160,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
- .init = dsi_14nm_phy_init,
},
.io_start = { 0xc994400, 0xc996000 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index eca86bf448f7..b752636f7f21 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -127,6 +127,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
.type = MSM_DSI_PHY_20NM,
.src_pll_truthtable = { {false, true}, {false, true} },
+ .has_phy_regulator = true,
.reg_cfg = {
.num = 2,
.regs = {
@@ -137,7 +138,6 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
.ops = {
.enable = dsi_20nm_phy_enable,
.disable = dsi_20nm_phy_disable,
- .init = msm_dsi_phy_init_common,
},
.io_start = { 0xfd998500, 0xfd9a0500 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index c3c580cfd8b1..5bf79de0da67 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -153,6 +153,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} },
+ .has_phy_regulator = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -162,7 +163,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
- .init = msm_dsi_phy_init_common,
},
.io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2,
@@ -171,6 +171,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} },
+ .has_phy_regulator = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -180,7 +181,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
- .init = msm_dsi_phy_init_common,
},
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
@@ -189,6 +189,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.type = MSM_DSI_PHY_28NM_LP,
.src_pll_truthtable = { {true, true}, {true, true} },
+ .has_phy_regulator = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -198,7 +199,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
- .init = msm_dsi_phy_init_common,
},
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index f22583353957..5d33de27a0f4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -176,6 +176,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.type = MSM_DSI_PHY_28NM_8960,
.src_pll_truthtable = { {true, true}, {false, true} },
+ .has_phy_regulator = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -185,7 +186,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
- .init = msm_dsi_phy_init_common,
},
.io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 79c034ae075d..cbfeec860e69 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -224,24 +224,10 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
DBG("DSI%d PHY disabled", phy->id);
}
-static int dsi_7nm_phy_init(struct msm_dsi_phy *phy)
-{
- struct platform_device *pdev = phy->pdev;
-
- phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
- "DSI_PHY_LANE");
- if (IS_ERR(phy->lane_base)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
- __func__);
- return -ENOMEM;
- }
-
- return 0;
-}
-
const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.type = MSM_DSI_PHY_7NM_V4_1,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -251,7 +237,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.ops = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
- .init = dsi_7nm_phy_init,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
@@ -260,6 +245,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.type = MSM_DSI_PHY_7NM,
.src_pll_truthtable = { {false, false}, {true, false} },
+ .has_phy_lane = true,
.reg_cfg = {
.num = 1,
.regs = {
@@ -269,7 +255,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.ops = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
- .init = dsi_7nm_phy_init,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 06/25] drm/msm/dsi: drop multiple pll enable_seq support
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (3 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 04/25] drm/msm/dsi: replace PHY's init callback with configurable data Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 07/25] drm/msm/dsi: move all PLL callbacks into PHY config struct Dmitry Baryshkov
` (19 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
The only PLL using multiple enable sequences is the 28nm PLL, which just
does the single step in the loop. Push that support back into the PLL
code.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 23 +++++--
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 3 +-
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 65 +++++++------------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 +-
5 files changed, 42 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 6a63901da7a4..4386edfa91fe 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1087,8 +1087,7 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
pll_14nm->vco_delay = 1;
- pll->en_seq_cnt = 1;
- pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
+ pll->enable_seq = dsi_pll_14nm_enable_seq;
ret = pll_14nm_register(pll_14nm);
if (ret) {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 2f502efa4dd5..760cf7956fa2 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -311,7 +311,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
/*
* PLL Callbacks
*/
-static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
@@ -386,6 +386,19 @@ static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
return locked ? 0 : -EINVAL;
}
+static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+{
+ int i, ret;
+
+ for (i = 0; i < 3; i++) {
+ ret = _dsi_pll_28nm_enable_seq_hpm(pll);
+ if (!ret)
+ return 0;
+ }
+
+ return ret;
+}
+
static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -619,15 +632,11 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
if (type == MSM_DSI_PHY_28NM_HPM) {
pll_28nm->vco_delay = 1;
- pll->en_seq_cnt = 3;
- pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm;
- pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm;
- pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm;
+ pll->enable_seq = dsi_pll_28nm_enable_seq_hpm;
} else if (type == MSM_DSI_PHY_28NM_LP) {
pll_28nm->vco_delay = 1000;
- pll->en_seq_cnt = 1;
- pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp;
+ pll->enable_seq = dsi_pll_28nm_enable_seq_lp;
} else {
DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type);
return ERR_PTR(-EINVAL);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 4a40513057e8..2cfb7edf91d8 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -515,8 +515,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
pll->save_state = dsi_pll_28nm_save_state;
pll->restore_state = dsi_pll_28nm_restore_state;
- pll->en_seq_cnt = 1;
- pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
+ pll->enable_seq = dsi_pll_28nm_enable_seq;
ret = pll_28nm_register(pll_28nm);
if (ret) {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 3dc65877fa10..9e9fa90bf504 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -5,46 +5,6 @@
#include "dsi_pll.h"
-static int dsi_pll_enable(struct msm_dsi_pll *pll)
-{
- int i, ret = 0;
-
- /*
- * Certain PLLs do not allow VCO rate update when it is on.
- * Keep track of their status to turn on/off after set rate success.
- */
- if (unlikely(pll->pll_on))
- return 0;
-
- /* Try all enable sequences until one succeeds */
- for (i = 0; i < pll->en_seq_cnt; i++) {
- ret = pll->enable_seqs[i](pll);
- DBG("DSI PLL %s after sequence #%d",
- ret ? "unlocked" : "locked", i + 1);
- if (!ret)
- break;
- }
-
- if (ret) {
- DRM_ERROR("DSI PLL failed to lock\n");
- return ret;
- }
-
- pll->pll_on = true;
-
- return 0;
-}
-
-static void dsi_pll_disable(struct msm_dsi_pll *pll)
-{
- if (unlikely(!pll->pll_on))
- return;
-
- pll->disable_seq(pll);
-
- pll->pll_on = false;
-}
-
/*
* DSI PLL Helper functions
*/
@@ -64,15 +24,36 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ int ret = 0;
- return dsi_pll_enable(pll);
+ /*
+ * Certain PLLs do not allow VCO rate update when it is on.
+ * Keep track of their status to turn on/off after set rate success.
+ */
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ ret = pll->enable_seq(pll);
+ if (ret) {
+ DRM_ERROR("DSI PLL failed to lock\n");
+ return ret;
+ }
+
+ pll->pll_on = true;
+
+ return 0;
}
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- dsi_pll_disable(pll);
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll->disable_seq(pll);
+
+ pll->pll_on = false;
}
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index bbecb1de5678..eebf90671eec 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -12,7 +12,6 @@
#include "dsi.h"
#define NUM_DSI_CLOCKS_MAX 6
-#define MAX_DSI_PLL_EN_SEQS 10
struct msm_dsi_pll {
enum msm_dsi_phy_type type;
@@ -23,9 +22,8 @@ struct msm_dsi_pll {
unsigned long min_rate;
unsigned long max_rate;
- u32 en_seq_cnt;
- int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
+ int (*enable_seq)(struct msm_dsi_pll *pll);
void (*disable_seq)(struct msm_dsi_pll *pll);
int (*get_provider)(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider,
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 07/25] drm/msm/dsi: move all PLL callbacks into PHY config struct
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (4 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 06/25] drm/msm/dsi: drop multiple pll enable_seq support Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 08/25] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Dmitry Baryshkov
` (18 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits
the amount of data in the struct msm_dsi_pll.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 14 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 15 +++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 38 ++++++++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 47 ++++++++-----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 65 ++++++++++++------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 33 +++++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 49 +++++++++-----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 67 ++++---------------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 67 +------------------
10 files changed, 191 insertions(+), 210 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 78ef5d4ed922..21cf883fb6f1 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -107,8 +107,6 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
/* dsi pll */
struct msm_dsi_pll;
#ifdef CONFIG_DRM_MSM_DSI_PLL
-struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int dsi_id);
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
@@ -117,10 +115,6 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
enum msm_dsi_phy_usecase uc);
#else
-static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id) {
- return ERR_PTR(-ENODEV);
-}
static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 83eb0a630443..5f153b683521 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -709,12 +709,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
if (ret)
goto fail;
- phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
- if (IS_ERR_OR_NULL(phy->pll)) {
- DRM_DEV_INFO(dev,
- "%s: pll init failed: %ld, need separate pll clk driver\n",
- __func__, PTR_ERR(phy->pll));
- phy->pll = NULL;
+ if (phy->cfg->ops.pll_init) {
+ ret = phy->cfg->ops.pll_init(phy);
+ if (ret) {
+ DRM_DEV_INFO(dev,
+ "%s: pll init failed: %d, need separate pll clk driver\n",
+ __func__, ret);
+ goto fail;
+ }
}
dsi_phy_disable_resource(phy);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 03dfb08e7128..244d2c900d40 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -17,15 +17,30 @@
#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
struct msm_dsi_phy_ops {
+ int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_phy_clk_request *clk_req);
void (*disable)(struct msm_dsi_phy *phy);
};
+struct msm_dsi_pll_ops {
+ int (*enable_seq)(struct msm_dsi_pll *pll);
+ void (*disable_seq)(struct msm_dsi_pll *pll);
+ int (*get_provider)(struct msm_dsi_pll *pll,
+ struct clk **byte_clk_provider,
+ struct clk **pixel_clk_provider);
+ void (*destroy)(struct msm_dsi_pll *pll);
+ void (*save_state)(struct msm_dsi_pll *pll);
+ int (*restore_state)(struct msm_dsi_pll *pll);
+ int (*set_usecase)(struct msm_dsi_pll *pll,
+ enum msm_dsi_phy_usecase uc);
+};
+
struct msm_dsi_phy_cfg {
enum msm_dsi_phy_type type;
struct dsi_reg_config reg_cfg;
struct msm_dsi_phy_ops ops;
+ const struct msm_dsi_pll_ops pll_ops;
/*
* Each cell {phy_id, pll_id} of the truth table indicates
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 5da369b5c475..f697ff9a0d8e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -828,15 +828,17 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
return ret;
}
-struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
+static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
{
+ struct platform_device *pdev = phy->pdev;
+ int id = phy->id;
struct dsi_pll_10nm *pll_10nm;
struct msm_dsi_pll *pll;
int ret;
pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
if (!pll_10nm)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
DBG("DSI PLL%d", id);
@@ -847,13 +849,13 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
spin_lock_init(&pll_10nm->postdiv_lock);
@@ -861,24 +863,22 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
pll = &pll_10nm->base;
pll->min_rate = 1000000000UL;
pll->max_rate = 3500000000UL;
- pll->get_provider = dsi_pll_10nm_get_provider;
- pll->destroy = dsi_pll_10nm_destroy;
- pll->save_state = dsi_pll_10nm_save_state;
- pll->restore_state = dsi_pll_10nm_restore_state;
- pll->set_usecase = dsi_pll_10nm_set_usecase;
+ pll->cfg = phy->cfg;
pll_10nm->vco_delay = 1;
ret = pll_10nm_register(pll_10nm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ERR_PTR(ret);
+ return ret;
}
+ phy->pll = pll;
+
/* TODO: Remove this when we have proper display handover support */
msm_dsi_pll_save_state(pll);
- return pll;
+ return 0;
}
static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
@@ -1102,6 +1102,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.ops = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
+ .pll_init = dsi_pll_10nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_10nm_get_provider,
+ .destroy = dsi_pll_10nm_destroy,
+ .save_state = dsi_pll_10nm_save_state,
+ .restore_state = dsi_pll_10nm_restore_state,
+ .set_usecase = dsi_pll_10nm_set_usecase,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
@@ -1120,6 +1128,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.ops = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
+ .pll_init = dsi_pll_10nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_10nm_get_provider,
+ .destroy = dsi_pll_10nm_destroy,
+ .save_state = dsi_pll_10nm_save_state,
+ .restore_state = dsi_pll_10nm_restore_state,
+ .set_usecase = dsi_pll_10nm_set_usecase,
},
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 4386edfa91fe..011d285bf2c0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1042,18 +1042,20 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
return 0;
}
-struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
+static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
{
+ struct platform_device *pdev = phy->pdev;
+ int id = phy->id;
struct dsi_pll_14nm *pll_14nm;
struct msm_dsi_pll *pll;
int ret;
if (!pdev)
- return ERR_PTR(-ENODEV);
+ return -ENODEV;
pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
if (!pll_14nm)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
DBG("PLL%d", id);
@@ -1064,13 +1066,13 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
spin_lock_init(&pll_14nm->postdiv_lock);
@@ -1078,24 +1080,19 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
pll = &pll_14nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
- pll->get_provider = dsi_pll_14nm_get_provider;
- pll->destroy = dsi_pll_14nm_destroy;
- pll->disable_seq = dsi_pll_14nm_disable_seq;
- pll->save_state = dsi_pll_14nm_save_state;
- pll->restore_state = dsi_pll_14nm_restore_state;
- pll->set_usecase = dsi_pll_14nm_set_usecase;
+ pll->cfg = phy->cfg;
pll_14nm->vco_delay = 1;
- pll->enable_seq = dsi_pll_14nm_enable_seq;
-
ret = pll_14nm_register(pll_14nm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ERR_PTR(ret);
+ return ret;
}
- return pll;
+ phy->pll = pll;
+
+ return 0;
}
static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
@@ -1230,6 +1227,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
+ .pll_init = dsi_pll_14nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_14nm_get_provider,
+ .destroy = dsi_pll_14nm_destroy,
+ .save_state = dsi_pll_14nm_save_state,
+ .restore_state = dsi_pll_14nm_restore_state,
+ .set_usecase = dsi_pll_14nm_set_usecase,
+ .disable_seq = dsi_pll_14nm_disable_seq,
+ .enable_seq = dsi_pll_14nm_enable_seq,
},
.io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2,
@@ -1248,6 +1255,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
+ .pll_init = dsi_pll_14nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_14nm_get_provider,
+ .destroy = dsi_pll_14nm_destroy,
+ .save_state = dsi_pll_14nm_save_state,
+ .restore_state = dsi_pll_14nm_restore_state,
+ .set_usecase = dsi_pll_14nm_set_usecase,
+ .disable_seq = dsi_pll_14nm_disable_seq,
+ .enable_seq = dsi_pll_14nm_enable_seq,
},
.io_start = { 0xc994400, 0xc996000 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 760cf7956fa2..fb6e19d9495d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -597,19 +597,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
return 0;
}
-struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id)
+static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
{
+ struct platform_device *pdev = phy->pdev;
+ int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
int ret;
if (!pdev)
- return ERR_PTR(-ENODEV);
+ return -ENODEV;
pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
if (!pll_28nm)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
pll_28nm->pdev = pdev;
pll_28nm->id = id;
@@ -617,40 +618,33 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
pll = &pll_28nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
- pll->get_provider = dsi_pll_28nm_get_provider;
- pll->destroy = dsi_pll_28nm_destroy;
- pll->disable_seq = dsi_pll_28nm_disable_seq;
- pll->save_state = dsi_pll_28nm_save_state;
- pll->restore_state = dsi_pll_28nm_restore_state;
-
- if (type == MSM_DSI_PHY_28NM_HPM) {
+ if (phy->cfg->type == MSM_DSI_PHY_28NM_HPM) {
pll_28nm->vco_delay = 1;
-
- pll->enable_seq = dsi_pll_28nm_enable_seq_hpm;
- } else if (type == MSM_DSI_PHY_28NM_LP) {
+ } else if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) {
pll_28nm->vco_delay = 1000;
-
- pll->enable_seq = dsi_pll_28nm_enable_seq_lp;
} else {
- DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type);
- return ERR_PTR(-EINVAL);
+ DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", phy->cfg->type);
+ return -EINVAL;
}
+ pll->cfg = phy->cfg;
+
ret = pll_28nm_register(pll_28nm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ERR_PTR(ret);
+ return ret;
}
- return pll;
-}
+ phy->pll = pll;
+ return 0;
+}
static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
struct msm_dsi_dphy_timing *timing)
@@ -809,6 +803,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_28nm_get_provider,
+ .destroy = dsi_pll_28nm_destroy,
+ .save_state = dsi_pll_28nm_save_state,
+ .restore_state = dsi_pll_28nm_restore_state,
+ .disable_seq = dsi_pll_28nm_disable_seq,
+ .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2,
@@ -827,6 +830,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_28nm_get_provider,
+ .destroy = dsi_pll_28nm_destroy,
+ .save_state = dsi_pll_28nm_save_state,
+ .restore_state = dsi_pll_28nm_restore_state,
+ .disable_seq = dsi_pll_28nm_disable_seq,
+ .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
@@ -845,6 +857,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_28nm_get_provider,
+ .destroy = dsi_pll_28nm_destroy,
+ .save_state = dsi_pll_28nm_save_state,
+ .restore_state = dsi_pll_28nm_restore_state,
+ .disable_seq = dsi_pll_28nm_disable_seq,
+ .enable_seq = dsi_pll_28nm_enable_seq_lp,
},
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 2cfb7edf91d8..08f31be3b0dc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -483,19 +483,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
return 0;
}
-struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
- int id)
+static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
{
+ struct platform_device *pdev = phy->pdev;
+ int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
int ret;
if (!pdev)
- return ERR_PTR(-ENODEV);
+ return -ENODEV;
pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
if (!pll_28nm)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
@@ -503,27 +504,24 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
pll = &pll_28nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
- pll->get_provider = dsi_pll_28nm_get_provider;
- pll->destroy = dsi_pll_28nm_destroy;
- pll->disable_seq = dsi_pll_28nm_disable_seq;
- pll->save_state = dsi_pll_28nm_save_state;
- pll->restore_state = dsi_pll_28nm_restore_state;
- pll->enable_seq = dsi_pll_28nm_enable_seq;
+ pll->cfg = phy->cfg;
ret = pll_28nm_register(pll_28nm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ERR_PTR(ret);
+ return ret;
}
- return pll;
+ phy->pll = pll;
+
+ return 0;
}
static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
@@ -704,6 +702,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_8960_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_28nm_get_provider,
+ .destroy = dsi_pll_28nm_destroy,
+ .save_state = dsi_pll_28nm_save_state,
+ .restore_state = dsi_pll_28nm_restore_state,
+ .disable_seq = dsi_pll_28nm_disable_seq,
+ .enable_seq = dsi_pll_28nm_enable_seq,
},
.io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index f9af9d70b56a..68b54e5060e4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -178,7 +178,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
dec = div_u64(dec_multiple, multiplier);
- if (pll->base.type != MSM_DSI_PHY_7NM_V4_1)
+ if (pll->base.cfg->type != MSM_DSI_PHY_7NM_V4_1)
regs->pll_clock_inverters = 0x28;
else if (pll_freq <= 1000000000ULL)
regs->pll_clock_inverters = 0xa0;
@@ -273,7 +273,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
void __iomem *base = pll->mmio;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
- if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) {
+ if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) {
if (pll->vco_current_rate >= 3100000000ULL)
analog_controls_five_1 = 0x03;
@@ -307,9 +307,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
- pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22);
+ pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22);
- if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) {
+ if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) {
pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
@@ -853,16 +853,17 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
return ret;
}
-struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id)
+static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
{
+ struct platform_device *pdev = phy->pdev;
+ int id = phy->id;
struct dsi_pll_7nm *pll_7nm;
struct msm_dsi_pll *pll;
int ret;
pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
if (!pll_7nm)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
DBG("DSI PLL%d", id);
@@ -873,13 +874,13 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_7nm->mmio)) {
DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
spin_lock_init(&pll_7nm->postdiv_lock);
@@ -887,30 +888,28 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
pll = &pll_7nm->base;
pll->min_rate = 1000000000UL;
pll->max_rate = 3500000000UL;
- if (type == MSM_DSI_PHY_7NM_V4_1) {
+ if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) {
pll->min_rate = 600000000UL;
pll->max_rate = (unsigned long)5000000000ULL;
/* workaround for max rate overflowing on 32-bit builds: */
pll->max_rate = max(pll->max_rate, 0xffffffffUL);
}
- pll->get_provider = dsi_pll_7nm_get_provider;
- pll->destroy = dsi_pll_7nm_destroy;
- pll->save_state = dsi_pll_7nm_save_state;
- pll->restore_state = dsi_pll_7nm_restore_state;
- pll->set_usecase = dsi_pll_7nm_set_usecase;
+ pll->cfg = phy->cfg;
pll_7nm->vco_delay = 1;
ret = pll_7nm_register(pll_7nm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ERR_PTR(ret);
+ return ret;
}
+ phy->pll = pll;
+
/* TODO: Remove this when we have proper display handover support */
msm_dsi_pll_save_state(pll);
- return pll;
+ return 0;
}
static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
@@ -1142,6 +1141,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.ops = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_7nm_get_provider,
+ .destroy = dsi_pll_7nm_destroy,
+ .save_state = dsi_pll_7nm_save_state,
+ .restore_state = dsi_pll_7nm_restore_state,
+ .set_usecase = dsi_pll_7nm_set_usecase,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
@@ -1160,6 +1167,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.ops = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ },
+ .pll_ops = {
+ .get_provider = dsi_pll_7nm_get_provider,
+ .destroy = dsi_pll_7nm_destroy,
+ .save_state = dsi_pll_7nm_save_state,
+ .restore_state = dsi_pll_7nm_restore_state,
+ .set_usecase = dsi_pll_7nm_set_usecase,
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 9e9fa90bf504..c7ff0eba0e8b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -3,6 +3,7 @@
* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*/
+#include "dsi_phy.h"
#include "dsi_pll.h"
/*
@@ -33,7 +34,7 @@ int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
if (unlikely(pll->pll_on))
return 0;
- ret = pll->enable_seq(pll);
+ ret = pll->cfg->pll_ops.enable_seq(pll);
if (ret) {
DRM_ERROR("DSI PLL failed to lock\n");
return ret;
@@ -51,7 +52,7 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
if (unlikely(!pll->pll_on))
return;
- pll->disable_seq(pll);
+ pll->cfg->pll_ops.disable_seq(pll);
pll->pll_on = false;
}
@@ -76,8 +77,8 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
{
- if (pll->get_provider)
- return pll->get_provider(pll,
+ if (pll->cfg->pll_ops.get_provider)
+ return pll->cfg->pll_ops.get_provider(pll,
byte_clk_provider,
pixel_clk_provider);
@@ -86,14 +87,14 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
- if (pll->destroy)
- pll->destroy(pll);
+ if (pll->cfg->pll_ops.destroy)
+ pll->cfg->pll_ops.destroy(pll);
}
void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
{
- if (pll->save_state) {
- pll->save_state(pll);
+ if (pll->cfg->pll_ops.save_state) {
+ pll->cfg->pll_ops.save_state(pll);
pll->state_saved = true;
}
}
@@ -102,8 +103,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
{
int ret;
- if (pll->restore_state && pll->state_saved) {
- ret = pll->restore_state(pll);
+ if (pll->cfg->pll_ops.restore_state && pll->state_saved) {
+ ret = pll->cfg->pll_ops.restore_state(pll);
if (ret)
return ret;
@@ -116,50 +117,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
enum msm_dsi_phy_usecase uc)
{
- if (pll->set_usecase)
- return pll->set_usecase(pll, uc);
+ if (pll->cfg->pll_ops.set_usecase)
+ return pll->cfg->pll_ops.set_usecase(pll, uc);
return 0;
}
-
-struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id)
-{
- struct device *dev = &pdev->dev;
- struct msm_dsi_pll *pll;
-
- switch (type) {
- case MSM_DSI_PHY_28NM_HPM:
- case MSM_DSI_PHY_28NM_LP:
- pll = msm_dsi_pll_28nm_init(pdev, type, id);
- break;
- case MSM_DSI_PHY_28NM_8960:
- pll = msm_dsi_pll_28nm_8960_init(pdev, id);
- break;
- case MSM_DSI_PHY_14NM:
- pll = msm_dsi_pll_14nm_init(pdev, id);
- break;
- case MSM_DSI_PHY_10NM:
- pll = msm_dsi_pll_10nm_init(pdev, id);
- break;
- case MSM_DSI_PHY_7NM:
- case MSM_DSI_PHY_7NM_V4_1:
- pll = msm_dsi_pll_7nm_init(pdev, type, id);
- break;
- default:
- pll = ERR_PTR(-ENXIO);
- break;
- }
-
- if (IS_ERR(pll)) {
- DRM_DEV_ERROR(dev, "%s: failed to init DSI PLL\n", __func__);
- return pll;
- }
-
- pll->type = type;
-
- DBG("DSI:%d PLL registered", id);
-
- return pll;
-}
-
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index eebf90671eec..4fa73fbcba52 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -14,8 +14,6 @@
#define NUM_DSI_CLOCKS_MAX 6
struct msm_dsi_pll {
- enum msm_dsi_phy_type type;
-
struct clk_hw clk_hw;
bool pll_on;
bool state_saved;
@@ -23,16 +21,7 @@ struct msm_dsi_pll {
unsigned long min_rate;
unsigned long max_rate;
- int (*enable_seq)(struct msm_dsi_pll *pll);
- void (*disable_seq)(struct msm_dsi_pll *pll);
- int (*get_provider)(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider);
- void (*destroy)(struct msm_dsi_pll *pll);
- void (*save_state)(struct msm_dsi_pll *pll);
- int (*restore_state)(struct msm_dsi_pll *pll);
- int (*set_usecase)(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc);
+ const struct msm_dsi_phy_cfg *cfg;
};
#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
@@ -72,59 +61,5 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
struct clk **clks, u32 num_clks);
-/*
- * Initialization for Each PLL Type
- */
-#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
-struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id);
-#else
-static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
- struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
-#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
-struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
- int id);
-#else
-static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(
- struct platform_device *pdev, int id)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
-
-#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
-struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id);
-#else
-static inline struct msm_dsi_pll *
-msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
-#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
-struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id);
-#else
-static inline struct msm_dsi_pll *
-msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
-#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
-struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id);
-#else
-static inline struct msm_dsi_pll *
-msm_dsi_pll_7nm_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int id)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
-
#endif /* __DSI_PLL_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 08/25] drm/msm/dsi: drop global msm_dsi_phy_type enumaration
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (5 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 07/25] drm/msm/dsi: move all PLL callbacks into PHY config struct Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 09/25] drm/msm/dsi: move min/max PLL rate to phy config Dmitry Baryshkov
` (17 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
With the current upstream driver the msm_dsi_phy_type enum does not make
much sense: all DSI PHYs are probed using the dt bindings, the phy type
is not passed between drivers. Use quirks in phy individual PHY drivers
to differentiate minor harware differences and drop the enum.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 12 -----------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 ----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 11 +++++-----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 19 ++++++++----------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 20 ++++++++++---------
8 files changed, 25 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 21cf883fb6f1..98a4b296fa30 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -23,18 +23,6 @@
struct msm_dsi_phy_shared_timings;
struct msm_dsi_phy_clk_request;
-enum msm_dsi_phy_type {
- MSM_DSI_PHY_28NM_HPM,
- MSM_DSI_PHY_28NM_LP,
- MSM_DSI_PHY_20NM,
- MSM_DSI_PHY_28NM_8960,
- MSM_DSI_PHY_14NM,
- MSM_DSI_PHY_10NM,
- MSM_DSI_PHY_7NM,
- MSM_DSI_PHY_7NM_V4_1,
- MSM_DSI_PHY_MAX
-};
-
enum msm_dsi_phy_usecase {
MSM_DSI_PHY_STANDALONE,
MSM_DSI_PHY_MASTER,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 244d2c900d40..39abb86446f9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -13,9 +13,6 @@
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-/* v3.0.0 10nm implementation that requires the old timings settings */
-#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
-
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
@@ -37,7 +34,6 @@ struct msm_dsi_pll_ops {
};
struct msm_dsi_phy_cfg {
- enum msm_dsi_phy_type type;
struct dsi_reg_config reg_cfg;
struct msm_dsi_phy_ops ops;
const struct msm_dsi_pll_ops pll_ops;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index f697ff9a0d8e..dc8ccc994759 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -59,6 +59,9 @@ struct dsi_pll_regs {
u32 ssc_control;
};
+/* v3.0.0 10nm implementation that requires the old timings settings */
+#define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0)
+
struct dsi_pll_config {
u32 ref_freq;
bool div_override;
@@ -915,7 +918,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
void __iomem *lane_base = phy->lane_base;
- if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)
+ if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)
tx_dctrl[3] = 0x02;
/* Strength ctrl settings */
@@ -950,7 +953,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
tx_dctrl[i]);
}
- if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) {
+ if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) {
/* Toggle BIT 0 to release freeze I/0 */
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
@@ -1090,7 +1093,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
- .type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
@@ -1116,7 +1118,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
- .type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
@@ -1139,5 +1140,5 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
},
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
- .quirks = V3_0_0_10NM_OLD_TIMINGS_QUIRK,
+ .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 011d285bf2c0..d78f846cf8e4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1215,7 +1215,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
- .type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
@@ -1243,7 +1242,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
- .type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index b752636f7f21..5e73f811d645 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -125,7 +125,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
- .type = MSM_DSI_PHY_20NM,
.src_pll_truthtable = { {false, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index fb6e19d9495d..bb33261d606d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -40,6 +40,9 @@
#define DSI_BYTE_PLL_CLK 0
#define DSI_PIXEL_PLL_CLK 1
+/* v2.0.0 28nm LP implementation */
+#define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
+
#define LPFR_LUT_SIZE 10
struct lpfr_cfg {
unsigned long vco_rate;
@@ -624,14 +627,10 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
pll = &pll_28nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
- if (phy->cfg->type == MSM_DSI_PHY_28NM_HPM) {
- pll_28nm->vco_delay = 1;
- } else if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) {
+ if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
pll_28nm->vco_delay = 1000;
- } else {
- DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", phy->cfg->type);
- return -EINVAL;
- }
+ else
+ pll_28nm->vco_delay = 1;
pll->cfg = phy->cfg;
@@ -706,7 +705,7 @@ static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1);
dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
- if (phy->cfg->type == MSM_DSI_PHY_28NM_LP)
+ if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05);
else
dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d);
@@ -791,7 +790,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
- .type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
@@ -818,7 +816,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
- .type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
@@ -845,7 +842,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
- .type = MSM_DSI_PHY_28NM_LP,
.src_pll_truthtable = { {true, true}, {true, true} },
.has_phy_regulator = true,
.reg_cfg = {
@@ -869,5 +865,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
},
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
+ .quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 08f31be3b0dc..79b0842a8dc4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -690,7 +690,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
- .type = MSM_DSI_PHY_28NM_8960,
.src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 68b54e5060e4..44ae495e8fca 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -59,6 +59,9 @@ struct dsi_pll_regs {
u32 ssc_control;
};
+/* Hardware is V4.1 */
+#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
+
struct dsi_pll_config {
u32 ref_freq;
bool div_override;
@@ -178,7 +181,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
dec = div_u64(dec_multiple, multiplier);
- if (pll->base.cfg->type != MSM_DSI_PHY_7NM_V4_1)
+ if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
regs->pll_clock_inverters = 0x28;
else if (pll_freq <= 1000000000ULL)
regs->pll_clock_inverters = 0xa0;
@@ -273,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
void __iomem *base = pll->mmio;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
- if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) {
+ if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
if (pll->vco_current_rate >= 3100000000ULL)
analog_controls_five_1 = 0x03;
@@ -307,9 +310,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
- pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22);
+ pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
- if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) {
+ if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
@@ -888,7 +891,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
pll = &pll_7nm->base;
pll->min_rate = 1000000000UL;
pll->max_rate = 3500000000UL;
- if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) {
+ if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
pll->min_rate = 600000000UL;
pll->max_rate = (unsigned long)5000000000ULL;
/* workaround for max rate overflowing on 32-bit builds: */
@@ -948,7 +951,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
const u8 *tx_dctrl = tx_dctrl_0;
void __iomem *lane_base = phy->lane_base;
- if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1)
+ if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
tx_dctrl = tx_dctrl_1;
/* Strength ctrl settings */
@@ -1012,7 +1015,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
/* Alter PHY configurations if data rate less than 1.5GHZ*/
less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
- if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) {
+ if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
@@ -1129,7 +1132,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
- .type = MSM_DSI_PHY_7NM_V4_1,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
@@ -1152,10 +1154,10 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
},
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_V4_1,
};
const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
- .type = MSM_DSI_PHY_7NM,
.src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 09/25] drm/msm/dsi: move min/max PLL rate to phy config
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (6 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 08/25] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 10/25] drm/msm/dsi: remove msm_dsi_pll_set_usecase Dmitry Baryshkov
` (16 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 ++++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 ++++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 8 ++++++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 ++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 8 ++++----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 ---
8 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 39abb86446f9..000e4207dabc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg {
struct msm_dsi_phy_ops ops;
const struct msm_dsi_pll_ops pll_ops;
+ unsigned long min_pll_rate;
+ unsigned long max_pll_rate;
+
/*
* Each cell {phy_id, pll_id} of the truth table indicates
* if the source PLL selection bit should be set for each PHY.
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index dc8ccc994759..5f9d0cfc4e03 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_10nm->postdiv_lock);
pll = &pll_10nm->base;
- pll->min_rate = 1000000000UL;
- pll->max_rate = 3500000000UL;
pll->cfg = phy->cfg;
pll_10nm->vco_delay = 1;
@@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
+ .min_pll_rate = 1000000000UL,
+ .max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
};
@@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
+ .min_pll_rate = 1000000000UL,
+ .max_pll_rate = 3500000000UL,
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index d78f846cf8e4..8e4528301e5d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1078,8 +1078,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_14nm->postdiv_lock);
pll = &pll_14nm->base;
- pll->min_rate = VCO_MIN_RATE;
- pll->max_rate = VCO_MAX_RATE;
pll->cfg = phy->cfg;
pll_14nm->vco_delay = 1;
@@ -1237,6 +1235,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2,
};
@@ -1264,6 +1264,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0xc994400, 0xc996000 },
.num_dsi_phy = 2,
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index bb33261d606d..d267b25e5da0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -625,8 +625,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
}
pll = &pll_28nm->base;
- pll->min_rate = VCO_MIN_RATE;
- pll->max_rate = VCO_MAX_RATE;
if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
pll_28nm->vco_delay = 1000;
else
@@ -811,6 +809,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2,
};
@@ -837,6 +837,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
};
@@ -863,6 +865,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_lp,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 79b0842a8dc4..31e7910c6050 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -508,8 +508,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
}
pll = &pll_28nm->base;
- pll->min_rate = VCO_MIN_RATE;
- pll->max_rate = VCO_MAX_RATE;
pll->cfg = phy->cfg;
@@ -711,6 +709,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq,
},
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2,
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 44ae495e8fca..4831d6769da7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -889,14 +889,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_7nm->postdiv_lock);
pll = &pll_7nm->base;
- pll->min_rate = 1000000000UL;
- pll->max_rate = 3500000000UL;
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
- pll->min_rate = 600000000UL;
- pll->max_rate = (unsigned long)5000000000ULL;
- /* workaround for max rate overflowing on 32-bit builds: */
- pll->max_rate = max(pll->max_rate, 0xffffffffUL);
- }
pll->cfg = phy->cfg;
pll_7nm->vco_delay = 1;
@@ -1152,6 +1144,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.restore_state = dsi_pll_7nm_restore_state,
.set_usecase = dsi_pll_7nm_set_usecase,
},
+ .min_pll_rate = 600000000UL,
+ .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V4_1,
@@ -1178,6 +1172,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.restore_state = dsi_pll_7nm_restore_state,
.set_usecase = dsi_pll_7nm_set_usecase,
},
+ .min_pll_rate = 1000000000UL,
+ .max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index c7ff0eba0e8b..e607adffe001 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -14,10 +14,10 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- if (rate < pll->min_rate)
- return pll->min_rate;
- else if (rate > pll->max_rate)
- return pll->max_rate;
+ if (rate < pll->cfg->min_pll_rate)
+ return pll->cfg->min_pll_rate;
+ else if (rate > pll->cfg->max_pll_rate)
+ return pll->cfg->max_pll_rate;
else
return rate;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index 4fa73fbcba52..8306911f8318 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -18,9 +18,6 @@ struct msm_dsi_pll {
bool pll_on;
bool state_saved;
- unsigned long min_rate;
- unsigned long max_rate;
-
const struct msm_dsi_phy_cfg *cfg;
};
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 10/25] drm/msm/dsi: remove msm_dsi_pll_set_usecase
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (7 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 09/25] drm/msm/dsi: move min/max PLL rate to phy config Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov
` (15 subsequent siblings)
24 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
msm_dsi_pll_set_usecase() function is not used outside of individual DSI
PHY drivers, so drop it in favour of calling the the respective
set_usecase functions directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 7 -------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 4 +---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 +---
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 9 ---------
6 files changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 98a4b296fa30..b310cf344ed4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -100,8 +100,6 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
-int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc);
#else
static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
@@ -118,11 +116,6 @@ static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
{
return 0;
}
-static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc)
-{
- return -ENODEV;
-}
#endif
/* dsi host */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 000e4207dabc..f737bef74b91 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -29,8 +29,6 @@ struct msm_dsi_pll_ops {
void (*destroy)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
- int (*set_usecase)(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc);
};
struct msm_dsi_phy_cfg {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 5f9d0cfc4e03..7a98e420414f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -1049,7 +1049,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
/* Select full-rate mode */
dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
- ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
@@ -1109,7 +1109,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
- .set_usecase = dsi_pll_10nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
@@ -1136,7 +1135,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
- .set_usecase = dsi_pll_10nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 8e4528301e5d..bab86fa6dc4b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1190,7 +1190,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
- ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
@@ -1231,7 +1231,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .set_usecase = dsi_pll_14nm_set_usecase,
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
@@ -1260,7 +1259,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .set_usecase = dsi_pll_14nm_set_usecase,
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 4831d6769da7..5acdfe1f63be 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1064,7 +1064,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
/* Select full-rate mode */
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
- ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
@@ -1142,7 +1142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
- .set_usecase = dsi_pll_7nm_set_usecase,
},
.min_pll_rate = 600000000UL,
.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
@@ -1170,7 +1169,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
- .set_usecase = dsi_pll_7nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index e607adffe001..98ee4560581a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -113,12 +113,3 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-
-int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc)
-{
- if (pll->cfg->pll_ops.set_usecase)
- return pll->cfg->pll_ops.set_usecase(pll, uc);
-
- return 0;
-}
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (8 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 10/25] drm/msm/dsi: remove msm_dsi_pll_set_usecase Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-29 22:12 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
` (14 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
All MSM DSI PHYs provide two clocks: byte and pixel ones.
Register/unregister provided clocks from the generic place, removing
boilerplate code from all MSM DSI PHY drivers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 11 +---
drivers/gpu/drm/msm/dsi/dsi_host.c | 4 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 13 +---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 34 ++++++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 9 ++-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 55 ++--------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 53 ++--------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 63 +++----------------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 57 +++--------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 55 ++--------------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 16 +----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 +-
12 files changed, 78 insertions(+), 295 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index b310cf344ed4..43590f338d20 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -96,19 +96,12 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
struct msm_dsi_pll;
#ifdef CONFIG_DRM_MSM_DSI_PLL
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
-int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
#else
static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
}
-static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
-{
- return -ENODEV;
-}
static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
{
}
@@ -144,7 +137,7 @@ struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer);
void msm_dsi_host_unregister(struct mipi_dsi_host *host);
int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
- struct msm_dsi_pll *src_pll);
+ struct msm_dsi_phy *src_phy);
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
struct msm_dsi_phy_clk_request *clk_req,
@@ -196,6 +189,8 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
+int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
+ struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
#endif /* __DSI_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index ab281cba0f08..41e1d0f7ab6e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2226,13 +2226,13 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
}
int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
- struct msm_dsi_pll *src_pll)
+ struct msm_dsi_phy *src_phy)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
struct clk *byte_clk_provider, *pixel_clk_provider;
int ret;
- ret = msm_dsi_pll_get_clk_provider(src_pll,
+ ret = msm_dsi_phy_get_clk_provider(src_phy,
&byte_clk_provider, &pixel_clk_provider);
if (ret) {
pr_info("%s: can't get provider from pll, don't set parent\n",
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 1d28dfba2c9b..86e36be58701 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -70,7 +70,6 @@ static int dsi_mgr_setup_components(int id)
struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
- struct msm_dsi_pll *src_pll;
int ret;
if (!IS_DUAL_DSI()) {
@@ -79,10 +78,7 @@ static int dsi_mgr_setup_components(int id)
return ret;
msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
- src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
- if (IS_ERR(src_pll))
- return PTR_ERR(src_pll);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
+ ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
} else if (!other_dsi) {
ret = 0;
} else {
@@ -109,13 +105,10 @@ static int dsi_mgr_setup_components(int id)
MSM_DSI_PHY_MASTER);
msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
MSM_DSI_PHY_SLAVE);
- src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy);
- if (IS_ERR(src_pll))
- return PTR_ERR(src_pll);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
+ ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy);
if (ret)
return ret;
- ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll);
+ ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy);
}
return ret;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 5f153b683521..69214447f757 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -3,6 +3,7 @@
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
+#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "dsi_phy.h"
@@ -652,6 +653,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
if (!match)
return -ENODEV;
+ phy->provided_clocks = devm_kzalloc(dev,
+ struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
+ GFP_KERNEL);
+ if (!phy->provided_clocks)
+ return -ENOMEM;
+
+ phy->provided_clocks->num = NUM_PROVIDED_CLKS;
+
phy->cfg = match->data;
phy->pdev = pdev;
@@ -719,6 +728,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
}
}
+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ phy->provided_clocks);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret);
+ goto fail;
+ }
+
dsi_phy_disable_resource(phy);
platform_set_drvdata(pdev, phy);
@@ -726,6 +742,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
return 0;
fail:
+ if (phy->pll) {
+ of_clk_del_provider(dev->of_node);
+ msm_dsi_pll_destroy(phy->pll);
+ phy->pll = NULL;
+ }
+
return ret;
}
@@ -734,6 +756,7 @@ static int dsi_phy_driver_remove(struct platform_device *pdev)
struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
if (phy && phy->pll) {
+ of_clk_del_provider(pdev->dev.of_node);
msm_dsi_pll_destroy(phy->pll);
phy->pll = NULL;
}
@@ -851,3 +874,14 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
if (phy)
phy->usecase = uc;
}
+
+int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
+ struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
+{
+ if (byte_clk_provider)
+ *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
+ if (pixel_clk_provider)
+ *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
+
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f737bef74b91..c3099629fa3b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -23,9 +23,6 @@ struct msm_dsi_phy_ops {
struct msm_dsi_pll_ops {
int (*enable_seq)(struct msm_dsi_pll *pll);
void (*disable_seq)(struct msm_dsi_pll *pll);
- int (*get_provider)(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider);
void (*destroy)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
@@ -87,6 +84,10 @@ struct msm_dsi_dphy_timing {
u8 hs_halfbyte_en_ckln;
};
+#define DSI_BYTE_PLL_CLK 0
+#define DSI_PIXEL_PLL_CLK 1
+#define NUM_PROVIDED_CLKS 2
+
struct msm_dsi_phy {
struct platform_device *pdev;
void __iomem *base;
@@ -104,6 +105,8 @@ struct msm_dsi_phy {
bool regulator_ldo_mode;
struct msm_dsi_pll *pll;
+
+ struct clk_hw_onecell_data *provided_clocks;
};
/*
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 7a98e420414f..8666da1c29e5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -36,10 +36,6 @@
* dsi0_pll_post_out_div_clk
*/
-#define DSI_BYTE_PLL_CLK 0
-#define DSI_PIXEL_PLL_CLK 1
-#define NUM_PROVIDED_CLKS 2
-
#define VCO_REF_CLK_RATE 19200000
struct dsi_pll_regs {
@@ -116,9 +112,6 @@ struct dsi_pll_10nm {
struct clk_hw *pclk_mux_hw;
struct clk_hw *out_dsiclk_hw;
- /* clock-provider: */
- struct clk_hw_onecell_data *hw_data;
-
struct pll_10nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -621,30 +614,11 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
- struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data;
-
- DBG("DSI PLL%d", pll_10nm->id);
-
- if (byte_clk_provider)
- *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
- if (pixel_clk_provider)
- *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
-
- return 0;
-}
-
static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
- struct device *dev = &pll_10nm->pdev->dev;
DBG("DSI PLL%d", pll_10nm->id);
- of_clk_del_provider(dev->of_node);
clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
@@ -662,7 +636,7 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
* state to follow the master PLL's divider/mux state. Therefore, we don't
* require special clock ops that also configure the slave PLL registers
*/
-static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
+static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
@@ -674,18 +648,11 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
.ops = &clk_ops_dsi_pll_10nm_vco,
};
struct device *dev = &pll_10nm->pdev->dev;
- struct clk_hw_onecell_data *hw_data;
struct clk_hw *hw;
int ret;
DBG("DSI%d", pll_10nm->id);
- hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
- NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
- GFP_KERNEL);
- if (!hw_data)
- return -ENOMEM;
-
snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
pll_10nm->base.clk_hw.init = &vco_init;
@@ -737,7 +704,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
}
pll_10nm->byte_clk_hw = hw;
- hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
+ provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
@@ -797,22 +764,10 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
}
pll_10nm->out_dsiclk_hw = hw;
- hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
-
- hw_data->num = NUM_PROVIDED_CLKS;
- pll_10nm->hw_data = hw_data;
-
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
- pll_10nm->hw_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
- goto err_dsiclk_hw;
- }
+ provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
-err_dsiclk_hw:
- clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
err_pclk_mux_hw:
clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
err_post_out_div_clk_hw:
@@ -868,7 +823,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
pll_10nm->vco_delay = 1;
- ret = pll_10nm_register(pll_10nm);
+ ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -1105,7 +1060,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_10nm_get_provider,
.destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
@@ -1131,7 +1085,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_10nm_get_provider,
.destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index bab86fa6dc4b..07ecdf34f614 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -34,15 +34,10 @@
#define POLL_MAX_READS 15
#define POLL_TIMEOUT_US 1000
-#define NUM_PROVIDED_CLKS 2
-
#define VCO_REF_CLK_RATE 19200000
#define VCO_MIN_RATE 1300000000UL
#define VCO_MAX_RATE 2600000000UL
-#define DSI_BYTE_PLL_CLK 0
-#define DSI_PIXEL_PLL_CLK 1
-
#define DSI_PLL_DEFAULT_VCO_POSTDIV 1
struct dsi_pll_input {
@@ -142,9 +137,6 @@ struct dsi_pll_14nm {
struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
u32 num_hws;
- /* clock-provider: */
- struct clk_hw_onecell_data *hw_data;
-
struct pll_14nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -880,29 +872,11 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
-
- if (byte_clk_provider)
- *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
- if (pixel_clk_provider)
- *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
-
- return 0;
-}
-
static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- struct platform_device *pdev = pll_14nm->pdev;
int num_hws = pll_14nm->num_hws;
- of_clk_del_provider(pdev->dev.of_node);
-
while (num_hws--)
clk_hw_unregister(pll_14nm->hws[num_hws]);
}
@@ -943,7 +917,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
return &pll_postdiv->hw;
}
-static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
+static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
{
char clk_name[32], parent[32], vco_name[32];
struct clk_init_data vco_init = {
@@ -955,19 +929,12 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
};
struct device *dev = &pll_14nm->pdev->dev;
struct clk_hw **hws = pll_14nm->hws;
- struct clk_hw_onecell_data *hw_data;
struct clk_hw *hw;
int num = 0;
int ret;
DBG("DSI%d", pll_14nm->id);
- hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
- NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
- GFP_KERNEL);
- if (!hw_data)
- return -ENOMEM;
-
snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
pll_14nm->base.clk_hw.init = &vco_init;
@@ -998,7 +965,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
return PTR_ERR(hw);
hws[num++] = hw;
- hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
+ provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
@@ -1025,20 +992,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
return PTR_ERR(hw);
hws[num++] = hw;
- hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
+ provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
pll_14nm->num_hws = num;
- hw_data->num = NUM_PROVIDED_CLKS;
- pll_14nm->hw_data = hw_data;
-
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
- pll_14nm->hw_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
- return ret;
- }
-
return 0;
}
@@ -1082,7 +1039,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
pll_14nm->vco_delay = 1;
- ret = pll_14nm_register(pll_14nm);
+ ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -1227,7 +1184,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.pll_init = dsi_pll_14nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_14nm_get_provider,
.destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
@@ -1255,7 +1211,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.pll_init = dsi_pll_14nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_14nm_get_provider,
.destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index d267b25e5da0..3446be318648 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -31,15 +31,10 @@
#define POLL_MAX_READS 10
#define POLL_TIMEOUT_US 50
-#define NUM_PROVIDED_CLKS 2
-
#define VCO_REF_CLK_RATE 19200000
#define VCO_MIN_RATE 350000000
#define VCO_MAX_RATE 750000000
-#define DSI_BYTE_PLL_CLK 0
-#define DSI_PIXEL_PLL_CLK 1
-
/* v2.0.0 28nm LP implementation */
#define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
@@ -83,10 +78,6 @@ struct dsi_pll_28nm {
struct clk *clks[NUM_DSI_CLOCKS_MAX];
u32 num_clks;
- /* clock-provider: */
- struct clk *provided_clks[NUM_PROVIDED_CLKS];
- struct clk_onecell_data clk_data;
-
struct pll_28nm_cached_state cached_state;
};
@@ -495,38 +486,16 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- if (byte_clk_provider)
- *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
- if (pixel_clk_provider)
- *pixel_clk_provider =
- pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
-
- return 0;
-}
-
static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
- int i;
-
- msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
- pll_28nm->clks, pll_28nm->num_clks);
- for (i = 0; i < NUM_PROVIDED_CLKS; i++)
- pll_28nm->provided_clks[i] = NULL;
+ msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
pll_28nm->num_clks = 0;
- pll_28nm->clk_data.clks = NULL;
- pll_28nm->clk_data.clk_num = 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
@@ -538,9 +507,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
};
struct device *dev = &pll_28nm->pdev->dev;
struct clk **clks = pll_28nm->clks;
- struct clk **provided_clks = pll_28nm->provided_clks;
int num = 0;
- int ret;
DBG("%d", pll_28nm->id);
@@ -564,11 +531,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
- clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
- clk_register_divider(dev, clk_name,
+ clks[num++] = clk_register_divider(dev, clk_name,
parent1, 0, pll_28nm->mmio +
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
0, 8, 0, NULL);
+ provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
@@ -581,22 +548,12 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
- clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
- clk_register_fixed_factor(dev, clk_name,
+ clks[num++] = clk_register_fixed_factor(dev, clk_name,
parent1, CLK_SET_RATE_PARENT, 1, 4);
+ provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
pll_28nm->num_clks = num;
- pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
- pll_28nm->clk_data.clks = provided_clks;
-
- ret = of_clk_add_provider(dev->of_node,
- of_clk_src_onecell_get, &pll_28nm->clk_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
- return ret;
- }
-
return 0;
}
@@ -625,14 +582,13 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
}
pll = &pll_28nm->base;
+ pll->cfg = phy->cfg;
if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
pll_28nm->vco_delay = 1000;
else
pll_28nm->vco_delay = 1;
- pll->cfg = phy->cfg;
-
- ret = pll_28nm_register(pll_28nm);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -802,7 +758,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_28nm_get_provider,
.destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
@@ -830,7 +785,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_28nm_get_provider,
.destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
@@ -858,7 +812,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_28nm_get_provider,
.destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 31e7910c6050..c4b433790cfb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -39,15 +39,10 @@
#define POLL_MAX_READS 8000
#define POLL_TIMEOUT_US 1
-#define NUM_PROVIDED_CLKS 2
-
#define VCO_REF_CLK_RATE 27000000
#define VCO_MIN_RATE 600000000
#define VCO_MAX_RATE 1200000000
-#define DSI_BYTE_PLL_CLK 0
-#define DSI_PIXEL_PLL_CLK 1
-
#define VCO_PREF_DIV_RATIO 27
struct pll_28nm_cached_state {
@@ -76,10 +71,6 @@ struct dsi_pll_28nm {
struct clk *clks[NUM_DSI_CLOCKS_MAX];
u32 num_clks;
- /* clock-provider: */
- struct clk *provided_clks[NUM_PROVIDED_CLKS];
- struct clk_onecell_data clk_data;
-
struct pll_28nm_cached_state cached_state;
};
@@ -377,30 +368,14 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- if (byte_clk_provider)
- *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
- if (pixel_clk_provider)
- *pixel_clk_provider =
- pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
-
- return 0;
-}
-
static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
- msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
- pll_28nm->clks, pll_28nm->num_clks);
+ msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
{
char *clk_name, *parent_name, *vco_name;
struct clk_init_data vco_init = {
@@ -411,10 +386,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
};
struct device *dev = &pll_28nm->pdev->dev;
struct clk **clks = pll_28nm->clks;
- struct clk **provided_clks = pll_28nm->provided_clks;
struct clk_bytediv *bytediv;
struct clk_init_data bytediv_init = { };
- int ret, num = 0;
+ int num = 0;
DBG("%d", pll_28nm->id);
@@ -426,10 +400,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
if (!vco_name)
return -ENOMEM;
- parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
- if (!parent_name)
- return -ENOMEM;
-
clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
if (!clk_name)
return -ENOMEM;
@@ -457,29 +427,19 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
bytediv_init.num_parents = 1;
/* DIV2 */
- clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
- clk_register(dev, &bytediv->hw);
+ clks[num++] = clk_register(dev, &bytediv->hw);
+ provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
/* DIV3 */
- clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
- clk_register_divider(dev, clk_name,
+ clks[num++] = clk_register_divider(dev, clk_name,
parent_name, 0, pll_28nm->mmio +
REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
0, 8, 0, NULL);
+ provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
pll_28nm->num_clks = num;
- pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
- pll_28nm->clk_data.clks = provided_clks;
-
- ret = of_clk_add_provider(dev->of_node,
- of_clk_src_onecell_get, &pll_28nm->clk_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
- return ret;
- }
-
return 0;
}
@@ -511,7 +471,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
pll->cfg = phy->cfg;
- ret = pll_28nm_register(pll_28nm);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -702,7 +662,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.pll_init = dsi_pll_28nm_8960_init,
},
.pll_ops = {
- .get_provider = dsi_pll_28nm_get_provider,
.destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 5acdfe1f63be..0b601afa9e49 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -36,10 +36,6 @@
* dsi0_pll_post_out_div_clk
*/
-#define DSI_BYTE_PLL_CLK 0
-#define DSI_PIXEL_PLL_CLK 1
-#define NUM_PROVIDED_CLKS 2
-
#define VCO_REF_CLK_RATE 19200000
struct dsi_pll_regs {
@@ -116,9 +112,6 @@ struct dsi_pll_7nm {
struct clk_hw *pclk_mux_hw;
struct clk_hw *out_dsiclk_hw;
- /* clock-provider: */
- struct clk_hw_onecell_data *hw_data;
-
struct pll_7nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -646,30 +639,11 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
- struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data;
-
- DBG("DSI PLL%d", pll_7nm->id);
-
- if (byte_clk_provider)
- *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
- if (pixel_clk_provider)
- *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
-
- return 0;
-}
-
static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
- struct device *dev = &pll_7nm->pdev->dev;
DBG("DSI PLL%d", pll_7nm->id);
- of_clk_del_provider(dev->of_node);
clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
@@ -687,7 +661,7 @@ static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
* state to follow the master PLL's divider/mux state. Therefore, we don't
* require special clock ops that also configure the slave PLL registers
*/
-static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
+static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
@@ -699,18 +673,11 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
.ops = &clk_ops_dsi_pll_7nm_vco,
};
struct device *dev = &pll_7nm->pdev->dev;
- struct clk_hw_onecell_data *hw_data;
struct clk_hw *hw;
int ret;
DBG("DSI%d", pll_7nm->id);
- hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
- NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
- GFP_KERNEL);
- if (!hw_data)
- return -ENOMEM;
-
snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
pll_7nm->base.clk_hw.init = &vco_init;
@@ -762,7 +729,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
}
pll_7nm->byte_clk_hw = hw;
- hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
+ provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
@@ -822,22 +789,10 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
}
pll_7nm->out_dsiclk_hw = hw;
- hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
-
- hw_data->num = NUM_PROVIDED_CLKS;
- pll_7nm->hw_data = hw_data;
-
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
- pll_7nm->hw_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
- goto err_dsiclk_hw;
- }
+ provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
-err_dsiclk_hw:
- clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
err_pclk_mux_hw:
clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
err_post_out_div_clk_hw:
@@ -893,7 +848,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
pll_7nm->vco_delay = 1;
- ret = pll_7nm_register(pll_7nm);
+ ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -1138,7 +1093,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.pll_init = dsi_pll_7nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_7nm_get_provider,
.destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
@@ -1165,7 +1119,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.pll_init = dsi_pll_7nm_init,
},
.pll_ops = {
- .get_provider = dsi_pll_7nm_get_provider,
.destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 98ee4560581a..914e95435dcb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -57,11 +57,8 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
pll->pll_on = false;
}
-void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
- struct clk **clks, u32 num_clks)
+void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks)
{
- of_clk_del_provider(pdev->dev.of_node);
-
if (!num_clks || !clks)
return;
@@ -74,17 +71,6 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
/*
* DSI PLL API
*/
-int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
-{
- if (pll->cfg->pll_ops.get_provider)
- return pll->cfg->pll_ops.get_provider(pll,
- byte_clk_provider,
- pixel_clk_provider);
-
- return -EINVAL;
-}
-
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
if (pll->cfg->pll_ops.destroy)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index 8306911f8318..d819a886beb8 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -55,8 +55,7 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
/* misc */
-void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
- struct clk **clks, u32 num_clks);
+void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks);
#endif /* __DSI_PLL_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code
2021-03-27 11:02 ` [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov
@ 2021-03-29 22:12 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-29 22:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> All MSM DSI PHYs provide two clocks: byte and pixel ones.
> Register/unregister provided clocks from the generic place, removing
> boilerplate code from all MSM DSI PHY drivers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 11 +---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 4 +-
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 13 +---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 34 ++++++++++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 9 ++-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 55 ++--------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 53 ++--------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 63 +++----------------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 57 +++--------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 55 ++--------------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 16 +----
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 +-
> 12 files changed, 78 insertions(+), 295 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
> b/drivers/gpu/drm/msm/dsi/dsi.h
> index b310cf344ed4..43590f338d20 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -96,19 +96,12 @@ struct drm_encoder *msm_dsi_get_encoder(struct
> msm_dsi *msm_dsi);
> struct msm_dsi_pll;
> #ifdef CONFIG_DRM_MSM_DSI_PLL
> void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
> -int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
> void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
> int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
> #else
> static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
> {
> }
> -static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll
> *pll,
> - struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
> -{
> - return -ENODEV;
> -}
> static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
> {
> }
> @@ -144,7 +137,7 @@ struct drm_bridge *msm_dsi_host_get_bridge(struct
> mipi_dsi_host *host);
> int msm_dsi_host_register(struct mipi_dsi_host *host, bool
> check_defer);
> void msm_dsi_host_unregister(struct mipi_dsi_host *host);
> int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
> - struct msm_dsi_pll *src_pll);
> + struct msm_dsi_phy *src_phy);
> void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
> void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
> struct msm_dsi_phy_clk_request *clk_req,
> @@ -196,6 +189,8 @@ void msm_dsi_phy_get_shared_timings(struct
> msm_dsi_phy *phy,
> struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
> void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
> enum msm_dsi_phy_usecase uc);
> +int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
> + struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
>
> #endif /* __DSI_CONNECTOR_H__ */
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index ab281cba0f08..41e1d0f7ab6e 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2226,13 +2226,13 @@ void msm_dsi_host_cmd_xfer_commit(struct
> mipi_dsi_host *host, u32 dma_base,
> }
>
> int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
> - struct msm_dsi_pll *src_pll)
> + struct msm_dsi_phy *src_phy)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> struct clk *byte_clk_provider, *pixel_clk_provider;
> int ret;
>
> - ret = msm_dsi_pll_get_clk_provider(src_pll,
> + ret = msm_dsi_phy_get_clk_provider(src_phy,
> &byte_clk_provider, &pixel_clk_provider);
> if (ret) {
> pr_info("%s: can't get provider from pll, don't set parent\n",
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 1d28dfba2c9b..86e36be58701 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -70,7 +70,6 @@ static int dsi_mgr_setup_components(int id)
> struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
> struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
> struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
> - struct msm_dsi_pll *src_pll;
> int ret;
>
> if (!IS_DUAL_DSI()) {
> @@ -79,10 +78,7 @@ static int dsi_mgr_setup_components(int id)
> return ret;
>
> msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
> - src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
> - if (IS_ERR(src_pll))
> - return PTR_ERR(src_pll);
> - ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
> + ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
> } else if (!other_dsi) {
> ret = 0;
> } else {
> @@ -109,13 +105,10 @@ static int dsi_mgr_setup_components(int id)
> MSM_DSI_PHY_MASTER);
> msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
> MSM_DSI_PHY_SLAVE);
> - src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy);
> - if (IS_ERR(src_pll))
> - return PTR_ERR(src_pll);
> - ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
> + ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy);
> if (ret)
> return ret;
> - ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll);
> + ret = msm_dsi_host_set_src_pll(other_dsi->host,
> clk_master_dsi->phy);
> }
>
> return ret;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 5f153b683521..69214447f757 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -3,6 +3,7 @@
> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> */
>
> +#include <linux/clk-provider.h>
> #include <linux/platform_device.h>
>
> #include "dsi_phy.h"
> @@ -652,6 +653,14 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> if (!match)
> return -ENODEV;
>
> + phy->provided_clocks = devm_kzalloc(dev,
> + struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
> + GFP_KERNEL);
> + if (!phy->provided_clocks)
> + return -ENOMEM;
> +
> + phy->provided_clocks->num = NUM_PROVIDED_CLKS;
> +
> phy->cfg = match->data;
> phy->pdev = pdev;
>
> @@ -719,6 +728,13 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> }
> }
>
> + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> + phy->provided_clocks);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n",
> __func__, ret);
> + goto fail;
> + }
> +
> dsi_phy_disable_resource(phy);
>
> platform_set_drvdata(pdev, phy);
> @@ -726,6 +742,12 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> return 0;
>
> fail:
> + if (phy->pll) {
> + of_clk_del_provider(dev->of_node);
> + msm_dsi_pll_destroy(phy->pll);
> + phy->pll = NULL;
> + }
> +
> return ret;
> }
>
> @@ -734,6 +756,7 @@ static int dsi_phy_driver_remove(struct
> platform_device *pdev)
> struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
>
> if (phy && phy->pll) {
> + of_clk_del_provider(pdev->dev.of_node);
> msm_dsi_pll_destroy(phy->pll);
> phy->pll = NULL;
> }
> @@ -851,3 +874,14 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy
> *phy,
> if (phy)
> phy->usecase = uc;
> }
> +
> +int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
> + struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
> +{
> + if (byte_clk_provider)
> + *byte_clk_provider =
> phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
> + if (pixel_clk_provider)
> + *pixel_clk_provider =
> phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
> +
> + return -EINVAL;
> +}
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index f737bef74b91..c3099629fa3b 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -23,9 +23,6 @@ struct msm_dsi_phy_ops {
> struct msm_dsi_pll_ops {
> int (*enable_seq)(struct msm_dsi_pll *pll);
> void (*disable_seq)(struct msm_dsi_pll *pll);
> - int (*get_provider)(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider);
> void (*destroy)(struct msm_dsi_pll *pll);
> void (*save_state)(struct msm_dsi_pll *pll);
> int (*restore_state)(struct msm_dsi_pll *pll);
> @@ -87,6 +84,10 @@ struct msm_dsi_dphy_timing {
> u8 hs_halfbyte_en_ckln;
> };
>
> +#define DSI_BYTE_PLL_CLK 0
> +#define DSI_PIXEL_PLL_CLK 1
> +#define NUM_PROVIDED_CLKS 2
> +
> struct msm_dsi_phy {
> struct platform_device *pdev;
> void __iomem *base;
> @@ -104,6 +105,8 @@ struct msm_dsi_phy {
> bool regulator_ldo_mode;
>
> struct msm_dsi_pll *pll;
> +
> + struct clk_hw_onecell_data *provided_clocks;
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 7a98e420414f..8666da1c29e5 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -36,10 +36,6 @@
> *
> dsi0_pll_post_out_div_clk
> */
>
> -#define DSI_BYTE_PLL_CLK 0
> -#define DSI_PIXEL_PLL_CLK 1
> -#define NUM_PROVIDED_CLKS 2
> -
> #define VCO_REF_CLK_RATE 19200000
>
> struct dsi_pll_regs {
> @@ -116,9 +112,6 @@ struct dsi_pll_10nm {
> struct clk_hw *pclk_mux_hw;
> struct clk_hw *out_dsiclk_hw;
>
> - /* clock-provider: */
> - struct clk_hw_onecell_data *hw_data;
> -
> struct pll_10nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -621,30 +614,11 @@ static int dsi_pll_10nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider)
> -{
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> - struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data;
> -
> - DBG("DSI PLL%d", pll_10nm->id);
> -
> - if (byte_clk_provider)
> - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
> - if (pixel_clk_provider)
> - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
> -
> - return 0;
> -}
> -
> static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> - struct device *dev = &pll_10nm->pdev->dev;
>
> DBG("DSI PLL%d", pll_10nm->id);
> - of_clk_del_provider(dev->of_node);
>
> clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
> clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
> @@ -662,7 +636,7 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll
> *pll)
> * state to follow the master PLL's divider/mux state. Therefore, we
> don't
> * require special clock ops that also configure the slave PLL
> registers
> */
> -static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
> +static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct
> clk_hw **provided_clocks)
> {
> char clk_name[32], parent[32], vco_name[32];
> char parent2[32], parent3[32], parent4[32];
> @@ -674,18 +648,11 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm)
> .ops = &clk_ops_dsi_pll_10nm_vco,
> };
> struct device *dev = &pll_10nm->pdev->dev;
> - struct clk_hw_onecell_data *hw_data;
> struct clk_hw *hw;
> int ret;
>
> DBG("DSI%d", pll_10nm->id);
>
> - hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
> - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
> - GFP_KERNEL);
> - if (!hw_data)
> - return -ENOMEM;
> -
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
> pll_10nm->base.clk_hw.init = &vco_init;
>
> @@ -737,7 +704,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm)
> }
>
> pll_10nm->byte_clk_hw = hw;
> - hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
> + provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> @@ -797,22 +764,10 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm)
> }
>
> pll_10nm->out_dsiclk_hw = hw;
> - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
> -
> - hw_data->num = NUM_PROVIDED_CLKS;
> - pll_10nm->hw_data = hw_data;
> -
> - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> - pll_10nm->hw_data);
> - if (ret) {
> - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
> - goto err_dsiclk_hw;
> - }
> + provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> return 0;
>
> -err_dsiclk_hw:
> - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
> err_pclk_mux_hw:
> clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
> err_post_out_div_clk_hw:
> @@ -868,7 +823,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
>
> pll_10nm->vco_delay = 1;
>
> - ret = pll_10nm_register(pll_10nm);
> + ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> return ret;
> @@ -1105,7 +1060,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =
> {
> .pll_init = dsi_pll_10nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_10nm_get_provider,
> .destroy = dsi_pll_10nm_destroy,
> .save_state = dsi_pll_10nm_save_state,
> .restore_state = dsi_pll_10nm_restore_state,
> @@ -1131,7 +1085,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_10nm_8998_cfgs = {
> .pll_init = dsi_pll_10nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_10nm_get_provider,
> .destroy = dsi_pll_10nm_destroy,
> .save_state = dsi_pll_10nm_save_state,
> .restore_state = dsi_pll_10nm_restore_state,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index bab86fa6dc4b..07ecdf34f614 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -34,15 +34,10 @@
> #define POLL_MAX_READS 15
> #define POLL_TIMEOUT_US 1000
>
> -#define NUM_PROVIDED_CLKS 2
> -
> #define VCO_REF_CLK_RATE 19200000
> #define VCO_MIN_RATE 1300000000UL
> #define VCO_MAX_RATE 2600000000UL
>
> -#define DSI_BYTE_PLL_CLK 0
> -#define DSI_PIXEL_PLL_CLK 1
> -
> #define DSI_PLL_DEFAULT_VCO_POSTDIV 1
>
> struct dsi_pll_input {
> @@ -142,9 +137,6 @@ struct dsi_pll_14nm {
> struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
> u32 num_hws;
>
> - /* clock-provider: */
> - struct clk_hw_onecell_data *hw_data;
> -
> struct pll_14nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -880,29 +872,11 @@ static int dsi_pll_14nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider)
> -{
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> - struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
> -
> - if (byte_clk_provider)
> - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
> - if (pixel_clk_provider)
> - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
> -
> - return 0;
> -}
> -
> static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> - struct platform_device *pdev = pll_14nm->pdev;
> int num_hws = pll_14nm->num_hws;
>
> - of_clk_del_provider(pdev->dev.of_node);
> -
> while (num_hws--)
> clk_hw_unregister(pll_14nm->hws[num_hws]);
> }
> @@ -943,7 +917,7 @@ static struct clk_hw
> *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
> return &pll_postdiv->hw;
> }
>
> -static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
> +static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct
> clk_hw **provided_clocks)
> {
> char clk_name[32], parent[32], vco_name[32];
> struct clk_init_data vco_init = {
> @@ -955,19 +929,12 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm)
> };
> struct device *dev = &pll_14nm->pdev->dev;
> struct clk_hw **hws = pll_14nm->hws;
> - struct clk_hw_onecell_data *hw_data;
> struct clk_hw *hw;
> int num = 0;
> int ret;
>
> DBG("DSI%d", pll_14nm->id);
>
> - hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
> - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
> - GFP_KERNEL);
> - if (!hw_data)
> - return -ENOMEM;
> -
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
> pll_14nm->base.clk_hw.init = &vco_init;
>
> @@ -998,7 +965,7 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm)
> return PTR_ERR(hw);
>
> hws[num++] = hw;
> - hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
> + provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
> snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
> @@ -1025,20 +992,10 @@ static int pll_14nm_register(struct
> dsi_pll_14nm *pll_14nm)
> return PTR_ERR(hw);
>
> hws[num++] = hw;
> - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
> + provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> pll_14nm->num_hws = num;
>
> - hw_data->num = NUM_PROVIDED_CLKS;
> - pll_14nm->hw_data = hw_data;
> -
> - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> - pll_14nm->hw_data);
> - if (ret) {
> - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
> - return ret;
> - }
> -
> return 0;
> }
>
> @@ -1082,7 +1039,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
>
> pll_14nm->vco_delay = 1;
>
> - ret = pll_14nm_register(pll_14nm);
> + ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> return ret;
> @@ -1227,7 +1184,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =
> {
> .pll_init = dsi_pll_14nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_14nm_get_provider,
> .destroy = dsi_pll_14nm_destroy,
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> @@ -1255,7 +1211,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_14nm_660_cfgs = {
> .pll_init = dsi_pll_14nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_14nm_get_provider,
> .destroy = dsi_pll_14nm_destroy,
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index d267b25e5da0..3446be318648 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -31,15 +31,10 @@
> #define POLL_MAX_READS 10
> #define POLL_TIMEOUT_US 50
>
> -#define NUM_PROVIDED_CLKS 2
> -
> #define VCO_REF_CLK_RATE 19200000
> #define VCO_MIN_RATE 350000000
> #define VCO_MAX_RATE 750000000
>
> -#define DSI_BYTE_PLL_CLK 0
> -#define DSI_PIXEL_PLL_CLK 1
> -
> /* v2.0.0 28nm LP implementation */
> #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
>
> @@ -83,10 +78,6 @@ struct dsi_pll_28nm {
> struct clk *clks[NUM_DSI_CLOCKS_MAX];
> u32 num_clks;
>
> - /* clock-provider: */
> - struct clk *provided_clks[NUM_PROVIDED_CLKS];
> - struct clk_onecell_data clk_data;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -495,38 +486,16 @@ static int dsi_pll_28nm_restore_state(struct
> msm_dsi_pll *pll)
> return 0;
> }
>
> -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> -
> - if (byte_clk_provider)
> - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
> - if (pixel_clk_provider)
> - *pixel_clk_provider =
> - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
> -
> - return 0;
> -}
> -
> static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> - int i;
> -
> - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
> - pll_28nm->clks, pll_28nm->num_clks);
>
> - for (i = 0; i < NUM_PROVIDED_CLKS; i++)
> - pll_28nm->provided_clks[i] = NULL;
> + msm_dsi_pll_helper_unregister_clks(pll_28nm->clks,
> pll_28nm->num_clks);
>
> pll_28nm->num_clks = 0;
> - pll_28nm->clk_data.clks = NULL;
> - pll_28nm->clk_data.clk_num = 0;
> }
>
> -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct
> clk_hw **provided_clocks)
> {
> char clk_name[32], parent1[32], parent2[32], vco_name[32];
> struct clk_init_data vco_init = {
> @@ -538,9 +507,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
> };
> struct device *dev = &pll_28nm->pdev->dev;
> struct clk **clks = pll_28nm->clks;
> - struct clk **provided_clks = pll_28nm->provided_clks;
> int num = 0;
> - int ret;
>
> DBG("%d", pll_28nm->id);
>
> @@ -564,11 +531,11 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
>
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
> - clk_register_divider(dev, clk_name,
> + clks[num++] = clk_register_divider(dev, clk_name,
> parent1, 0, pll_28nm->mmio +
> REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> 0, 8, 0, NULL);
> + provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
>
> snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> @@ -581,22 +548,12 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
>
> snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
> - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
> - clk_register_fixed_factor(dev, clk_name,
> + clks[num++] = clk_register_fixed_factor(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT, 1, 4);
> + provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
>
> pll_28nm->num_clks = num;
>
> - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
> - pll_28nm->clk_data.clks = provided_clks;
> -
> - ret = of_clk_add_provider(dev->of_node,
> - of_clk_src_onecell_get, &pll_28nm->clk_data);
> - if (ret) {
> - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
> - return ret;
> - }
> -
> return 0;
> }
>
> @@ -625,14 +582,13 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
> }
>
> pll = &pll_28nm->base;
> + pll->cfg = phy->cfg;
> if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> pll_28nm->vco_delay = 1000;
> else
> pll_28nm->vco_delay = 1;
>
> - pll->cfg = phy->cfg;
> -
> - ret = pll_28nm_register(pll_28nm);
> + ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> return ret;
> @@ -802,7 +758,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
> = {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_28nm_get_provider,
> .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> @@ -830,7 +785,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_hpm_famb_cfgs = {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_28nm_get_provider,
> .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> @@ -858,7 +812,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs =
> {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_28nm_get_provider,
> .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 31e7910c6050..c4b433790cfb 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -39,15 +39,10 @@
> #define POLL_MAX_READS 8000
> #define POLL_TIMEOUT_US 1
>
> -#define NUM_PROVIDED_CLKS 2
> -
> #define VCO_REF_CLK_RATE 27000000
> #define VCO_MIN_RATE 600000000
> #define VCO_MAX_RATE 1200000000
>
> -#define DSI_BYTE_PLL_CLK 0
> -#define DSI_PIXEL_PLL_CLK 1
> -
> #define VCO_PREF_DIV_RATIO 27
>
> struct pll_28nm_cached_state {
> @@ -76,10 +71,6 @@ struct dsi_pll_28nm {
> struct clk *clks[NUM_DSI_CLOCKS_MAX];
> u32 num_clks;
>
> - /* clock-provider: */
> - struct clk *provided_clks[NUM_PROVIDED_CLKS];
> - struct clk_onecell_data clk_data;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -377,30 +368,14 @@ static int dsi_pll_28nm_restore_state(struct
> msm_dsi_pll *pll)
> return 0;
> }
>
> -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> -
> - if (byte_clk_provider)
> - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
> - if (pixel_clk_provider)
> - *pixel_clk_provider =
> - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
> -
> - return 0;
> -}
> -
> static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>
> - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
> - pll_28nm->clks, pll_28nm->num_clks);
> + msm_dsi_pll_helper_unregister_clks(pll_28nm->clks,
> pll_28nm->num_clks);
> }
>
> -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct
> clk_hw **provided_clocks)
> {
> char *clk_name, *parent_name, *vco_name;
> struct clk_init_data vco_init = {
> @@ -411,10 +386,9 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
> };
> struct device *dev = &pll_28nm->pdev->dev;
> struct clk **clks = pll_28nm->clks;
> - struct clk **provided_clks = pll_28nm->provided_clks;
> struct clk_bytediv *bytediv;
> struct clk_init_data bytediv_init = { };
> - int ret, num = 0;
> + int num = 0;
>
> DBG("%d", pll_28nm->id);
>
> @@ -426,10 +400,6 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
> if (!vco_name)
> return -ENOMEM;
>
> - parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
> - if (!parent_name)
> - return -ENOMEM;
> -
> clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
> if (!clk_name)
> return -ENOMEM;
> @@ -457,29 +427,19 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm)
> bytediv_init.num_parents = 1;
>
> /* DIV2 */
> - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
> - clk_register(dev, &bytediv->hw);
> + clks[num++] = clk_register(dev, &bytediv->hw);
> + provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
>
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> /* DIV3 */
> - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
> - clk_register_divider(dev, clk_name,
> + clks[num++] = clk_register_divider(dev, clk_name,
> parent_name, 0, pll_28nm->mmio +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
> 0, 8, 0, NULL);
> + provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
>
> pll_28nm->num_clks = num;
>
> - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
> - pll_28nm->clk_data.clks = provided_clks;
> -
> - ret = of_clk_add_provider(dev->of_node,
> - of_clk_src_onecell_get, &pll_28nm->clk_data);
> - if (ret) {
> - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
> - return ret;
> - }
> -
> return 0;
> }
>
> @@ -511,7 +471,7 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
>
> pll->cfg = phy->cfg;
>
> - ret = pll_28nm_register(pll_28nm);
> + ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> return ret;
> @@ -702,7 +662,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs
> = {
> .pll_init = dsi_pll_28nm_8960_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_28nm_get_provider,
> .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 5acdfe1f63be..0b601afa9e49 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -36,10 +36,6 @@
> *
> dsi0_pll_post_out_div_clk
> */
>
> -#define DSI_BYTE_PLL_CLK 0
> -#define DSI_PIXEL_PLL_CLK 1
> -#define NUM_PROVIDED_CLKS 2
> -
> #define VCO_REF_CLK_RATE 19200000
>
> struct dsi_pll_regs {
> @@ -116,9 +112,6 @@ struct dsi_pll_7nm {
> struct clk_hw *pclk_mux_hw;
> struct clk_hw *out_dsiclk_hw;
>
> - /* clock-provider: */
> - struct clk_hw_onecell_data *hw_data;
> -
> struct pll_7nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -646,30 +639,11 @@ static int dsi_pll_7nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider,
> - struct clk **pixel_clk_provider)
> -{
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> - struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data;
> -
> - DBG("DSI PLL%d", pll_7nm->id);
> -
> - if (byte_clk_provider)
> - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
> - if (pixel_clk_provider)
> - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
> -
> - return 0;
> -}
> -
> static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> - struct device *dev = &pll_7nm->pdev->dev;
>
> DBG("DSI PLL%d", pll_7nm->id);
> - of_clk_del_provider(dev->of_node);
>
> clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
> clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
> @@ -687,7 +661,7 @@ static void dsi_pll_7nm_destroy(struct msm_dsi_pll
> *pll)
> * state to follow the master PLL's divider/mux state. Therefore, we
> don't
> * require special clock ops that also configure the slave PLL
> registers
> */
> -static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
> +static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct
> clk_hw **provided_clocks)
> {
> char clk_name[32], parent[32], vco_name[32];
> char parent2[32], parent3[32], parent4[32];
> @@ -699,18 +673,11 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm)
> .ops = &clk_ops_dsi_pll_7nm_vco,
> };
> struct device *dev = &pll_7nm->pdev->dev;
> - struct clk_hw_onecell_data *hw_data;
> struct clk_hw *hw;
> int ret;
>
> DBG("DSI%d", pll_7nm->id);
>
> - hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
> - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
> - GFP_KERNEL);
> - if (!hw_data)
> - return -ENOMEM;
> -
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
> pll_7nm->base.clk_hw.init = &vco_init;
>
> @@ -762,7 +729,7 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm)
> }
>
> pll_7nm->byte_clk_hw = hw;
> - hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
> + provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> @@ -822,22 +789,10 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm)
> }
>
> pll_7nm->out_dsiclk_hw = hw;
> - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
> -
> - hw_data->num = NUM_PROVIDED_CLKS;
> - pll_7nm->hw_data = hw_data;
> -
> - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> - pll_7nm->hw_data);
> - if (ret) {
> - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
> - goto err_dsiclk_hw;
> - }
> + provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> return 0;
>
> -err_dsiclk_hw:
> - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
> err_pclk_mux_hw:
> clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
> err_post_out_div_clk_hw:
> @@ -893,7 +848,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
>
> pll_7nm->vco_delay = 1;
>
> - ret = pll_7nm_register(pll_7nm);
> + ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> return ret;
> @@ -1138,7 +1093,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> .pll_init = dsi_pll_7nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_7nm_get_provider,
> .destroy = dsi_pll_7nm_destroy,
> .save_state = dsi_pll_7nm_save_state,
> .restore_state = dsi_pll_7nm_restore_state,
> @@ -1165,7 +1119,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_7nm_8150_cfgs = {
> .pll_init = dsi_pll_7nm_init,
> },
> .pll_ops = {
> - .get_provider = dsi_pll_7nm_get_provider,
> .destroy = dsi_pll_7nm_destroy,
> .save_state = dsi_pll_7nm_save_state,
> .restore_state = dsi_pll_7nm_restore_state,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> index 98ee4560581a..914e95435dcb 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> @@ -57,11 +57,8 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw
> *hw)
> pll->pll_on = false;
> }
>
> -void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
> - struct clk **clks, u32 num_clks)
> +void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32
> num_clks)
> {
> - of_clk_del_provider(pdev->dev.of_node);
> -
> if (!num_clks || !clks)
> return;
>
> @@ -74,17 +71,6 @@ void msm_dsi_pll_helper_unregister_clks(struct
> platform_device *pdev,
> /*
> * DSI PLL API
> */
> -int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
> - struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
> -{
> - if (pll->cfg->pll_ops.get_provider)
> - return pll->cfg->pll_ops.get_provider(pll,
> - byte_clk_provider,
> - pixel_clk_provider);
> -
> - return -EINVAL;
> -}
> -
> void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
> {
> if (pll->cfg->pll_ops.destroy)
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> index 8306911f8318..d819a886beb8 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> @@ -55,8 +55,7 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw
> *hw,
> int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
> void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
> /* misc */
> -void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
> - struct clk **clks, u32 num_clks);
> +void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32
> num_clks);
>
> #endif /* __DSI_PLL_H__ */
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (9 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-29 23:33 ` [Freedreno] " abhinavk
2021-03-30 0:49 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
` (13 subsequent siblings)
24 siblings, 2 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Use devres-enabled version of clock registration functions. This lets us
remove dsi_pll destroy callbacks completely.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 84 ++++---------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 35 +-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 50 +++++------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 39 +++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84 ++++---------------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 17 ----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 -
10 files changed, 71 insertions(+), 249 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 43590f338d20..0970f05cd47f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -95,13 +95,9 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
/* dsi pll */
struct msm_dsi_pll;
#ifdef CONFIG_DRM_MSM_DSI_PLL
-void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
#else
-static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
-{
-}
static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
{
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 69214447f757..df3b91b0ea88 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -744,7 +744,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
fail:
if (phy->pll) {
of_clk_del_provider(dev->of_node);
- msm_dsi_pll_destroy(phy->pll);
phy->pll = NULL;
}
@@ -757,7 +756,6 @@ static int dsi_phy_driver_remove(struct platform_device *pdev)
if (phy && phy->pll) {
of_clk_del_provider(pdev->dev.of_node);
- msm_dsi_pll_destroy(phy->pll);
phy->pll = NULL;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index c3099629fa3b..2c5196844ba9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -23,7 +23,6 @@ struct msm_dsi_phy_ops {
struct msm_dsi_pll_ops {
int (*enable_seq)(struct msm_dsi_pll *pll);
void (*disable_seq)(struct msm_dsi_pll *pll);
- void (*destroy)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 8666da1c29e5..6300b92c65eb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -103,15 +103,6 @@ struct dsi_pll_10nm {
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
- /* private clocks: */
- struct clk_hw *out_div_clk_hw;
- struct clk_hw *bit_clk_hw;
- struct clk_hw *byte_clk_hw;
- struct clk_hw *by_2_bit_clk_hw;
- struct clk_hw *post_out_div_clk_hw;
- struct clk_hw *pclk_mux_hw;
- struct clk_hw *out_dsiclk_hw;
-
struct pll_10nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -614,22 +605,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
-
- DBG("DSI PLL%d", pll_10nm->id);
-
- clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
- clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
- clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
- clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
- clk_hw_unregister(&pll_10nm->base.clk_hw);
-}
-
/*
* The post dividers and mux clocks are created using the standard divider and
* mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
@@ -656,30 +631,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
pll_10nm->base.clk_hw.init = &vco_init;
- ret = clk_hw_register(dev, &pll_10nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
if (ret)
return ret;
snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
- hw = clk_hw_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
pll_10nm->mmio +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_base_clk_hw;
+ goto fail;
}
- pll_10nm->out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
/* BIT CLK: DIV_CTRL_3_0 */
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT,
pll_10nm->phy_cmn_mmio +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
@@ -687,56 +660,49 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
&pll_10nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_out_div_clk_hw;
+ goto fail;
}
- pll_10nm->bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_bit_clk_hw;
+ goto fail;
}
- pll_10nm->byte_clk_hw = hw;
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_byte_clk_hw;
+ goto fail;
}
- pll_10nm->by_2_bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 4);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_by_2_bit_clk_hw;
+ goto fail;
}
- pll_10nm->post_out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
- hw = clk_hw_register_mux(dev, clk_name,
+ hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent, parent2, parent3, parent4
}), 4, 0, pll_10nm->phy_cmn_mmio +
@@ -744,44 +710,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
0, 2, 0, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_post_out_div_clk_hw;
+ goto fail;
}
- pll_10nm->pclk_mux_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
/* PIX CLK DIV : DIV_CTRL_7_4*/
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
0, pll_10nm->phy_cmn_mmio +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
4, 4, CLK_DIVIDER_ONE_BASED,
&pll_10nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_pclk_mux_hw;
+ goto fail;
}
- pll_10nm->out_dsiclk_hw = hw;
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
-err_pclk_mux_hw:
- clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
-err_post_out_div_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
-err_by_2_bit_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
-err_byte_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
-err_bit_clk_hw:
- clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
-err_out_div_clk_hw:
- clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
-err_base_clk_hw:
- clk_hw_unregister(&pll_10nm->base.clk_hw);
+fail:
return ret;
}
@@ -1060,7 +1010,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
},
@@ -1085,7 +1034,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
},
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 07ecdf34f614..7fe7c8348b42 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -133,10 +133,6 @@ struct dsi_pll_14nm {
u64 vco_current_rate;
u64 vco_ref_clk_rate;
- /* private clocks: */
- struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
- u32 num_hws;
-
struct pll_14nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -872,15 +868,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- int num_hws = pll_14nm->num_hws;
-
- while (num_hws--)
- clk_hw_unregister(pll_14nm->hws[num_hws]);
-}
-
static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
const char *name,
const char *parent_name,
@@ -910,7 +897,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
pll_postdiv->hw.init = &postdiv_init;
- ret = clk_hw_register(dev, &pll_postdiv->hw);
+ ret = devm_clk_hw_register(dev, &pll_postdiv->hw);
if (ret)
return ERR_PTR(ret);
@@ -928,9 +915,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
.ops = &clk_ops_dsi_pll_14nm_vco,
};
struct device *dev = &pll_14nm->pdev->dev;
- struct clk_hw **hws = pll_14nm->hws;
struct clk_hw *hw;
- int num = 0;
int ret;
DBG("DSI%d", pll_14nm->id);
@@ -938,12 +923,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
pll_14nm->base.clk_hw.init = &vco_init;
- ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
if (ret)
return ret;
- hws[num++] = &pll_14nm->base.clk_hw;
-
snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
@@ -953,18 +936,15 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- hws[num++] = hw;
-
snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
/* DSI Byte clock = VCO_CLK / N1 / 8 */
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw))
return PTR_ERR(hw);
- hws[num++] = hw;
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
@@ -974,12 +954,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
* Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
* on the way. Don't let it set parent.
*/
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
if (IS_ERR(hw))
return PTR_ERR(hw);
- hws[num++] = hw;
-
snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
@@ -991,11 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- hws[num++] = hw;
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
- pll_14nm->num_hws = num;
-
return 0;
}
@@ -1184,7 +1159,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.pll_init = dsi_pll_14nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
.disable_seq = dsi_pll_14nm_disable_seq,
@@ -1211,7 +1185,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.pll_init = dsi_pll_14nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_14nm_destroy,
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
.disable_seq = dsi_pll_14nm_disable_seq,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 3446be318648..3e9b7949b038 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -74,10 +74,6 @@ struct dsi_pll_28nm {
int vco_delay;
- /* private clocks: */
- struct clk *clks[NUM_DSI_CLOCKS_MAX];
- u32 num_clks;
-
struct pll_28nm_cached_state cached_state;
};
@@ -486,15 +482,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
-
- pll_28nm->num_clks = 0;
-}
-
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
@@ -506,53 +493,63 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
.ops = &clk_ops_dsi_pll_28nm_vco,
};
struct device *dev = &pll_28nm->pdev->dev;
- struct clk **clks = pll_28nm->clks;
- int num = 0;
+ struct clk_hw *hw;
+ int ret;
DBG("%d", pll_28nm->id);
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
pll_28nm->base.clk_hw.init = &vco_init;
- clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
+ if (ret)
+ return ret;
snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
- clks[num++] = clk_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent1, CLK_SET_RATE_PARENT,
pll_28nm->mmio +
REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
0, 4, 0, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
- clks[num++] = clk_register_fixed_factor(dev, clk_name,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
parent1, CLK_SET_RATE_PARENT,
1, 2);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
- clks[num++] = clk_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent1, 0, pll_28nm->mmio +
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
0, 8, 0, NULL);
- provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
- clks[num++] = clk_register_mux(dev, clk_name,
+ hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent1, parent2
}), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
- clks[num++] = clk_register_fixed_factor(dev, clk_name,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
parent1, CLK_SET_RATE_PARENT, 1, 4);
- provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
-
- pll_28nm->num_clks = num;
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ provided_clocks[DSI_BYTE_PLL_CLK] = hw;
return 0;
}
@@ -758,7 +755,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
.disable_seq = dsi_pll_28nm_disable_seq,
@@ -785,7 +781,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
.disable_seq = dsi_pll_28nm_disable_seq,
@@ -812,7 +807,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.pll_init = dsi_pll_28nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
.disable_seq = dsi_pll_28nm_disable_seq,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index c4b433790cfb..45b2bf482392 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -64,13 +64,6 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
- /* custom byte clock divider */
- struct clk_bytediv *bytediv;
-
- /* private clocks: */
- struct clk *clks[NUM_DSI_CLOCKS_MAX];
- u32 num_clks;
-
struct pll_28nm_cached_state cached_state;
};
@@ -368,13 +361,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
-}
-
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
{
char *clk_name, *parent_name, *vco_name;
@@ -385,10 +371,10 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
.ops = &clk_ops_dsi_pll_28nm_vco,
};
struct device *dev = &pll_28nm->pdev->dev;
- struct clk **clks = pll_28nm->clks;
+ struct clk_hw *hw;
struct clk_bytediv *bytediv;
struct clk_init_data bytediv_init = { };
- int num = 0;
+ int ret;
DBG("%d", pll_28nm->id);
@@ -404,14 +390,14 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
if (!clk_name)
return -ENOMEM;
- pll_28nm->bytediv = bytediv;
-
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
vco_init.name = vco_name;
pll_28nm->base.clk_hw.init = &vco_init;
- clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
+ if (ret)
+ return ret;
/* prepare and register bytediv */
bytediv->hw.init = &bytediv_init;
@@ -427,18 +413,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
bytediv_init.num_parents = 1;
/* DIV2 */
- clks[num++] = clk_register(dev, &bytediv->hw);
- provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
+ ret = devm_clk_hw_register(dev, &bytediv->hw);
+ if (ret)
+ return ret;
+ provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
/* DIV3 */
- clks[num++] = clk_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent_name, 0, pll_28nm->mmio +
REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
0, 8, 0, NULL);
- provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
-
- pll_28nm->num_clks = num;
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
}
@@ -662,7 +650,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.pll_init = dsi_pll_28nm_8960_init,
},
.pll_ops = {
- .destroy = dsi_pll_28nm_destroy,
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
.disable_seq = dsi_pll_28nm_disable_seq,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 0b601afa9e49..c482e51d1bee 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -103,15 +103,6 @@ struct dsi_pll_7nm {
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
- /* private clocks: */
- struct clk_hw *out_div_clk_hw;
- struct clk_hw *bit_clk_hw;
- struct clk_hw *byte_clk_hw;
- struct clk_hw *by_2_bit_clk_hw;
- struct clk_hw *post_out_div_clk_hw;
- struct clk_hw *pclk_mux_hw;
- struct clk_hw *out_dsiclk_hw;
-
struct pll_7nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -639,22 +630,6 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
-
- DBG("DSI PLL%d", pll_7nm->id);
-
- clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
- clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
- clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
- clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
- clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
- clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
- clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
- clk_hw_unregister(&pll_7nm->base.clk_hw);
-}
-
/*
* The post dividers and mux clocks are created using the standard divider and
* mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
@@ -681,30 +656,28 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
pll_7nm->base.clk_hw.init = &vco_init;
- ret = clk_hw_register(dev, &pll_7nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw);
if (ret)
return ret;
snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id);
- hw = clk_hw_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
pll_7nm->mmio +
REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_base_clk_hw;
+ goto fail;
}
- pll_7nm->out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
/* BIT CLK: DIV_CTRL_3_0 */
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT,
pll_7nm->phy_cmn_mmio +
REG_DSI_7nm_PHY_CMN_CLK_CFG0,
@@ -712,56 +685,49 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
&pll_7nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_out_div_clk_hw;
+ goto fail;
}
- pll_7nm->bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_bit_clk_hw;
+ goto fail;
}
- pll_7nm->byte_clk_hw = hw;
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_byte_clk_hw;
+ goto fail;
}
- pll_7nm->by_2_bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 4);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_by_2_bit_clk_hw;
+ goto fail;
}
- pll_7nm->post_out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
- hw = clk_hw_register_mux(dev, clk_name,
+ hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent, parent2, parent3, parent4
}), 4, 0, pll_7nm->phy_cmn_mmio +
@@ -769,44 +735,28 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
0, 2, 0, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_post_out_div_clk_hw;
+ goto fail;
}
- pll_7nm->pclk_mux_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id);
snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id);
/* PIX CLK DIV : DIV_CTRL_7_4*/
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
0, pll_7nm->phy_cmn_mmio +
REG_DSI_7nm_PHY_CMN_CLK_CFG0,
4, 4, CLK_DIVIDER_ONE_BASED,
&pll_7nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_pclk_mux_hw;
+ goto fail;
}
- pll_7nm->out_dsiclk_hw = hw;
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
-err_pclk_mux_hw:
- clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
-err_post_out_div_clk_hw:
- clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
-err_by_2_bit_clk_hw:
- clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
-err_byte_clk_hw:
- clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
-err_bit_clk_hw:
- clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
-err_out_div_clk_hw:
- clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
-err_base_clk_hw:
- clk_hw_unregister(&pll_7nm->base.clk_hw);
+fail:
return ret;
}
@@ -1093,7 +1043,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.pll_init = dsi_pll_7nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
},
@@ -1119,7 +1068,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.pll_init = dsi_pll_7nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_7nm_destroy,
.save_state = dsi_pll_7nm_save_state,
.restore_state = dsi_pll_7nm_restore_state,
},
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 914e95435dcb..96de79b94f1b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -57,26 +57,9 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
pll->pll_on = false;
}
-void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks)
-{
- if (!num_clks || !clks)
- return;
-
- do {
- clk_unregister(clks[--num_clks]);
- clks[num_clks] = NULL;
- } while (num_clks);
-}
-
/*
* DSI PLL API
*/
-void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
-{
- if (pll->cfg->pll_ops.destroy)
- pll->cfg->pll_ops.destroy(pll);
-}
-
void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
{
if (pll->cfg->pll_ops.save_state) {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index d819a886beb8..c94f079b8275 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -11,8 +11,6 @@
#include "dsi.h"
-#define NUM_DSI_CLOCKS_MAX 6
-
struct msm_dsi_pll {
struct clk_hw clk_hw;
bool pll_on;
@@ -54,8 +52,6 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate);
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
-/* misc */
-void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks);
#endif /* __DSI_PLL_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks
2021-03-27 11:02 ` [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
@ 2021-03-29 23:33 ` abhinavk
2021-03-30 0:49 ` Stephen Boyd
1 sibling, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-29 23:33 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Use devres-enabled version of clock registration functions. This lets
> us
> remove dsi_pll destroy callbacks completely.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 4 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 84 ++++---------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 35 +-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 50 +++++------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 39 +++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84 ++++---------------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 17 ----
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 -
> 10 files changed, 71 insertions(+), 249 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
> b/drivers/gpu/drm/msm/dsi/dsi.h
> index 43590f338d20..0970f05cd47f 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -95,13 +95,9 @@ struct drm_encoder *msm_dsi_get_encoder(struct
> msm_dsi *msm_dsi);
> /* dsi pll */
> struct msm_dsi_pll;
> #ifdef CONFIG_DRM_MSM_DSI_PLL
> -void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
> void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
> int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
> #else
> -static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
> -{
> -}
> static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
> {
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 69214447f757..df3b91b0ea88 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -744,7 +744,6 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> fail:
> if (phy->pll) {
> of_clk_del_provider(dev->of_node);
> - msm_dsi_pll_destroy(phy->pll);
> phy->pll = NULL;
> }
>
> @@ -757,7 +756,6 @@ static int dsi_phy_driver_remove(struct
> platform_device *pdev)
>
> if (phy && phy->pll) {
> of_clk_del_provider(pdev->dev.of_node);
> - msm_dsi_pll_destroy(phy->pll);
> phy->pll = NULL;
> }
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index c3099629fa3b..2c5196844ba9 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -23,7 +23,6 @@ struct msm_dsi_phy_ops {
> struct msm_dsi_pll_ops {
> int (*enable_seq)(struct msm_dsi_pll *pll);
> void (*disable_seq)(struct msm_dsi_pll *pll);
> - void (*destroy)(struct msm_dsi_pll *pll);
> void (*save_state)(struct msm_dsi_pll *pll);
> int (*restore_state)(struct msm_dsi_pll *pll);
> };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 8666da1c29e5..6300b92c65eb 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -103,15 +103,6 @@ struct dsi_pll_10nm {
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> - /* private clocks: */
> - struct clk_hw *out_div_clk_hw;
> - struct clk_hw *bit_clk_hw;
> - struct clk_hw *byte_clk_hw;
> - struct clk_hw *by_2_bit_clk_hw;
> - struct clk_hw *post_out_div_clk_hw;
> - struct clk_hw *pclk_mux_hw;
> - struct clk_hw *out_dsiclk_hw;
> -
> struct pll_10nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -614,22 +605,6 @@ static int dsi_pll_10nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> -
> - DBG("DSI PLL%d", pll_10nm->id);
> -
> - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
> - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
> - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
> - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
> - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
> - clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
> - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
> - clk_hw_unregister(&pll_10nm->base.clk_hw);
> -}
> -
> /*
> * The post dividers and mux clocks are created using the standard
> divider and
> * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its
> dividers/mux
> @@ -656,30 +631,28 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
> pll_10nm->base.clk_hw.init = &vco_init;
>
> - ret = clk_hw_register(dev, &pll_10nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
> if (ret)
> return ret;
>
> snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
>
> - hw = clk_hw_register_divider(dev, clk_name,
> + hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> pll_10nm->mmio +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
> 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_base_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->out_div_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
>
> /* BIT CLK: DIV_CTRL_3_0 */
> - hw = clk_hw_register_divider(dev, clk_name, parent,
> + hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> CLK_SET_RATE_PARENT,
> pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> @@ -687,56 +660,49 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> &pll_10nm->postdiv_lock);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_out_div_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->bit_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> CLK_SET_RATE_PARENT, 1, 8);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_bit_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->byte_clk_hw = hw;
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
>
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 2);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_byte_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->by_2_bit_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
>
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 4);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_by_2_bit_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->post_out_div_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
> snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
>
> - hw = clk_hw_register_mux(dev, clk_name,
> + hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent, parent2, parent3, parent4
> }), 4, 0, pll_10nm->phy_cmn_mmio +
> @@ -744,44 +710,28 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> 0, 2, 0, NULL);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_post_out_div_clk_hw;
> + goto fail;
> }
>
> - pll_10nm->pclk_mux_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> - hw = clk_hw_register_divider(dev, clk_name, parent,
> + hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> 0, pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> 4, 4, CLK_DIVIDER_ONE_BASED,
> &pll_10nm->postdiv_lock);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_pclk_mux_hw;
> + goto fail;
> }
>
> - pll_10nm->out_dsiclk_hw = hw;
> provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> return 0;
>
> -err_pclk_mux_hw:
> - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
> -err_post_out_div_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
> -err_by_2_bit_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
> -err_byte_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
> -err_bit_clk_hw:
> - clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
> -err_out_div_clk_hw:
> - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
> -err_base_clk_hw:
> - clk_hw_unregister(&pll_10nm->base.clk_hw);
> +fail:
>
> return ret;
> }
> @@ -1060,7 +1010,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =
> {
> .pll_init = dsi_pll_10nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_10nm_destroy,
> .save_state = dsi_pll_10nm_save_state,
> .restore_state = dsi_pll_10nm_restore_state,
> },
> @@ -1085,7 +1034,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_10nm_8998_cfgs = {
> .pll_init = dsi_pll_10nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_10nm_destroy,
> .save_state = dsi_pll_10nm_save_state,
> .restore_state = dsi_pll_10nm_restore_state,
> },
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 07ecdf34f614..7fe7c8348b42 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -133,10 +133,6 @@ struct dsi_pll_14nm {
> u64 vco_current_rate;
> u64 vco_ref_clk_rate;
>
> - /* private clocks: */
> - struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
> - u32 num_hws;
> -
> struct pll_14nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -872,15 +868,6 @@ static int dsi_pll_14nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> - int num_hws = pll_14nm->num_hws;
> -
> - while (num_hws--)
> - clk_hw_unregister(pll_14nm->hws[num_hws]);
> -}
> -
> static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm
> *pll_14nm,
> const char *name,
> const char *parent_name,
> @@ -910,7 +897,7 @@ static struct clk_hw
> *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
> pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
> pll_postdiv->hw.init = &postdiv_init;
>
> - ret = clk_hw_register(dev, &pll_postdiv->hw);
> + ret = devm_clk_hw_register(dev, &pll_postdiv->hw);
> if (ret)
> return ERR_PTR(ret);
>
> @@ -928,9 +915,7 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> .ops = &clk_ops_dsi_pll_14nm_vco,
> };
> struct device *dev = &pll_14nm->pdev->dev;
> - struct clk_hw **hws = pll_14nm->hws;
> struct clk_hw *hw;
> - int num = 0;
> int ret;
>
> DBG("DSI%d", pll_14nm->id);
> @@ -938,12 +923,10 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
> pll_14nm->base.clk_hw.init = &vco_init;
>
> - ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
> if (ret)
> return ret;
>
> - hws[num++] = &pll_14nm->base.clk_hw;
> -
> snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
> snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
>
> @@ -953,18 +936,15 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - hws[num++] = hw;
> -
> snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
> snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
>
> /* DSI Byte clock = VCO_CLK / N1 / 8 */
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> CLK_SET_RATE_PARENT, 1, 8);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - hws[num++] = hw;
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
> @@ -974,12 +954,10 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
> * on the way. Don't let it set parent.
> */
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1,
> 2);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - hws[num++] = hw;
> -
> snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
> snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
>
> @@ -991,11 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - hws[num++] = hw;
> provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> - pll_14nm->num_hws = num;
> -
> return 0;
> }
>
> @@ -1184,7 +1159,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =
> {
> .pll_init = dsi_pll_14nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_14nm_destroy,
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> .disable_seq = dsi_pll_14nm_disable_seq,
> @@ -1211,7 +1185,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_14nm_660_cfgs = {
> .pll_init = dsi_pll_14nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_14nm_destroy,
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> .disable_seq = dsi_pll_14nm_disable_seq,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 3446be318648..3e9b7949b038 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -74,10 +74,6 @@ struct dsi_pll_28nm {
>
> int vco_delay;
>
> - /* private clocks: */
> - struct clk *clks[NUM_DSI_CLOCKS_MAX];
> - u32 num_clks;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -486,15 +482,6 @@ static int dsi_pll_28nm_restore_state(struct
> msm_dsi_pll *pll)
> return 0;
> }
>
> -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> -
> - msm_dsi_pll_helper_unregister_clks(pll_28nm->clks,
> pll_28nm->num_clks);
> -
> - pll_28nm->num_clks = 0;
> -}
> -
> static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct
> clk_hw **provided_clocks)
> {
> char clk_name[32], parent1[32], parent2[32], vco_name[32];
> @@ -506,53 +493,63 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> .ops = &clk_ops_dsi_pll_28nm_vco,
> };
> struct device *dev = &pll_28nm->pdev->dev;
> - struct clk **clks = pll_28nm->clks;
> - int num = 0;
> + struct clk_hw *hw;
> + int ret;
>
> DBG("%d", pll_28nm->id);
>
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> pll_28nm->base.clk_hw.init = &vco_init;
> - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
> + if (ret)
> + return ret;
>
> snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> - clks[num++] = clk_register_divider(dev, clk_name,
> + hw = devm_clk_hw_register_divider(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT,
> pll_28nm->mmio +
> REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
> 0, 4, 0, NULL);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
>
> snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
> snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
> - clks[num++] = clk_register_fixed_factor(dev, clk_name,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT,
> 1, 2);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
>
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> - clks[num++] = clk_register_divider(dev, clk_name,
> + hw = devm_clk_hw_register_divider(dev, clk_name,
> parent1, 0, pll_28nm->mmio +
> REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> 0, 8, 0, NULL);
> - provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
> - clks[num++] = clk_register_mux(dev, clk_name,
> + hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent1, parent2
> }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
> REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
>
> snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
> - clks[num++] = clk_register_fixed_factor(dev, clk_name,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT, 1, 4);
> - provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
> -
> - pll_28nm->num_clks = num;
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> return 0;
> }
> @@ -758,7 +755,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
> = {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> .disable_seq = dsi_pll_28nm_disable_seq,
> @@ -785,7 +781,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_hpm_famb_cfgs = {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> .disable_seq = dsi_pll_28nm_disable_seq,
> @@ -812,7 +807,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs =
> {
> .pll_init = dsi_pll_28nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> .disable_seq = dsi_pll_28nm_disable_seq,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index c4b433790cfb..45b2bf482392 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -64,13 +64,6 @@ struct dsi_pll_28nm {
> struct platform_device *pdev;
> void __iomem *mmio;
>
> - /* custom byte clock divider */
> - struct clk_bytediv *bytediv;
> -
> - /* private clocks: */
> - struct clk *clks[NUM_DSI_CLOCKS_MAX];
> - u32 num_clks;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -368,13 +361,6 @@ static int dsi_pll_28nm_restore_state(struct
> msm_dsi_pll *pll)
> return 0;
> }
>
> -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> -
> - msm_dsi_pll_helper_unregister_clks(pll_28nm->clks,
> pll_28nm->num_clks);
> -}
> -
> static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct
> clk_hw **provided_clocks)
> {
> char *clk_name, *parent_name, *vco_name;
> @@ -385,10 +371,10 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> .ops = &clk_ops_dsi_pll_28nm_vco,
> };
> struct device *dev = &pll_28nm->pdev->dev;
> - struct clk **clks = pll_28nm->clks;
> + struct clk_hw *hw;
> struct clk_bytediv *bytediv;
> struct clk_init_data bytediv_init = { };
> - int num = 0;
> + int ret;
>
> DBG("%d", pll_28nm->id);
>
> @@ -404,14 +390,14 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> if (!clk_name)
> return -ENOMEM;
>
> - pll_28nm->bytediv = bytediv;
> -
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> vco_init.name = vco_name;
>
> pll_28nm->base.clk_hw.init = &vco_init;
>
> - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
> + if (ret)
> + return ret;
>
> /* prepare and register bytediv */
> bytediv->hw.init = &bytediv_init;
> @@ -427,18 +413,20 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> bytediv_init.num_parents = 1;
>
> /* DIV2 */
> - clks[num++] = clk_register(dev, &bytediv->hw);
> - provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
> + ret = devm_clk_hw_register(dev, &bytediv->hw);
> + if (ret)
> + return ret;
> + provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;
>
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> /* DIV3 */
> - clks[num++] = clk_register_divider(dev, clk_name,
> + hw = devm_clk_hw_register_divider(dev, clk_name,
> parent_name, 0, pll_28nm->mmio +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
> 0, 8, 0, NULL);
> - provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
> -
> - pll_28nm->num_clks = num;
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> return 0;
> }
> @@ -662,7 +650,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs
> = {
> .pll_init = dsi_pll_28nm_8960_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_28nm_destroy,
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> .disable_seq = dsi_pll_28nm_disable_seq,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 0b601afa9e49..c482e51d1bee 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -103,15 +103,6 @@ struct dsi_pll_7nm {
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> - /* private clocks: */
> - struct clk_hw *out_div_clk_hw;
> - struct clk_hw *bit_clk_hw;
> - struct clk_hw *byte_clk_hw;
> - struct clk_hw *by_2_bit_clk_hw;
> - struct clk_hw *post_out_div_clk_hw;
> - struct clk_hw *pclk_mux_hw;
> - struct clk_hw *out_dsiclk_hw;
> -
> struct pll_7nm_cached_state cached_state;
>
> enum msm_dsi_phy_usecase uc;
> @@ -639,22 +630,6 @@ static int dsi_pll_7nm_set_usecase(struct
> msm_dsi_pll *pll,
> return 0;
> }
>
> -static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> -
> - DBG("DSI PLL%d", pll_7nm->id);
> -
> - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
> - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
> - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
> - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
> - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
> - clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
> - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
> - clk_hw_unregister(&pll_7nm->base.clk_hw);
> -}
> -
> /*
> * The post dividers and mux clocks are created using the standard
> divider and
> * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its
> dividers/mux
> @@ -681,30 +656,28 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
> pll_7nm->base.clk_hw.init = &vco_init;
>
> - ret = clk_hw_register(dev, &pll_7nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw);
> if (ret)
> return ret;
>
> snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id);
>
> - hw = clk_hw_register_divider(dev, clk_name,
> + hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> pll_7nm->mmio +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
> 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_base_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->out_div_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
>
> /* BIT CLK: DIV_CTRL_3_0 */
> - hw = clk_hw_register_divider(dev, clk_name, parent,
> + hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> CLK_SET_RATE_PARENT,
> pll_7nm->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> @@ -712,56 +685,49 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> &pll_7nm->postdiv_lock);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_out_div_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->bit_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> CLK_SET_RATE_PARENT, 1, 8);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_bit_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->byte_clk_hw = hw;
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
>
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 2);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_byte_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->by_2_bit_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
>
> - hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
> + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 4);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_by_2_bit_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->post_out_div_clk_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
> snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
>
> - hw = clk_hw_register_mux(dev, clk_name,
> + hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent, parent2, parent3, parent4
> }), 4, 0, pll_7nm->phy_cmn_mmio +
> @@ -769,44 +735,28 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> 0, 2, 0, NULL);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_post_out_div_clk_hw;
> + goto fail;
> }
>
> - pll_7nm->pclk_mux_hw = hw;
> -
> snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id);
> snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id);
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> - hw = clk_hw_register_divider(dev, clk_name, parent,
> + hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> 0, pll_7nm->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> 4, 4, CLK_DIVIDER_ONE_BASED,
> &pll_7nm->postdiv_lock);
> if (IS_ERR(hw)) {
> ret = PTR_ERR(hw);
> - goto err_pclk_mux_hw;
> + goto fail;
> }
>
> - pll_7nm->out_dsiclk_hw = hw;
> provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> return 0;
>
> -err_pclk_mux_hw:
> - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
> -err_post_out_div_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw);
> -err_by_2_bit_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw);
> -err_byte_clk_hw:
> - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw);
> -err_bit_clk_hw:
> - clk_hw_unregister_divider(pll_7nm->bit_clk_hw);
> -err_out_div_clk_hw:
> - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw);
> -err_base_clk_hw:
> - clk_hw_unregister(&pll_7nm->base.clk_hw);
> +fail:
>
> return ret;
> }
> @@ -1093,7 +1043,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> .pll_init = dsi_pll_7nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_7nm_destroy,
> .save_state = dsi_pll_7nm_save_state,
> .restore_state = dsi_pll_7nm_restore_state,
> },
> @@ -1119,7 +1068,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_7nm_8150_cfgs = {
> .pll_init = dsi_pll_7nm_init,
> },
> .pll_ops = {
> - .destroy = dsi_pll_7nm_destroy,
> .save_state = dsi_pll_7nm_save_state,
> .restore_state = dsi_pll_7nm_restore_state,
> },
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> index 914e95435dcb..96de79b94f1b 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> @@ -57,26 +57,9 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw
> *hw)
> pll->pll_on = false;
> }
>
> -void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32
> num_clks)
> -{
> - if (!num_clks || !clks)
> - return;
> -
> - do {
> - clk_unregister(clks[--num_clks]);
> - clks[num_clks] = NULL;
> - } while (num_clks);
> -}
> -
> /*
> * DSI PLL API
> */
> -void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
> -{
> - if (pll->cfg->pll_ops.destroy)
> - pll->cfg->pll_ops.destroy(pll);
> -}
> -
> void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
> {
> if (pll->cfg->pll_ops.save_state) {
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> index d819a886beb8..c94f079b8275 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> @@ -11,8 +11,6 @@
>
> #include "dsi.h"
>
> -#define NUM_DSI_CLOCKS_MAX 6
> -
> struct msm_dsi_pll {
> struct clk_hw clk_hw;
> bool pll_on;
> @@ -54,8 +52,6 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw
> *hw,
> unsigned long rate, unsigned long *parent_rate);
> int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
> void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
> -/* misc */
> -void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32
> num_clks);
>
> #endif /* __DSI_PLL_H__ */
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks
2021-03-27 11:02 ` [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
2021-03-29 23:33 ` [Freedreno] " abhinavk
@ 2021-03-30 0:49 ` Stephen Boyd
1 sibling, 0 replies; 50+ messages in thread
From: Stephen Boyd @ 2021-03-30 0:49 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Jonathan Marek,
Michael Turquette, Rob Clark, Sean Paul
Cc: David Airlie, Daniel Vetter, linux-arm-msm, dri-devel, freedreno,
linux-clk
Subject should say register instead of registe
Quoting Dmitry Baryshkov (2021-03-27 04:02:52)
> Use devres-enabled version of clock registration functions. This lets us
> remove dsi_pll destroy callbacks completely.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 4 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 84 ++++---------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 35 +-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 50 +++++------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 39 +++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84 ++++---------------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 17 ----
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 -
> 10 files changed, 71 insertions(+), 249 deletions(-)
Awesome diffstat!
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (10 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-29 23:43 ` [Freedreno] " abhinavk
2021-03-30 0:50 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov
` (12 subsequent siblings)
24 siblings, 2 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Use devm_of_clk_add_hw_provider() to register provided clocks. This
allows dropping the remove function alltogether.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +---------------------
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index df3b91b0ea88..46561435a27d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -728,7 +728,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
}
}
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
phy->provided_clocks);
if (ret) {
DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret);
@@ -742,31 +742,11 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
return 0;
fail:
- if (phy->pll) {
- of_clk_del_provider(dev->of_node);
- phy->pll = NULL;
- }
-
return ret;
}
-static int dsi_phy_driver_remove(struct platform_device *pdev)
-{
- struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
-
- if (phy && phy->pll) {
- of_clk_del_provider(pdev->dev.of_node);
- phy->pll = NULL;
- }
-
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
static struct platform_driver dsi_phy_platform_driver = {
.probe = dsi_phy_driver_probe,
- .remove = dsi_phy_driver_remove,
.driver = {
.name = "msm_dsi_phy",
.of_match_table = dsi_phy_dt_match,
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider
2021-03-27 11:02 ` [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
@ 2021-03-29 23:43 ` abhinavk
2021-03-30 0:50 ` Stephen Boyd
1 sibling, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-29 23:43 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Use devm_of_clk_add_hw_provider() to register provided clocks. This
> allows dropping the remove function alltogether.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +---------------------
> 1 file changed, 1 insertion(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index df3b91b0ea88..46561435a27d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -728,7 +728,7 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> }
> }
>
> - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> phy->provided_clocks);
> if (ret) {
> DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n",
> __func__, ret);
> @@ -742,31 +742,11 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> return 0;
>
> fail:
> - if (phy->pll) {
> - of_clk_del_provider(dev->of_node);
> - phy->pll = NULL;
> - }
> -
> return ret;
> }
>
> -static int dsi_phy_driver_remove(struct platform_device *pdev)
> -{
> - struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
> -
> - if (phy && phy->pll) {
> - of_clk_del_provider(pdev->dev.of_node);
> - phy->pll = NULL;
> - }
> -
> - platform_set_drvdata(pdev, NULL);
> -
> - return 0;
> -}
> -
> static struct platform_driver dsi_phy_platform_driver = {
> .probe = dsi_phy_driver_probe,
> - .remove = dsi_phy_driver_remove,
> .driver = {
> .name = "msm_dsi_phy",
> .of_match_table = dsi_phy_dt_match,
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider
2021-03-27 11:02 ` [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
2021-03-29 23:43 ` [Freedreno] " abhinavk
@ 2021-03-30 0:50 ` Stephen Boyd
1 sibling, 0 replies; 50+ messages in thread
From: Stephen Boyd @ 2021-03-30 0:50 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Jonathan Marek,
Michael Turquette, Rob Clark, Sean Paul
Cc: David Airlie, Daniel Vetter, linux-arm-msm, dri-devel, freedreno,
linux-clk
Would make it devm_of_clk_add_hw_provider() in the subject
Quoting Dmitry Baryshkov (2021-03-27 04:02:53)
> Use devm_of_clk_add_hw_provider() to register provided clocks. This
> allows dropping the remove function alltogether.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (11 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-29 23:51 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers Dmitry Baryshkov
` (11 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(),
thus removing last bits of knowledge about msm_dsi_pll from dsi_manager.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 18 ++---------
drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 35 +++++++++++++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 26 ----------------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 11 -------
8 files changed, 42 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 0970f05cd47f..53feea9d30c0 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -92,21 +92,6 @@ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
-/* dsi pll */
-struct msm_dsi_pll;
-#ifdef CONFIG_DRM_MSM_DSI_PLL
-void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
-int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
-#else
-static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
-{
-}
-static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
-{
- return 0;
-}
-#endif
-
/* dsi host */
struct msm_dsi_host;
int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
@@ -182,11 +167,12 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timing);
-struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
+void msm_dsi_phy_save_state(struct msm_dsi_phy *phy);
+int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy);
#endif /* __DSI_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 86e36be58701..0c47c5fb1ab3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -498,7 +498,6 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
- struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
@@ -532,9 +531,8 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
id, ret);
}
- /* Save PLL status if it is a clock source */
- src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
- msm_dsi_pll_save_state(src_pll);
+ /* Save PHY status if it is a clock source */
+ msm_dsi_phy_save_state(msm_dsi->phy);
ret = msm_dsi_host_power_off(host);
if (ret)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 46561435a27d..176930800082 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -799,9 +799,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
* source.
*/
if (phy->usecase != MSM_DSI_PHY_SLAVE) {
- ret = msm_dsi_pll_restore_state(phy->pll);
+ ret = msm_dsi_phy_restore_state(phy);
if (ret) {
- DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
+ DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n",
__func__, ret);
goto pll_restor_fail;
}
@@ -838,14 +838,6 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
sizeof(*shared_timings));
}
-struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
-{
- if (!phy)
- return NULL;
-
- return phy->pll;
-}
-
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc)
{
@@ -863,3 +855,26 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
return -EINVAL;
}
+
+void msm_dsi_phy_save_state(struct msm_dsi_phy *phy)
+{
+ if (phy->cfg->pll_ops.save_state) {
+ phy->cfg->pll_ops.save_state(phy->pll);
+ phy->pll->state_saved = true;
+ }
+}
+
+int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy)
+{
+ int ret;
+
+ if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) {
+ ret = phy->cfg->pll_ops.restore_state(phy->pll);
+ if (ret)
+ return ret;
+
+ phy->pll->state_saved = false;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 2c5196844ba9..8133732e0c7f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -6,6 +6,7 @@
#ifndef __DSI_PHY_H__
#define __DSI_PHY_H__
+#include <linux/clk-provider.h>
#include <linux/regulator/consumer.h>
#include "dsi.h"
@@ -13,6 +14,16 @@
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
+struct msm_dsi_pll {
+ struct clk_hw clk_hw;
+ bool pll_on;
+ bool state_saved;
+
+ const struct msm_dsi_phy_cfg *cfg;
+};
+
+#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
+
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 6300b92c65eb..e0df12a841b2 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -782,7 +782,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
phy->pll = pll;
/* TODO: Remove this when we have proper display handover support */
- msm_dsi_pll_save_state(pll);
+ msm_dsi_phy_save_state(phy);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index c482e51d1bee..e6c8040e1bd3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -807,7 +807,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
phy->pll = pll;
/* TODO: Remove this when we have proper display handover support */
- msm_dsi_pll_save_state(pll);
+ msm_dsi_phy_save_state(phy);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 96de79b94f1b..652c2d6bfeec 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -56,29 +56,3 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
pll->pll_on = false;
}
-
-/*
- * DSI PLL API
- */
-void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
-{
- if (pll->cfg->pll_ops.save_state) {
- pll->cfg->pll_ops.save_state(pll);
- pll->state_saved = true;
- }
-}
-
-int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
-{
- int ret;
-
- if (pll->cfg->pll_ops.restore_state && pll->state_saved) {
- ret = pll->cfg->pll_ops.restore_state(pll);
- if (ret)
- return ret;
-
- pll->state_saved = false;
- }
-
- return 0;
-}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index c94f079b8275..eca13cf67c21 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -6,21 +6,10 @@
#ifndef __DSI_PLL_H__
#define __DSI_PLL_H__
-#include <linux/clk-provider.h>
#include <linux/delay.h>
#include "dsi.h"
-struct msm_dsi_pll {
- struct clk_hw clk_hw;
- bool pll_on;
- bool state_saved;
-
- const struct msm_dsi_phy_cfg *cfg;
-};
-
-#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
-
static inline void pll_write(void __iomem *reg, u32 data)
{
msm_writel(data, reg);
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions
2021-03-27 11:02 ` [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov
@ 2021-03-29 23:51 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-29 23:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Morph msm_dsi_pll_save/restore_state() into
> msm_dsi_phy_save/restore_state(),
> thus removing last bits of knowledge about msm_dsi_pll from
> dsi_manager.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 18 ++---------
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 35 +++++++++++++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++++++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 26 ----------------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 11 -------
> 8 files changed, 42 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
> b/drivers/gpu/drm/msm/dsi/dsi.h
> index 0970f05cd47f..53feea9d30c0 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -92,21 +92,6 @@ static inline bool msm_dsi_device_connected(struct
> msm_dsi *msm_dsi)
>
> struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
>
> -/* dsi pll */
> -struct msm_dsi_pll;
> -#ifdef CONFIG_DRM_MSM_DSI_PLL
> -void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
> -int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
> -#else
> -static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
> -{
> -}
> -static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
> -{
> - return 0;
> -}
> -#endif
> -
> /* dsi host */
> struct msm_dsi_host;
> int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
> @@ -182,11 +167,12 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
> int src_pll_id,
> void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
> void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_shared_timings *shared_timing);
> -struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
> void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
> enum msm_dsi_phy_usecase uc);
> int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
> struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
> +void msm_dsi_phy_save_state(struct msm_dsi_phy *phy);
> +int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy);
I think renaming these to
msm_dsi_phy_pll_save_state()/msm_dsi_phy_pll_restore_state()
will be better because internally they are only saving/restoring PLL
states,
Once thats fixed, please feel free to add :
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>
> #endif /* __DSI_CONNECTOR_H__ */
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 86e36be58701..0c47c5fb1ab3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -498,7 +498,6 @@ static void dsi_mgr_bridge_post_disable(struct
> drm_bridge *bridge)
> struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
> struct mipi_dsi_host *host = msm_dsi->host;
> struct drm_panel *panel = msm_dsi->panel;
> - struct msm_dsi_pll *src_pll;
> bool is_dual_dsi = IS_DUAL_DSI();
> int ret;
>
> @@ -532,9 +531,8 @@ static void dsi_mgr_bridge_post_disable(struct
> drm_bridge *bridge)
> id, ret);
> }
>
> - /* Save PLL status if it is a clock source */
> - src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
> - msm_dsi_pll_save_state(src_pll);
> + /* Save PHY status if it is a clock source */
> + msm_dsi_phy_save_state(msm_dsi->phy);
>
> ret = msm_dsi_host_power_off(host);
> if (ret)
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 46561435a27d..176930800082 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -799,9 +799,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
> int src_pll_id,
> * source.
> */
> if (phy->usecase != MSM_DSI_PHY_SLAVE) {
> - ret = msm_dsi_pll_restore_state(phy->pll);
> + ret = msm_dsi_phy_restore_state(phy);
> if (ret) {
> - DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
> + DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n",
> __func__, ret);
> goto pll_restor_fail;
> }
> @@ -838,14 +838,6 @@ void msm_dsi_phy_get_shared_timings(struct
> msm_dsi_phy *phy,
> sizeof(*shared_timings));
> }
>
> -struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
> -{
> - if (!phy)
> - return NULL;
> -
> - return phy->pll;
> -}
> -
> void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
> enum msm_dsi_phy_usecase uc)
> {
> @@ -863,3 +855,26 @@ int msm_dsi_phy_get_clk_provider(struct
> msm_dsi_phy *phy,
>
> return -EINVAL;
> }
> +
> +void msm_dsi_phy_save_state(struct msm_dsi_phy *phy)
> +{
> + if (phy->cfg->pll_ops.save_state) {
> + phy->cfg->pll_ops.save_state(phy->pll);
> + phy->pll->state_saved = true;
> + }
> +}
> +
> +int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy)
> +{
> + int ret;
> +
> + if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) {
> + ret = phy->cfg->pll_ops.restore_state(phy->pll);
> + if (ret)
> + return ret;
> +
> + phy->pll->state_saved = false;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 2c5196844ba9..8133732e0c7f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -6,6 +6,7 @@
> #ifndef __DSI_PHY_H__
> #define __DSI_PHY_H__
>
> +#include <linux/clk-provider.h>
> #include <linux/regulator/consumer.h>
>
> #include "dsi.h"
> @@ -13,6 +14,16 @@
> #define dsi_phy_read(offset) msm_readl((offset))
> #define dsi_phy_write(offset, data) msm_writel((data), (offset))
>
> +struct msm_dsi_pll {
> + struct clk_hw clk_hw;
> + bool pll_on;
> + bool state_saved;
> +
> + const struct msm_dsi_phy_cfg *cfg;
> +};
> +
> +#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
> +
> struct msm_dsi_phy_ops {
> int (*pll_init)(struct msm_dsi_phy *phy);
> int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 6300b92c65eb..e0df12a841b2 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -782,7 +782,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> phy->pll = pll;
>
> /* TODO: Remove this when we have proper display handover support */
> - msm_dsi_pll_save_state(pll);
> + msm_dsi_phy_save_state(phy);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index c482e51d1bee..e6c8040e1bd3 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -807,7 +807,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> phy->pll = pll;
>
> /* TODO: Remove this when we have proper display handover support */
> - msm_dsi_pll_save_state(pll);
> + msm_dsi_phy_save_state(phy);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> index 96de79b94f1b..652c2d6bfeec 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> @@ -56,29 +56,3 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw
> *hw)
>
> pll->pll_on = false;
> }
> -
> -/*
> - * DSI PLL API
> - */
> -void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
> -{
> - if (pll->cfg->pll_ops.save_state) {
> - pll->cfg->pll_ops.save_state(pll);
> - pll->state_saved = true;
> - }
> -}
> -
> -int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
> -{
> - int ret;
> -
> - if (pll->cfg->pll_ops.restore_state && pll->state_saved) {
> - ret = pll->cfg->pll_ops.restore_state(pll);
> - if (ret)
> - return ret;
> -
> - pll->state_saved = false;
> - }
> -
> - return 0;
> -}
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> index c94f079b8275..eca13cf67c21 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> @@ -6,21 +6,10 @@
> #ifndef __DSI_PLL_H__
> #define __DSI_PLL_H__
>
> -#include <linux/clk-provider.h>
> #include <linux/delay.h>
>
> #include "dsi.h"
>
> -struct msm_dsi_pll {
> - struct clk_hw clk_hw;
> - bool pll_on;
> - bool state_saved;
> -
> - const struct msm_dsi_phy_cfg *cfg;
> -};
> -
> -#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
> -
> static inline void pll_write(void __iomem *reg, u32 data)
> {
> msm_writel(data, reg);
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (12 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 0:01 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver Dmitry Baryshkov
` (10 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
These drivers do not use vco_delay variable, so drop it from all of
them.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 ---
3 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index e0df12a841b2..bfb96d87d1d7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -99,7 +99,6 @@ struct dsi_pll_10nm {
/* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
- int vco_delay;
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
@@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
pll = &pll_10nm->base;
pll->cfg = phy->cfg;
- pll_10nm->vco_delay = 1;
-
ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 7fe7c8348b42..434d02ffa7fe 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -122,8 +122,6 @@ struct dsi_pll_14nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
- int vco_delay;
-
struct dsi_pll_input in;
struct dsi_pll_output out;
@@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
pll = &pll_14nm->base;
pll->cfg = phy->cfg;
- pll_14nm->vco_delay = 1;
-
ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index e6c8040e1bd3..f760904efac9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -99,7 +99,6 @@ struct dsi_pll_7nm {
/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
- int vco_delay;
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
@@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
pll = &pll_7nm->base;
pll->cfg = phy->cfg;
- pll_7nm->vco_delay = 1;
-
ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers
2021-03-27 11:02 ` [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers Dmitry Baryshkov
@ 2021-03-30 0:01 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 0:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> These drivers do not use vco_delay variable, so drop it from all of
> them.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 ---
> 3 files changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index e0df12a841b2..bfb96d87d1d7 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -99,7 +99,6 @@ struct dsi_pll_10nm {
> /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - int vco_delay;
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_10nm->base;
> pll->cfg = phy->cfg;
>
> - pll_10nm->vco_delay = 1;
> -
> ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 7fe7c8348b42..434d02ffa7fe 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -122,8 +122,6 @@ struct dsi_pll_14nm {
> void __iomem *phy_cmn_mmio;
> void __iomem *mmio;
>
> - int vco_delay;
> -
> struct dsi_pll_input in;
> struct dsi_pll_output out;
>
> @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_14nm->base;
> pll->cfg = phy->cfg;
>
> - pll_14nm->vco_delay = 1;
> -
> ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index e6c8040e1bd3..f760904efac9 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -99,7 +99,6 @@ struct dsi_pll_7nm {
> /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - int vco_delay;
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_7nm->base;
> pll->cfg = phy->cfg;
>
> - pll_7nm->vco_delay = 1;
> -
> ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (13 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 0:03 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov
` (9 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Instead of setting the variable and then using it just in the one place,
determine vco_delay directly at the PLL configuration time.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 3e9b7949b038..ed369eb18e9d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -72,8 +72,6 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
- int vco_delay;
-
struct pll_28nm_cached_state cached_state;
};
@@ -212,8 +210,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
/* Add hardware recommended delay for correct PLL configuration */
- if (pll_28nm->vco_delay)
- udelay(pll_28nm->vco_delay);
+ if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
+ udelay(1000);
+ else
+ udelay(1);
pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
@@ -580,10 +580,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
pll = &pll_28nm->base;
pll->cfg = phy->cfg;
- if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
- pll_28nm->vco_delay = 1000;
- else
- pll_28nm->vco_delay = 1;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver
2021-03-27 11:02 ` [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver Dmitry Baryshkov
@ 2021-03-30 0:03 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 0:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Instead of setting the variable and then using it just in the one
> place,
> determine vco_delay directly at the PLL configuration time.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
The subject line should still be "drm/msm/dsi" and not "drm/msm/dpu".
Once thats fixed, please apply
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 3e9b7949b038..ed369eb18e9d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -72,8 +72,6 @@ struct dsi_pll_28nm {
> struct platform_device *pdev;
> void __iomem *mmio;
>
> - int vco_delay;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -212,8 +210,10 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
> pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
>
> /* Add hardware recommended delay for correct PLL configuration */
> - if (pll_28nm->vco_delay)
> - udelay(pll_28nm->vco_delay);
> + if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> + udelay(1000);
> + else
> + udelay(1);
>
> pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
> pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
> @@ -580,10 +580,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
>
> pll = &pll_28nm->base;
> pll->cfg = phy->cfg;
> - if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> - pll_28nm->vco_delay = 1000;
> - else
> - pll_28nm->vco_delay = 1;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> if (ret) {
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (14 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 0:50 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov
` (8 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
10nm and 7nm already do not use these helpers, as they handle setting
slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
remove unnecessary indirection and drop enable_seq/disable_seq PLL
callbacks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 87 +++++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 86 ++++++++-----
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 120 ++++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 35 -----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 2 -
6 files changed, 171 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 8133732e0c7f..b477d21804c8 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -32,8 +32,6 @@ struct msm_dsi_phy_ops {
};
struct msm_dsi_pll_ops {
- int (*enable_seq)(struct msm_dsi_pll *pll);
- void (*disable_seq)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 434d02ffa7fe..91c5bb2fd169 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -652,12 +652,58 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
return (unsigned long)vco_rate;
}
+static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *base = pll_14nm->mmio;
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ bool locked;
+
+ DBG("");
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
+
+ locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
+ POLL_TIMEOUT_US);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+
+ DBG("");
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_14nm_vco_set_rate,
.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_14nm_vco_prepare,
+ .unprepare = dsi_pll_14nm_vco_unprepare,
};
/*
@@ -749,39 +795,6 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
* PLL Callbacks
*/
-static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *base = pll_14nm->mmio;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
- bool locked;
-
- DBG("");
-
- pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
-
- locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
- POLL_TIMEOUT_US);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
-
- DBG("");
-
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
-}
-
static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
@@ -1157,8 +1170,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -1183,8 +1194,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index ed369eb18e9d..20b31398b540 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -289,19 +289,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
-static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
- .set_rate = dsi_pll_28nm_clk_set_rate,
- .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
- .is_enabled = dsi_pll_28nm_clk_is_enabled,
-};
-
-/*
- * PLL Callbacks
- */
-static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
@@ -376,21 +364,28 @@ static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
return locked ? 0 : -EINVAL;
}
-static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
int i, ret;
+ if (unlikely(pll->pll_on))
+ return 0;
+
for (i = 0; i < 3; i++) {
- ret = _dsi_pll_28nm_enable_seq_hpm(pll);
- if (!ret)
+ ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
+ if (!ret) {
+ pll->pll_on = true;
return 0;
+ }
}
return ret;
}
-static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
@@ -400,6 +395,9 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
DBG("id=%d", pll_28nm->id);
+ if (unlikely(pll->pll_on))
+ return 0;
+
pll_28nm_software_reset(pll_28nm);
/*
@@ -424,22 +422,54 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
- if (unlikely(!locked))
+ if (unlikely(!locked)) {
DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
+ return -EINVAL;
+ }
- return locked ? 0 : -EINVAL;
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
}
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
+
+ pll->pll_on = false;
}
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_hpm,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_lp,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+/*
+ * PLL Callbacks
+ */
+
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -490,7 +520,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
- .ops = &clk_ops_dsi_pll_28nm_vco,
};
struct device *dev = &pll_28nm->pdev->dev;
struct clk_hw *hw;
@@ -498,6 +527,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
DBG("%d", pll_28nm->id);
+ if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP)
+ vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
+ else
+ vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
+
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
pll_28nm->base.clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
@@ -753,8 +787,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -779,8 +811,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -805,8 +835,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_lp,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 45b2bf482392..952444e3e8f0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -178,12 +178,76 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
+static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct device *dev = &pll_28nm->pdev->dev;
+ void __iomem *base = pll_28nm->mmio;
+ bool locked;
+ unsigned int bit_div, byte_div;
+ int max_reads = 1000, timeout_us = 100;
+ u32 val;
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ /*
+ * before enabling the PLL, configure the bit clock divider since we
+ * don't expose it as a clock to the outside world
+ * 1: read back the byte clock divider that should already be set
+ * 2: divide by 8 to get bit clock divider
+ * 3: write it to POSTDIV1
+ */
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ byte_div = val + 1;
+ bit_div = byte_div / 8;
+
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val &= ~0xf;
+ val |= (bit_div - 1);
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
+
+ /* enable the PLL */
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
+ DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
+
+ locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_28nm_vco_prepare,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
.is_enabled = dsi_pll_28nm_clk_is_enabled,
};
@@ -270,56 +334,6 @@ static const struct clk_ops clk_bytediv_ops = {
/*
* PLL Callbacks
*/
-static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
- struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
- bool locked;
- unsigned int bit_div, byte_div;
- int max_reads = 1000, timeout_us = 100;
- u32 val;
-
- DBG("id=%d", pll_28nm->id);
-
- /*
- * before enabling the PLL, configure the bit clock divider since we
- * don't expose it as a clock to the outside world
- * 1: read back the byte clock divider that should already be set
- * 2: divide by 8 to get bit clock divider
- * 3: write it to POSTDIV1
- */
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
- byte_div = val + 1;
- bit_div = byte_div / 8;
-
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
- val &= ~0xf;
- val |= (bit_div - 1);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
-
- /* enable the PLL */
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
- DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
-
- locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- DBG("id=%d", pll_28nm->id);
- pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
-}
-
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -652,8 +666,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 652c2d6bfeec..cae668b669a4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -21,38 +21,3 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
else
return rate;
}
-
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- int ret = 0;
-
- /*
- * Certain PLLs do not allow VCO rate update when it is on.
- * Keep track of their status to turn on/off after set rate success.
- */
- if (unlikely(pll->pll_on))
- return 0;
-
- ret = pll->cfg->pll_ops.enable_seq(pll);
- if (ret) {
- DRM_ERROR("DSI PLL failed to lock\n");
- return ret;
- }
-
- pll->pll_on = true;
-
- return 0;
-}
-
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-
- if (unlikely(!pll->pll_on))
- return;
-
- pll->cfg->pll_ops.disable_seq(pll);
-
- pll->pll_on = false;
-}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index eca13cf67c21..da83e4c11f4f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -39,8 +39,6 @@ static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
/* clock callbacks */
long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate);
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
#endif /* __DSI_PLL_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare
2021-03-27 11:02 ` [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov
@ 2021-03-30 0:50 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 0:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> 10nm and 7nm already do not use these helpers, as they handle setting
> slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
> remove unnecessary indirection and drop enable_seq/disable_seq PLL
> callbacks.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
There is some amount of duplication of code when we inline the
vco ops to the respective PLL files. Diff stats have infact more
additions than removal, however in terms of the bigger interest of
removing the dsi_pll.c/dsi_pll.h in the coming patchsets
https://patchwork.freedesktop.org/patch/426369/?series=88517&rev=2
I am okay with this change. Hence,
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 87 +++++++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 86 ++++++++-----
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 120 ++++++++++--------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 35 -----
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 2 -
> 6 files changed, 171 insertions(+), 161 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 8133732e0c7f..b477d21804c8 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -32,8 +32,6 @@ struct msm_dsi_phy_ops {
> };
>
> struct msm_dsi_pll_ops {
> - int (*enable_seq)(struct msm_dsi_pll *pll);
> - void (*disable_seq)(struct msm_dsi_pll *pll);
> void (*save_state)(struct msm_dsi_pll *pll);
> int (*restore_state)(struct msm_dsi_pll *pll);
> };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 434d02ffa7fe..91c5bb2fd169 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -652,12 +652,58 @@ static unsigned long
> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
> return (unsigned long)vco_rate;
> }
>
> +static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
> +{
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + void __iomem *base = pll_14nm->mmio;
> + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + bool locked;
> +
> + DBG("");
> +
> + if (unlikely(pll->pll_on))
> + return 0;
> +
> + pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
> + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
> +
> + locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
> + POLL_TIMEOUT_US);
> +
> + if (unlikely(!locked)) {
> + DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
> + return -EINVAL;
> + }
> +
> + DBG("DSI PLL lock success");
> + pll->pll_on = true;
> +
> + return 0;
> +}
> +
> +static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
> +{
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> +
> + DBG("");
> +
> + if (unlikely(!pll->pll_on))
> + return;
> +
> + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
> +
> + pll->pll_on = false;
> +}
> +
> static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
> .round_rate = msm_dsi_pll_helper_clk_round_rate,
> .set_rate = dsi_pll_14nm_vco_set_rate,
> .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
> - .prepare = msm_dsi_pll_helper_clk_prepare,
> - .unprepare = msm_dsi_pll_helper_clk_unprepare,
> + .prepare = dsi_pll_14nm_vco_prepare,
> + .unprepare = dsi_pll_14nm_vco_unprepare,
> };
>
> /*
> @@ -749,39 +795,6 @@ static const struct clk_ops
> clk_ops_dsi_pll_14nm_postdiv = {
> * PLL Callbacks
> */
>
> -static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> - void __iomem *base = pll_14nm->mmio;
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> - bool locked;
> -
> - DBG("");
> -
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
> -
> - locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
> - POLL_TIMEOUT_US);
> -
> - if (unlikely(!locked))
> - DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
> - else
> - DBG("DSI PLL lock success");
> -
> - return locked ? 0 : -EINVAL;
> -}
> -
> -static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> -
> - DBG("");
> -
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
> -}
> -
> static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> @@ -1157,8 +1170,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =
> {
> .pll_ops = {
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> - .disable_seq = dsi_pll_14nm_disable_seq,
> - .enable_seq = dsi_pll_14nm_enable_seq,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -1183,8 +1194,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_14nm_660_cfgs = {
> .pll_ops = {
> .save_state = dsi_pll_14nm_save_state,
> .restore_state = dsi_pll_14nm_restore_state,
> - .disable_seq = dsi_pll_14nm_disable_seq,
> - .enable_seq = dsi_pll_14nm_enable_seq,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index ed369eb18e9d..20b31398b540 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -289,19 +289,7 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> return vco_rate;
> }
>
> -static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> - .set_rate = dsi_pll_28nm_clk_set_rate,
> - .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> - .prepare = msm_dsi_pll_helper_clk_prepare,
> - .unprepare = msm_dsi_pll_helper_clk_unprepare,
> - .is_enabled = dsi_pll_28nm_clk_is_enabled,
> -};
> -
> -/*
> - * PLL Callbacks
> - */
> -static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
> +static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> struct device *dev = &pll_28nm->pdev->dev;
> @@ -376,21 +364,28 @@ static int _dsi_pll_28nm_enable_seq_hpm(struct
> msm_dsi_pll *pll)
> return locked ? 0 : -EINVAL;
> }
>
> -static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
> +static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
> {
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> int i, ret;
>
> + if (unlikely(pll->pll_on))
> + return 0;
> +
> for (i = 0; i < 3; i++) {
> - ret = _dsi_pll_28nm_enable_seq_hpm(pll);
> - if (!ret)
> + ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
> + if (!ret) {
> + pll->pll_on = true;
> return 0;
> + }
> }
>
> return ret;
> }
>
> -static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
> +static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
> {
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> struct device *dev = &pll_28nm->pdev->dev;
> void __iomem *base = pll_28nm->mmio;
> @@ -400,6 +395,9 @@ static int dsi_pll_28nm_enable_seq_lp(struct
> msm_dsi_pll *pll)
>
> DBG("id=%d", pll_28nm->id);
>
> + if (unlikely(pll->pll_on))
> + return 0;
> +
> pll_28nm_software_reset(pll_28nm);
>
> /*
> @@ -424,22 +422,54 @@ static int dsi_pll_28nm_enable_seq_lp(struct
> msm_dsi_pll *pll)
>
> locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
>
> - if (unlikely(!locked))
> + if (unlikely(!locked)) {
> DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
> - else
> - DBG("DSI PLL lock success");
> + return -EINVAL;
> + }
>
> - return locked ? 0 : -EINVAL;
> + DBG("DSI PLL lock success");
> + pll->pll_on = true;
> +
> + return 0;
> }
>
> -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
> +static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
> {
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>
> DBG("id=%d", pll_28nm->id);
> +
> + if (unlikely(!pll->pll_on))
> + return;
> +
> pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
> +
> + pll->pll_on = false;
> }
>
> +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
> + .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .set_rate = dsi_pll_28nm_clk_set_rate,
> + .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> + .prepare = dsi_pll_28nm_vco_prepare_hpm,
> + .unprepare = dsi_pll_28nm_vco_unprepare,
> + .is_enabled = dsi_pll_28nm_clk_is_enabled,
> +};
> +
> +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
> + .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .set_rate = dsi_pll_28nm_clk_set_rate,
> + .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> + .prepare = dsi_pll_28nm_vco_prepare_lp,
> + .unprepare = dsi_pll_28nm_vco_unprepare,
> + .is_enabled = dsi_pll_28nm_clk_is_enabled,
> +};
> +
> +/*
> + * PLL Callbacks
> + */
> +
> static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> @@ -490,7 +520,6 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> .num_parents = 1,
> .name = vco_name,
> .flags = CLK_IGNORE_UNUSED,
> - .ops = &clk_ops_dsi_pll_28nm_vco,
> };
> struct device *dev = &pll_28nm->pdev->dev;
> struct clk_hw *hw;
> @@ -498,6 +527,11 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>
> DBG("%d", pll_28nm->id);
>
> + if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP)
> + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> + else
> + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
> +
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> pll_28nm->base.clk_hw.init = &vco_init;
> ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
> @@ -753,8 +787,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
> = {
> .pll_ops = {
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> - .disable_seq = dsi_pll_28nm_disable_seq,
> - .enable_seq = dsi_pll_28nm_enable_seq_hpm,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -779,8 +811,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_hpm_famb_cfgs = {
> .pll_ops = {
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> - .disable_seq = dsi_pll_28nm_disable_seq,
> - .enable_seq = dsi_pll_28nm_enable_seq_hpm,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -805,8 +835,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs =
> {
> .pll_ops = {
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> - .disable_seq = dsi_pll_28nm_disable_seq,
> - .enable_seq = dsi_pll_28nm_enable_seq_lp,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 45b2bf482392..952444e3e8f0 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -178,12 +178,76 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> return vco_rate;
> }
>
> +static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
> +{
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct device *dev = &pll_28nm->pdev->dev;
> + void __iomem *base = pll_28nm->mmio;
> + bool locked;
> + unsigned int bit_div, byte_div;
> + int max_reads = 1000, timeout_us = 100;
> + u32 val;
> +
> + DBG("id=%d", pll_28nm->id);
> +
> + if (unlikely(pll->pll_on))
> + return 0;
> +
> + /*
> + * before enabling the PLL, configure the bit clock divider since we
> + * don't expose it as a clock to the outside world
> + * 1: read back the byte clock divider that should already be set
> + * 2: divide by 8 to get bit clock divider
> + * 3: write it to POSTDIV1
> + */
> + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> + byte_div = val + 1;
> + bit_div = byte_div / 8;
> +
> + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> + val &= ~0xf;
> + val |= (bit_div - 1);
> + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
> +
> + /* enable the PLL */
> + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> + DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
> +
> + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
> +
> + if (unlikely(!locked)) {
> + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
> + return -EINVAL;
> + }
> +
> + DBG("DSI PLL lock success");
> + pll->pll_on = true;
> +
> + return 0;
> +}
> +
> +static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
> +{
> + struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> +
> + DBG("id=%d", pll_28nm->id);
> +
> + if (unlikely(!pll->pll_on))
> + return;
> +
> + pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
> +
> + pll->pll_on = false;
> +}
> +
> static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
> .round_rate = msm_dsi_pll_helper_clk_round_rate,
> .set_rate = dsi_pll_28nm_clk_set_rate,
> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> - .prepare = msm_dsi_pll_helper_clk_prepare,
> - .unprepare = msm_dsi_pll_helper_clk_unprepare,
> + .prepare = dsi_pll_28nm_vco_prepare,
> + .unprepare = dsi_pll_28nm_vco_unprepare,
> .is_enabled = dsi_pll_28nm_clk_is_enabled,
> };
>
> @@ -270,56 +334,6 @@ static const struct clk_ops clk_bytediv_ops = {
> /*
> * PLL Callbacks
> */
> -static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> - struct device *dev = &pll_28nm->pdev->dev;
> - void __iomem *base = pll_28nm->mmio;
> - bool locked;
> - unsigned int bit_div, byte_div;
> - int max_reads = 1000, timeout_us = 100;
> - u32 val;
> -
> - DBG("id=%d", pll_28nm->id);
> -
> - /*
> - * before enabling the PLL, configure the bit clock divider since we
> - * don't expose it as a clock to the outside world
> - * 1: read back the byte clock divider that should already be set
> - * 2: divide by 8 to get bit clock divider
> - * 3: write it to POSTDIV1
> - */
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> - byte_div = val + 1;
> - bit_div = byte_div / 8;
> -
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> - val &= ~0xf;
> - val |= (bit_div - 1);
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
> -
> - /* enable the PLL */
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> - DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
> -
> - locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
> -
> - if (unlikely(!locked))
> - DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
> - else
> - DBG("DSI PLL lock success");
> -
> - return locked ? 0 : -EINVAL;
> -}
> -
> -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
> -{
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> -
> - DBG("id=%d", pll_28nm->id);
> - pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
> -}
> -
> static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> @@ -652,8 +666,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs
> = {
> .pll_ops = {
> .save_state = dsi_pll_28nm_save_state,
> .restore_state = dsi_pll_28nm_restore_state,
> - .disable_seq = dsi_pll_28nm_disable_seq,
> - .enable_seq = dsi_pll_28nm_enable_seq,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> index 652c2d6bfeec..cae668b669a4 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> @@ -21,38 +21,3 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw
> *hw,
> else
> return rate;
> }
> -
> -int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
> -{
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - int ret = 0;
> -
> - /*
> - * Certain PLLs do not allow VCO rate update when it is on.
> - * Keep track of their status to turn on/off after set rate success.
> - */
> - if (unlikely(pll->pll_on))
> - return 0;
> -
> - ret = pll->cfg->pll_ops.enable_seq(pll);
> - if (ret) {
> - DRM_ERROR("DSI PLL failed to lock\n");
> - return ret;
> - }
> -
> - pll->pll_on = true;
> -
> - return 0;
> -}
> -
> -void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
> -{
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> -
> - if (unlikely(!pll->pll_on))
> - return;
> -
> - pll->cfg->pll_ops.disable_seq(pll);
> -
> - pll->pll_on = false;
> -}
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> index eca13cf67c21..da83e4c11f4f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> @@ -39,8 +39,6 @@ static inline void pll_write_ndelay(void __iomem
> *reg, u32 data, u32 delay_ns)
> /* clock callbacks */
> long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
> unsigned long rate, unsigned long *parent_rate);
> -int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
> -void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
>
> #endif /* __DSI_PLL_H__ */
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (15 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 3:09 ` abhinavk
2021-03-27 11:02 ` [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov
` (7 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Make save_state/restore callbacks accept struct msm_dsi_phy rather than
struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
us to drop struct msm_dsi_pll_ops.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 12 +++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 22 +++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 24 ++++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 34 ++++++++-----------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 18 +++++-----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 22 +++++-------
7 files changed, 60 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 176930800082..f21f3babec68 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -858,9 +858,9 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
void msm_dsi_phy_save_state(struct msm_dsi_phy *phy)
{
- if (phy->cfg->pll_ops.save_state) {
- phy->cfg->pll_ops.save_state(phy->pll);
- phy->pll->state_saved = true;
+ if (phy->cfg->ops.save_state) {
+ phy->cfg->ops.save_state(phy);
+ phy->state_saved = true;
}
}
@@ -868,12 +868,12 @@ int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy)
{
int ret;
- if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) {
- ret = phy->cfg->pll_ops.restore_state(phy->pll);
+ if (phy->cfg->ops.restore_state && phy->state_saved) {
+ ret = phy->cfg->ops.restore_state(phy);
if (ret)
return ret;
- phy->pll->state_saved = false;
+ phy->state_saved = false;
}
return 0;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index b477d21804c8..fa09f4c2c071 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -17,7 +17,6 @@
struct msm_dsi_pll {
struct clk_hw clk_hw;
bool pll_on;
- bool state_saved;
const struct msm_dsi_phy_cfg *cfg;
};
@@ -29,17 +28,13 @@ struct msm_dsi_phy_ops {
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_phy_clk_request *clk_req);
void (*disable)(struct msm_dsi_phy *phy);
-};
-
-struct msm_dsi_pll_ops {
- void (*save_state)(struct msm_dsi_pll *pll);
- int (*restore_state)(struct msm_dsi_pll *pll);
+ void (*save_state)(struct msm_dsi_phy *phy);
+ int (*restore_state)(struct msm_dsi_phy *phy);
};
struct msm_dsi_phy_cfg {
struct dsi_reg_config reg_cfg;
struct msm_dsi_phy_ops ops;
- const struct msm_dsi_pll_ops pll_ops;
unsigned long min_pll_rate;
unsigned long max_pll_rate;
@@ -115,6 +110,8 @@ struct msm_dsi_phy {
struct msm_dsi_pll *pll;
struct clk_hw_onecell_data *provided_clocks;
+
+ bool state_saved;
};
/*
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index bfb96d87d1d7..25fd4d860c4d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -518,9 +518,9 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
* PLL Callbacks
*/
-static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll)
+static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
@@ -541,9 +541,9 @@ static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll)
cached->pix_clk_div, cached->pll_mux);
}
-static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
+static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 val;
@@ -562,7 +562,7 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
+ ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
if (ret) {
DRM_DEV_ERROR(&pll_10nm->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
@@ -1005,10 +1005,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
.pll_init = dsi_pll_10nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_10nm_save_state,
- .restore_state = dsi_pll_10nm_restore_state,
+ .save_state = dsi_10nm_save_state,
+ .restore_state = dsi_10nm_restore_state,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
@@ -1029,10 +1027,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable,
.pll_init = dsi_pll_10nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_10nm_save_state,
- .restore_state = dsi_pll_10nm_restore_state,
+ .save_state = dsi_10nm_save_state,
+ .restore_state = dsi_10nm_restore_state,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 91c5bb2fd169..c7c462bfe96d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -795,9 +795,9 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
* PLL Callbacks
*/
-static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
+static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
u32 data;
@@ -810,18 +810,18 @@ static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
DBG("DSI%d PLL save state %x %x", pll_14nm->id,
cached_state->n1postdiv, cached_state->n2postdiv);
- cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
+ cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
}
-static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll)
+static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
u32 data;
int ret;
- ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw,
+ ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_14nm->pdev->dev,
@@ -1166,10 +1166,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_14nm_save_state,
- .restore_state = dsi_pll_14nm_restore_state,
+ .save_state = dsi_14nm_save_state,
+ .restore_state = dsi_14nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -1190,10 +1188,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_14nm_save_state,
- .restore_state = dsi_pll_14nm_restore_state,
+ .save_state = dsi_14nm_save_state,
+ .restore_state = dsi_14nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 20b31398b540..bfd110eb25fc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -470,9 +470,9 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
* PLL Callbacks
*/
-static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
+static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
@@ -481,20 +481,20 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
cached_state->postdiv1 =
pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
- if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw))
- cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
+ if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw))
+ cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
else
cached_state->vco_rate = 0;
}
-static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
+static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
int ret;
- ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
+ ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_28nm->pdev->dev,
@@ -527,7 +527,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
DBG("%d", pll_28nm->id);
- if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP)
+ if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
else
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
@@ -783,10 +783,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
.pll_init = dsi_pll_28nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_28nm_save_state,
- .restore_state = dsi_pll_28nm_restore_state,
+ .save_state = dsi_28nm_save_state,
+ .restore_state = dsi_28nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -807,10 +805,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
.pll_init = dsi_pll_28nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_28nm_save_state,
- .restore_state = dsi_pll_28nm_restore_state,
+ .save_state = dsi_28nm_save_state,
+ .restore_state = dsi_28nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -831,10 +827,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
.pll_init = dsi_pll_28nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_28nm_save_state,
- .restore_state = dsi_pll_28nm_restore_state,
+ .save_state = dsi_28nm_save_state,
+ .restore_state = dsi_28nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 952444e3e8f0..c71c5f07666d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -334,9 +334,9 @@ static const struct clk_ops clk_bytediv_ops = {
/*
* PLL Callbacks
*/
-static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
+static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
@@ -347,17 +347,17 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
cached_state->postdiv1 =
pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
- cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
+ cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
}
-static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
+static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
int ret;
- ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
+ ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_28nm->pdev->dev,
@@ -662,10 +662,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
.pll_init = dsi_pll_28nm_8960_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_28nm_save_state,
- .restore_state = dsi_pll_28nm_restore_state,
+ .save_state = dsi_28nm_save_state,
+ .restore_state = dsi_28nm_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index f760904efac9..015e099d7b7f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -543,9 +543,9 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
* PLL Callbacks
*/
-static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll)
+static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
@@ -566,9 +566,9 @@ static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll)
cached->pix_clk_div, cached->pll_mux);
}
-static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
+static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 val;
@@ -587,7 +587,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
+ ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
if (ret) {
DRM_DEV_ERROR(&pll_7nm->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
@@ -1038,10 +1038,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
.pll_init = dsi_pll_7nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_7nm_save_state,
- .restore_state = dsi_pll_7nm_restore_state,
+ .save_state = dsi_7nm_save_state,
+ .restore_state = dsi_7nm_restore_state,
},
.min_pll_rate = 600000000UL,
.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
@@ -1063,10 +1061,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
.pll_init = dsi_pll_7nm_init,
- },
- .pll_ops = {
- .save_state = dsi_pll_7nm_save_state,
- .restore_state = dsi_pll_7nm_restore_state,
+ .save_state = dsi_7nm_save_state,
+ .restore_state = dsi_7nm_restore_state,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy
2021-03-27 11:02 ` [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov
@ 2021-03-30 3:09 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie, freedreno,
linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Make save_state/restore callbacks accept struct msm_dsi_phy rather than
> struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
> us to drop struct msm_dsi_pll_ops.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 12 +++----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 22 +++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 24 ++++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 34 ++++++++-----------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 18 +++++-----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 22 +++++-------
> 7 files changed, 60 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 176930800082..f21f3babec68 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -858,9 +858,9 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy
> *phy,
>
> void msm_dsi_phy_save_state(struct msm_dsi_phy *phy)
> {
> - if (phy->cfg->pll_ops.save_state) {
> - phy->cfg->pll_ops.save_state(phy->pll);
> - phy->pll->state_saved = true;
> + if (phy->cfg->ops.save_state) {
> + phy->cfg->ops.save_state(phy);
> + phy->state_saved = true;
> }
> }
>
> @@ -868,12 +868,12 @@ int msm_dsi_phy_restore_state(struct msm_dsi_phy
> *phy)
> {
> int ret;
>
> - if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) {
> - ret = phy->cfg->pll_ops.restore_state(phy->pll);
> + if (phy->cfg->ops.restore_state && phy->state_saved) {
> + ret = phy->cfg->ops.restore_state(phy);
> if (ret)
> return ret;
>
> - phy->pll->state_saved = false;
> + phy->state_saved = false;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index b477d21804c8..fa09f4c2c071 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -17,7 +17,6 @@
> struct msm_dsi_pll {
> struct clk_hw clk_hw;
> bool pll_on;
> - bool state_saved;
>
> const struct msm_dsi_phy_cfg *cfg;
> };
> @@ -29,17 +28,13 @@ struct msm_dsi_phy_ops {
> int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
> struct msm_dsi_phy_clk_request *clk_req);
> void (*disable)(struct msm_dsi_phy *phy);
> -};
> -
> -struct msm_dsi_pll_ops {
> - void (*save_state)(struct msm_dsi_pll *pll);
> - int (*restore_state)(struct msm_dsi_pll *pll);
> + void (*save_state)(struct msm_dsi_phy *phy);
> + int (*restore_state)(struct msm_dsi_phy *phy);
I think that naming these save_pll_state/restore_pll_state would be more
appropriate.
> };
>
> struct msm_dsi_phy_cfg {
> struct dsi_reg_config reg_cfg;
> struct msm_dsi_phy_ops ops;
> - const struct msm_dsi_pll_ops pll_ops;
>
> unsigned long min_pll_rate;
> unsigned long max_pll_rate;
> @@ -115,6 +110,8 @@ struct msm_dsi_phy {
> struct msm_dsi_pll *pll;
>
> struct clk_hw_onecell_data *provided_clocks;
> +
> + bool state_saved;
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index bfb96d87d1d7..25fd4d860c4d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -518,9 +518,9 @@ static const struct clk_ops
> clk_ops_dsi_pll_10nm_vco = {
> * PLL Callbacks
> */
>
> -static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll)
> +static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
> @@ -541,9 +541,9 @@ static void dsi_pll_10nm_save_state(struct
> msm_dsi_pll *pll)
> cached->pix_clk_div, cached->pll_mux);
> }
>
> -static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
> +static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> u32 val;
> @@ -562,7 +562,7 @@ static int dsi_pll_10nm_restore_state(struct
> msm_dsi_pll *pll)
> val |= cached->pll_mux;
> pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> + ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> if (ret) {
> DRM_DEV_ERROR(&pll_10nm->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> @@ -1005,10 +1005,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =
> {
> .enable = dsi_10nm_phy_enable,
> .disable = dsi_10nm_phy_disable,
> .pll_init = dsi_pll_10nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_10nm_save_state,
> - .restore_state = dsi_pll_10nm_restore_state,
> + .save_state = dsi_10nm_save_state,
> + .restore_state = dsi_10nm_restore_state,
> },
> .min_pll_rate = 1000000000UL,
> .max_pll_rate = 3500000000UL,
> @@ -1029,10 +1027,8 @@ const struct msm_dsi_phy_cfg
> dsi_phy_10nm_8998_cfgs = {
> .enable = dsi_10nm_phy_enable,
> .disable = dsi_10nm_phy_disable,
> .pll_init = dsi_pll_10nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_10nm_save_state,
> - .restore_state = dsi_pll_10nm_restore_state,
> + .save_state = dsi_10nm_save_state,
> + .restore_state = dsi_10nm_restore_state,
> },
> .min_pll_rate = 1000000000UL,
> .max_pll_rate = 3500000000UL,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 91c5bb2fd169..c7c462bfe96d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -795,9 +795,9 @@ static const struct clk_ops
> clk_ops_dsi_pll_14nm_postdiv = {
> * PLL Callbacks
> */
>
> -static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
> +static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> u32 data;
> @@ -810,18 +810,18 @@ static void dsi_pll_14nm_save_state(struct
> msm_dsi_pll *pll)
> DBG("DSI%d PLL save state %x %x", pll_14nm->id,
> cached_state->n1postdiv, cached_state->n2postdiv);
>
> - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
> + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> }
>
> -static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll)
> +static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> u32 data;
> int ret;
>
> - ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw,
> + ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_14nm->pdev->dev,
> @@ -1166,10 +1166,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =
> {
> .enable = dsi_14nm_phy_enable,
> .disable = dsi_14nm_phy_disable,
> .pll_init = dsi_pll_14nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_14nm_save_state,
> - .restore_state = dsi_pll_14nm_restore_state,
> + .save_state = dsi_14nm_save_state,
Similarly even for the respective PLL API names,
dsi_14nm_pll_save_state/dsi_14nm_pll_restore_state will be better.
> + .restore_state = dsi_14nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -1190,10 +1188,8 @@ const struct msm_dsi_phy_cfg
> dsi_phy_14nm_660_cfgs = {
> .enable = dsi_14nm_phy_enable,
> .disable = dsi_14nm_phy_disable,
> .pll_init = dsi_pll_14nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_14nm_save_state,
> - .restore_state = dsi_pll_14nm_restore_state,
> + .save_state = dsi_14nm_save_state,
> + .restore_state = dsi_14nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 20b31398b540..bfd110eb25fc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -470,9 +470,9 @@ static const struct clk_ops
> clk_ops_dsi_pll_28nm_vco_lp = {
> * PLL Callbacks
> */
>
> -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
> +static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
>
> @@ -481,20 +481,20 @@ static void dsi_pll_28nm_save_state(struct
> msm_dsi_pll *pll)
> cached_state->postdiv1 =
> pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
> cached_state->byte_mux = pll_read(base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG);
> - if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw))
> - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
> + if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw))
> + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> else
> cached_state->vco_rate = 0;
> }
>
> -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
> +static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
> int ret;
>
> - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
> + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> @@ -527,7 +527,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>
> DBG("%d", pll_28nm->id);
>
> - if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP)
> + if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> else
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
> @@ -783,10 +783,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
> = {
> .enable = dsi_28nm_phy_enable,
> .disable = dsi_28nm_phy_disable,
> .pll_init = dsi_pll_28nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_28nm_save_state,
> - .restore_state = dsi_pll_28nm_restore_state,
> + .save_state = dsi_28nm_save_state,
> + .restore_state = dsi_28nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -807,10 +805,8 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_hpm_famb_cfgs = {
> .enable = dsi_28nm_phy_enable,
> .disable = dsi_28nm_phy_disable,
> .pll_init = dsi_pll_28nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_28nm_save_state,
> - .restore_state = dsi_pll_28nm_restore_state,
> + .save_state = dsi_28nm_save_state,
> + .restore_state = dsi_28nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> @@ -831,10 +827,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs
> = {
> .enable = dsi_28nm_phy_enable,
> .disable = dsi_28nm_phy_disable,
> .pll_init = dsi_pll_28nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_28nm_save_state,
> - .restore_state = dsi_pll_28nm_restore_state,
> + .save_state = dsi_28nm_save_state,
> + .restore_state = dsi_28nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 952444e3e8f0..c71c5f07666d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -334,9 +334,9 @@ static const struct clk_ops clk_bytediv_ops = {
> /*
> * PLL Callbacks
> */
> -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
> +static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
>
> @@ -347,17 +347,17 @@ static void dsi_pll_28nm_save_state(struct
> msm_dsi_pll *pll)
> cached_state->postdiv1 =
> pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
>
> - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
> + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> }
>
> -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
> +static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
> int ret;
>
> - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
> + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> @@ -662,10 +662,8 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_8960_cfgs = {
> .enable = dsi_28nm_phy_enable,
> .disable = dsi_28nm_phy_disable,
> .pll_init = dsi_pll_28nm_8960_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_28nm_save_state,
> - .restore_state = dsi_pll_28nm_restore_state,
> + .save_state = dsi_28nm_save_state,
> + .restore_state = dsi_28nm_restore_state,
> },
> .min_pll_rate = VCO_MIN_RATE,
> .max_pll_rate = VCO_MAX_RATE,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index f760904efac9..015e099d7b7f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -543,9 +543,9 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco
> = {
> * PLL Callbacks
> */
>
> -static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll)
> +static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
> @@ -566,9 +566,9 @@ static void dsi_pll_7nm_save_state(struct
> msm_dsi_pll *pll)
> cached->pix_clk_div, cached->pll_mux);
> }
>
> -static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
> +static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> u32 val;
> @@ -587,7 +587,7 @@ static int dsi_pll_7nm_restore_state(struct
> msm_dsi_pll *pll)
> val |= cached->pll_mux;
> pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> + ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
Can you double check the char length on this line? Wouldnt this exceed
100chars?
similarly other dsi_pll_**_vco_set_rates might too
> if (ret) {
> DRM_DEV_ERROR(&pll_7nm->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> @@ -1038,10 +1038,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs =
> {
> .enable = dsi_7nm_phy_enable,
> .disable = dsi_7nm_phy_disable,
> .pll_init = dsi_pll_7nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_7nm_save_state,
> - .restore_state = dsi_pll_7nm_restore_state,
> + .save_state = dsi_7nm_save_state,
> + .restore_state = dsi_7nm_restore_state,
> },
> .min_pll_rate = 600000000UL,
> .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL :
> ULONG_MAX,
> @@ -1063,10 +1061,8 @@ const struct msm_dsi_phy_cfg
> dsi_phy_7nm_8150_cfgs = {
> .enable = dsi_7nm_phy_enable,
> .disable = dsi_7nm_phy_disable,
> .pll_init = dsi_pll_7nm_init,
> - },
> - .pll_ops = {
> - .save_state = dsi_pll_7nm_save_state,
> - .restore_state = dsi_pll_7nm_restore_state,
> + .save_state = dsi_7nm_save_state,
> + .restore_state = dsi_7nm_restore_state,
> },
> .min_pll_rate = 1000000000UL,
> .max_pll_rate = 3500000000UL,
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (16 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov
@ 2021-03-27 11:02 ` Dmitry Baryshkov
2021-03-30 3:13 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov
` (6 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:02 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
directly into struct msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/Kconfig | 8 --
drivers/gpu/drm/msm/Makefile | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 36 +++++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 66 ++++++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 78 ++++++++---------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 83 ++++++++++---------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 65 ++++++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 74 +++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 23 -----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 44 ----------
10 files changed, 221 insertions(+), 258 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index dabb4a1ccdcf..1f0b3f0e7149 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -76,14 +76,6 @@ config DRM_MSM_DSI
Choose this option if you have a need for MIPI DSI connector
support.
-config DRM_MSM_DSI_PLL
- bool "Enable DSI PLL driver in MSM DRM"
- depends on DRM_MSM_DSI && COMMON_CLK
- default y
- help
- Choose this option to enable DSI PLL driver which provides DSI
- source clocks under common clock framework.
-
config DRM_MSM_DSI_28NM_PHY
bool "Enable DSI 28nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 1be6996b80b7..610d630326bb 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -136,6 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
-msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o
-
obj-$(CONFIG_DRM_MSM) += msm.o
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index fa09f4c2c071..4fe410c97d3a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -7,6 +7,7 @@
#define __DSI_PHY_H__
#include <linux/clk-provider.h>
+#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include "dsi.h"
@@ -14,15 +15,6 @@
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-struct msm_dsi_pll {
- struct clk_hw clk_hw;
- bool pll_on;
-
- const struct msm_dsi_phy_cfg *cfg;
-};
-
-#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
-
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
@@ -107,7 +99,8 @@ struct msm_dsi_phy {
enum msm_dsi_phy_usecase usecase;
bool regulator_ldo_mode;
- struct msm_dsi_pll *pll;
+ struct clk_hw *vco_hw;
+ bool pll_on;
struct clk_hw_onecell_data *provided_clocks;
@@ -127,6 +120,27 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask);
+/* PLL accessors */
+static inline void pll_write(void __iomem *reg, u32 data)
+{
+ msm_writel(data, reg);
+}
+
+static inline u32 pll_read(const void __iomem *reg)
+{
+ return msm_readl(reg);
+}
+
+static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
+{
+ pll_write(reg, data);
+ udelay(delay_us);
+}
+
+static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
+{
+ pll_write((reg), data);
+ ndelay(delay_ns);
+}
#endif /* __DSI_PHY_H__ */
-
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 25fd4d860c4d..dec9beadddaa 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -7,7 +7,6 @@
#include <linux/clk-provider.h>
#include <linux/iopoll.h>
-#include "dsi_pll.h"
#include "dsi_phy.h"
#include "dsi.xml.h"
@@ -85,11 +84,13 @@ struct pll_10nm_cached_state {
};
struct dsi_pll_10nm {
- struct msm_dsi_pll base;
+ struct clk_hw clk_hw;
int id;
struct platform_device *pdev;
+ struct msm_dsi_phy *phy;
+
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
@@ -104,11 +105,10 @@ struct dsi_pll_10nm {
struct pll_10nm_cached_state cached_state;
- enum msm_dsi_phy_usecase uc;
struct dsi_pll_10nm *slave;
};
-#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base)
+#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw)
/*
* Global list of private DSI PLL struct pointers. We need this for Dual DSI
@@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll)
static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
parent_rate);
@@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
struct device *dev = &pll_10nm->pdev->dev;
int rc;
@@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
goto error;
}
- pll->pll_on = true;
+ pll_10nm->phy->pll_on = true;
dsi_pll_enable_global_clk(pll_10nm);
if (pll_10nm->slave)
@@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
/*
* To avoid any stray glitches while abruptly powering down the PLL
@@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
}
/* flush, ensure all register writes are done */
wmb();
- pll->pll_on = false;
+ pll_10nm->phy->pll_on = false;
}
static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
struct dsi_pll_config *config = &pll_10nm->pll_configuration;
void __iomem *base = pll_10nm->mmio;
u64 ref_clk = pll_10nm->vco_ref_clk_rate;
@@ -506,8 +502,21 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
return (unsigned long)vco_rate;
}
+static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *parent_rate)
+{
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
+
+ if (rate < pll_10nm->phy->cfg->min_pll_rate)
+ return pll_10nm->phy->cfg->min_pll_rate;
+ else if (rate > pll_10nm->phy->cfg->max_pll_rate)
+ return pll_10nm->phy->cfg->max_pll_rate;
+ else
+ return rate;
+}
+
static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_10nm_clk_round_rate,
.set_rate = dsi_pll_10nm_vco_set_rate,
.recalc_rate = dsi_pll_10nm_vco_recalc_rate,
.prepare = dsi_pll_10nm_vco_prepare,
@@ -520,7 +529,7 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
@@ -543,7 +552,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 val;
@@ -562,7 +571,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
+ ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
if (ret) {
DRM_DEV_ERROR(&pll_10nm->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
@@ -574,16 +583,15 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
return 0;
}
-static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc)
+static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+ struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
void __iomem *base = pll_10nm->phy_cmn_mmio;
u32 data = 0x0; /* internal PLL */
DBG("DSI PLL%d", pll_10nm->id);
- switch (uc) {
+ switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
break;
case MSM_DSI_PHY_MASTER:
@@ -599,8 +607,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
/* set PLL src */
pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
- pll_10nm->uc = uc;
-
return 0;
}
@@ -628,9 +634,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
DBG("DSI%d", pll_10nm->id);
snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
- pll_10nm->base.clk_hw.init = &vco_init;
+ pll_10nm->clk_hw.init = &vco_init;
- ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
if (ret)
return ret;
@@ -740,7 +746,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
struct platform_device *pdev = phy->pdev;
int id = phy->id;
struct dsi_pll_10nm *pll_10nm;
- struct msm_dsi_pll *pll;
int ret;
pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
@@ -767,8 +772,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_10nm->postdiv_lock);
- pll = &pll_10nm->base;
- pll->cfg = phy->cfg;
+ pll_10nm->phy = phy;
ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
if (ret) {
@@ -776,7 +780,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
return ret;
}
- phy->pll = pll;
+ phy->vco_hw = &pll_10nm->clk_hw;
/* TODO: Remove this when we have proper display handover support */
msm_dsi_phy_save_state(phy);
@@ -951,7 +955,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
/* Select full-rate mode */
dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
- ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_10nm_set_usecase(phy);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index c7c462bfe96d..86f9aedd790f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -8,7 +8,6 @@
#include <linux/delay.h>
#include "dsi_phy.h"
-#include "dsi_pll.h"
#include "dsi.xml.h"
#define PHY_14NM_CKLN_IDX 4
@@ -114,7 +113,7 @@ struct pll_14nm_cached_state {
};
struct dsi_pll_14nm {
- struct msm_dsi_pll base;
+ struct clk_hw clk_hw;
int id;
struct platform_device *pdev;
@@ -122,6 +121,8 @@ struct dsi_pll_14nm {
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
+ struct msm_dsi_phy *phy;
+
struct dsi_pll_input in;
struct dsi_pll_output out;
@@ -133,11 +134,10 @@ struct dsi_pll_14nm {
struct pll_14nm_cached_state cached_state;
- enum msm_dsi_phy_usecase uc;
struct dsi_pll_14nm *slave;
};
-#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
+#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw)
/*
* Private struct for N1/N2 post-divider clocks. These clocks are similar to
@@ -564,8 +564,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
struct dsi_pll_input *pin = &pll_14nm->in;
struct dsi_pll_output *pout = &pll_14nm->out;
@@ -600,7 +599,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
* don't lock the slave PLL. We just ensure that the PLL/PHY registers
* of the master and slave are identical
*/
- if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
+ if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
pll_db_commit_14nm(pll_14nm_slave, pin, pout);
@@ -614,8 +613,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *base = pll_14nm->mmio;
u64 vco_rate, multiplier = BIT(20);
u32 div_frac_start;
@@ -654,15 +652,14 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *base = pll_14nm->mmio;
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
bool locked;
DBG("");
- if (unlikely(pll->pll_on))
+ if (unlikely(pll_14nm->phy->pll_on))
return 0;
pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
@@ -677,29 +674,41 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
}
DBG("DSI PLL lock success");
- pll->pll_on = true;
+ pll_14nm->phy->pll_on = true;
return 0;
}
static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
DBG("");
- if (unlikely(!pll->pll_on))
+ if (unlikely(!pll_14nm->phy->pll_on))
return;
pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
- pll->pll_on = false;
+ pll_14nm->phy->pll_on = false;
+}
+
+static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *parent_rate)
+{
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
+
+ if (rate < pll_14nm->phy->cfg->min_pll_rate)
+ return pll_14nm->phy->cfg->min_pll_rate;
+ else if (rate > pll_14nm->phy->cfg->max_pll_rate)
+ return pll_14nm->phy->cfg->max_pll_rate;
+ else
+ return rate;
}
static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_14nm_clk_round_rate,
.set_rate = dsi_pll_14nm_vco_set_rate,
.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
.prepare = dsi_pll_14nm_vco_prepare,
@@ -773,7 +782,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
/* If we're master in dual DSI mode, then the slave PLL's post-dividers
* follow the master's post dividers
*/
- if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
+ if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
@@ -797,7 +806,7 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
u32 data;
@@ -810,18 +819,18 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
DBG("DSI%d PLL save state %x %x", pll_14nm->id,
cached_state->n1postdiv, cached_state->n2postdiv);
- cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
+ cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
}
static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
u32 data;
int ret;
- ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
+ ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_14nm->pdev->dev,
@@ -837,7 +846,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
/* also restore post-dividers for slave DSI PLL */
- if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
+ if (phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
@@ -847,14 +856,13 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
return 0;
}
-static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc)
+static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
void __iomem *base = pll_14nm->mmio;
u32 clkbuflr_en, bandgap = 0;
- switch (uc) {
+ switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
clkbuflr_en = 0x1;
break;
@@ -874,8 +882,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
if (bandgap)
pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
- pll_14nm->uc = uc;
-
return 0;
}
@@ -932,9 +938,9 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
DBG("DSI%d", pll_14nm->id);
snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
- pll_14nm->base.clk_hw.init = &vco_init;
+ pll_14nm->clk_hw.init = &vco_init;
- ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
if (ret)
return ret;
@@ -990,7 +996,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
struct platform_device *pdev = phy->pdev;
int id = phy->id;
struct dsi_pll_14nm *pll_14nm;
- struct msm_dsi_pll *pll;
int ret;
if (!pdev)
@@ -1020,8 +1025,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_14nm->postdiv_lock);
- pll = &pll_14nm->base;
- pll->cfg = phy->cfg;
+ pll_14nm->phy = phy;
ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
if (ret) {
@@ -1029,7 +1033,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
return ret;
}
- phy->pll = pll;
+ phy->vco_hw = &pll_14nm->clk_hw;
return 0;
}
@@ -1131,7 +1135,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
- ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_14nm_set_usecase(phy);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index bfd110eb25fc..1b95ea75235c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -7,7 +7,6 @@
#include <linux/clk-provider.h>
#include "dsi_phy.h"
-#include "dsi_pll.h"
#include "dsi.xml.h"
/*
@@ -66,16 +65,19 @@ struct pll_28nm_cached_state {
};
struct dsi_pll_28nm {
- struct msm_dsi_pll base;
+ struct clk_hw clk_hw;
int id;
struct platform_device *pdev;
+
+ struct msm_dsi_phy *phy;
+
void __iomem *mmio;
struct pll_28nm_cached_state cached_state;
};
-#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
+#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
u32 nb_tries, u32 timeout_us)
@@ -116,8 +118,7 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
unsigned long div_fbx1000, gen_vco_clk;
@@ -210,7 +211,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
/* Add hardware recommended delay for correct PLL configuration */
- if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
+ if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
udelay(1000);
else
udelay(1);
@@ -233,8 +234,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
POLL_TIMEOUT_US);
@@ -243,8 +243,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
@@ -289,9 +288,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
-static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
+static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
u32 max_reads = 5, timeout_us = 100;
@@ -366,16 +364,16 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
int i, ret;
- if (unlikely(pll->pll_on))
+ if (unlikely(pll_28nm->phy->pll_on))
return 0;
for (i = 0; i < 3; i++) {
- ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
+ ret = _dsi_pll_28nm_vco_prepare_hpm(pll_28nm);
if (!ret) {
- pll->pll_on = true;
+ pll_28nm->phy->pll_on = true;
return 0;
}
}
@@ -385,8 +383,7 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
bool locked;
@@ -395,7 +392,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
DBG("id=%d", pll_28nm->id);
- if (unlikely(pll->pll_on))
+ if (unlikely(pll_28nm->phy->pll_on))
return 0;
pll_28nm_software_reset(pll_28nm);
@@ -428,28 +425,40 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
}
DBG("DSI PLL lock success");
- pll->pll_on = true;
+ pll_28nm->phy->pll_on = true;
return 0;
}
static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
DBG("id=%d", pll_28nm->id);
- if (unlikely(!pll->pll_on))
+ if (unlikely(!pll_28nm->phy->pll_on))
return;
pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
- pll->pll_on = false;
+ pll_28nm->phy->pll_on = false;
+}
+
+static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *parent_rate)
+{
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
+
+ if (rate < pll_28nm->phy->cfg->min_pll_rate)
+ return pll_28nm->phy->cfg->min_pll_rate;
+ else if (rate > pll_28nm->phy->cfg->max_pll_rate)
+ return pll_28nm->phy->cfg->max_pll_rate;
+ else
+ return rate;
}
static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_28nm_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
.prepare = dsi_pll_28nm_vco_prepare_hpm,
@@ -458,7 +467,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
};
static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_28nm_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
.prepare = dsi_pll_28nm_vco_prepare_lp,
@@ -472,7 +481,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
@@ -481,20 +490,20 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
cached_state->postdiv1 =
pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
- if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw))
- cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
+ if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
+ cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
else
cached_state->vco_rate = 0;
}
static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
int ret;
- ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
+ ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_28nm->pdev->dev,
@@ -527,14 +536,14 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
DBG("%d", pll_28nm->id);
- if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
+ if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
else
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
- pll_28nm->base.clk_hw.init = &vco_init;
- ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
+ pll_28nm->clk_hw.init = &vco_init;
+ ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
if (ret)
return ret;
@@ -593,7 +602,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
struct platform_device *pdev = phy->pdev;
int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
- struct msm_dsi_pll *pll;
int ret;
if (!pdev)
@@ -612,8 +620,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
return -ENOMEM;
}
- pll = &pll_28nm->base;
- pll->cfg = phy->cfg;
+ pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {
@@ -621,7 +628,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
return ret;
}
- phy->pll = pll;
+ phy->vco_hw = &pll_28nm->clk_hw;
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index c71c5f07666d..3e63a3b70818 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -7,7 +7,6 @@
#include <linux/delay.h>
#include "dsi_phy.h"
-#include "dsi_pll.h"
#include "dsi.xml.h"
/*
@@ -58,16 +57,19 @@ struct clk_bytediv {
};
struct dsi_pll_28nm {
- struct msm_dsi_pll base;
+ struct clk_hw clk_hw;
int id;
struct platform_device *pdev;
+
+ struct msm_dsi_phy *phy;
+
void __iomem *mmio;
struct pll_28nm_cached_state cached_state;
};
-#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
+#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
int nb_tries, int timeout_us)
@@ -95,8 +97,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
void __iomem *base = pll_28nm->mmio;
u32 val, temp, fb_divider;
@@ -136,8 +137,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
POLL_TIMEOUT_US);
@@ -146,8 +146,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
void __iomem *base = pll_28nm->mmio;
unsigned long vco_rate;
u32 status, fb_divider, temp, ref_divider;
@@ -180,8 +179,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
bool locked;
@@ -191,7 +189,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
DBG("id=%d", pll_28nm->id);
- if (unlikely(pll->pll_on))
+ if (unlikely(pll_28nm->phy->pll_on))
return 0;
/*
@@ -222,28 +220,40 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
}
DBG("DSI PLL lock success");
- pll->pll_on = true;
+ pll_28nm->phy->pll_on = true;
return 0;
}
static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
DBG("id=%d", pll_28nm->id);
- if (unlikely(!pll->pll_on))
+ if (unlikely(!pll_28nm->phy->pll_on))
return;
pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
- pll->pll_on = false;
+ pll_28nm->phy->pll_on = false;
+}
+
+static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *parent_rate)
+{
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
+
+ if (rate < pll_28nm->phy->cfg->min_pll_rate)
+ return pll_28nm->phy->cfg->min_pll_rate;
+ else if (rate > pll_28nm->phy->cfg->max_pll_rate)
+ return pll_28nm->phy->cfg->max_pll_rate;
+ else
+ return rate;
}
static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_28nm_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
.prepare = dsi_pll_28nm_vco_prepare,
@@ -336,7 +346,7 @@ static const struct clk_ops clk_bytediv_ops = {
*/
static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
@@ -347,17 +357,17 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
cached_state->postdiv1 =
pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
- cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
+ cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
}
static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
void __iomem *base = pll_28nm->mmio;
int ret;
- ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
+ ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_28nm->pdev->dev,
@@ -407,9 +417,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
vco_init.name = vco_name;
- pll_28nm->base.clk_hw.init = &vco_init;
+ pll_28nm->clk_hw.init = &vco_init;
- ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
if (ret)
return ret;
@@ -450,7 +460,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
struct platform_device *pdev = phy->pdev;
int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
- struct msm_dsi_pll *pll;
int ret;
if (!pdev)
@@ -469,9 +478,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
return -ENOMEM;
}
- pll = &pll_28nm->base;
-
- pll->cfg = phy->cfg;
+ pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {
@@ -479,7 +486,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
return ret;
}
- phy->pll = pll;
+ phy->vco_hw = &pll_28nm->clk_hw;
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 015e099d7b7f..c922e46f5241 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -7,7 +7,6 @@
#include <linux/clk-provider.h>
#include <linux/iopoll.h>
-#include "dsi_pll.h"
#include "dsi_phy.h"
#include "dsi.xml.h"
@@ -85,11 +84,13 @@ struct pll_7nm_cached_state {
};
struct dsi_pll_7nm {
- struct msm_dsi_pll base;
+ struct clk_hw clk_hw;
int id;
struct platform_device *pdev;
+ struct msm_dsi_phy *phy;
+
void __iomem *phy_cmn_mmio;
void __iomem *mmio;
@@ -104,11 +105,10 @@ struct dsi_pll_7nm {
struct pll_7nm_cached_state cached_state;
- enum msm_dsi_phy_usecase uc;
struct dsi_pll_7nm *slave;
};
-#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base)
+#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
/*
* Global list of private DSI PLL struct pointers. We need this for Dual DSI
@@ -164,7 +164,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
dec = div_u64(dec_multiple, multiplier);
- if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
+ if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
regs->pll_clock_inverters = 0x28;
else if (pll_freq <= 1000000000ULL)
regs->pll_clock_inverters = 0xa0;
@@ -259,7 +259,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
void __iomem *base = pll->mmio;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
- if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
if (pll->vco_current_rate >= 3100000000ULL)
analog_controls_five_1 = 0x03;
@@ -293,9 +293,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
- pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
+ pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
- if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
@@ -321,8 +321,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll)
static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
parent_rate);
@@ -420,8 +419,7 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
int rc;
dsi_pll_enable_pll_bias(pll_7nm);
@@ -444,7 +442,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
goto error;
}
- pll->pll_on = true;
+ pll_7nm->phy->pll_on = true;
/*
* assert power on reset for PHY digital in case the PLL is
@@ -471,8 +469,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
/*
* To avoid any stray glitches while abruptly powering down the PLL
@@ -488,14 +485,13 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
}
/* flush, ensure all register writes are done */
wmb();
- pll->pll_on = false;
+ pll_7nm->phy->pll_on = false;
}
static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
struct dsi_pll_config *config = &pll_7nm->pll_configuration;
void __iomem *base = pll_7nm->mmio;
u64 ref_clk = pll_7nm->vco_ref_clk_rate;
@@ -531,8 +527,21 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
return (unsigned long)vco_rate;
}
+static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *parent_rate)
+{
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
+
+ if (rate < pll_7nm->phy->cfg->min_pll_rate)
+ return pll_7nm->phy->cfg->min_pll_rate;
+ else if (rate > pll_7nm->phy->cfg->max_pll_rate)
+ return pll_7nm->phy->cfg->max_pll_rate;
+ else
+ return rate;
+}
+
static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .round_rate = dsi_pll_7nm_clk_round_rate,
.set_rate = dsi_pll_7nm_vco_set_rate,
.recalc_rate = dsi_pll_7nm_vco_recalc_rate,
.prepare = dsi_pll_7nm_vco_prepare,
@@ -545,7 +554,7 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
@@ -568,7 +577,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 val;
@@ -587,7 +596,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
+ ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
if (ret) {
DRM_DEV_ERROR(&pll_7nm->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
@@ -599,16 +608,15 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
return 0;
}
-static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
- enum msm_dsi_phy_usecase uc)
+static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
{
- struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
void __iomem *base = pll_7nm->phy_cmn_mmio;
u32 data = 0x0; /* internal PLL */
DBG("DSI PLL%d", pll_7nm->id);
- switch (uc) {
+ switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
break;
case MSM_DSI_PHY_MASTER:
@@ -624,8 +632,6 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
/* set PLL src */
pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
- pll_7nm->uc = uc;
-
return 0;
}
@@ -653,9 +659,9 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
DBG("DSI%d", pll_7nm->id);
snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
- pll_7nm->base.clk_hw.init = &vco_init;
+ pll_7nm->clk_hw.init = &vco_init;
- ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
if (ret)
return ret;
@@ -765,7 +771,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
struct platform_device *pdev = phy->pdev;
int id = phy->id;
struct dsi_pll_7nm *pll_7nm;
- struct msm_dsi_pll *pll;
int ret;
pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
@@ -792,8 +797,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_7nm->postdiv_lock);
- pll = &pll_7nm->base;
- pll->cfg = phy->cfg;
+ pll_7nm->phy = phy;
ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
if (ret) {
@@ -801,7 +805,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
return ret;
}
- phy->pll = pll;
+ phy->vco_hw = &pll_7nm->clk_hw;
/* TODO: Remove this when we have proper display handover support */
msm_dsi_phy_save_state(phy);
@@ -966,7 +970,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
/* Select full-rate mode */
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
- ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase);
+ ret = dsi_7nm_set_usecase(phy);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
deleted file mode 100644
index cae668b669a4..000000000000
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
- */
-
-#include "dsi_phy.h"
-#include "dsi_pll.h"
-
-/*
- * DSI PLL Helper functions
- */
-long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
- unsigned long rate, unsigned long *parent_rate)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-
- if (rate < pll->cfg->min_pll_rate)
- return pll->cfg->min_pll_rate;
- else if (rate > pll->cfg->max_pll_rate)
- return pll->cfg->max_pll_rate;
- else
- return rate;
-}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
deleted file mode 100644
index da83e4c11f4f..000000000000
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DSI_PLL_H__
-#define __DSI_PLL_H__
-
-#include <linux/delay.h>
-
-#include "dsi.h"
-
-static inline void pll_write(void __iomem *reg, u32 data)
-{
- msm_writel(data, reg);
-}
-
-static inline u32 pll_read(const void __iomem *reg)
-{
- return msm_readl(reg);
-}
-
-static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
-{
- pll_write(reg, data);
- udelay(delay_us);
-}
-
-static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
-{
- pll_write((reg), data);
- ndelay(delay_ns);
-}
-
-/*
- * DSI PLL Helper functions
- */
-
-/* clock callbacks */
-long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
- unsigned long rate, unsigned long *parent_rate);
-
-#endif /* __DSI_PLL_H__ */
-
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton
2021-03-27 11:02 ` [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov
@ 2021-03-30 3:13 ` abhinavk
2021-03-30 3:35 ` abhinavk
0 siblings, 1 reply; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:13 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
> directly into struct msm_dsi_phy.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/Kconfig | 8 --
> drivers/gpu/drm/msm/Makefile | 2 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 36 +++++---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 66 ++++++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 78 ++++++++---------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 83 ++++++++++---------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 65 ++++++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 74 +++++++++--------
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 23 -----
> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 44 ----------
> 10 files changed, 221 insertions(+), 258 deletions(-)
> delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
>
> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> index dabb4a1ccdcf..1f0b3f0e7149 100644
> --- a/drivers/gpu/drm/msm/Kconfig
> +++ b/drivers/gpu/drm/msm/Kconfig
> @@ -76,14 +76,6 @@ config DRM_MSM_DSI
> Choose this option if you have a need for MIPI DSI connector
> support.
>
> -config DRM_MSM_DSI_PLL
> - bool "Enable DSI PLL driver in MSM DRM"
> - depends on DRM_MSM_DSI && COMMON_CLK
> - default y
> - help
> - Choose this option to enable DSI PLL driver which provides DSI
> - source clocks under common clock framework.
> -
> config DRM_MSM_DSI_28NM_PHY
> bool "Enable DSI 28nm PHY driver in MSM DRM"
> depends on DRM_MSM_DSI
> diff --git a/drivers/gpu/drm/msm/Makefile
> b/drivers/gpu/drm/msm/Makefile
> index 1be6996b80b7..610d630326bb 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -136,6 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) +=
> dsi/phy/dsi_phy_14nm.o
> msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
> msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
>
> -msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o
> -
> obj-$(CONFIG_DRM_MSM) += msm.o
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index fa09f4c2c071..4fe410c97d3a 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -7,6 +7,7 @@
> #define __DSI_PHY_H__
>
> #include <linux/clk-provider.h>
> +#include <linux/delay.h>
> #include <linux/regulator/consumer.h>
>
> #include "dsi.h"
> @@ -14,15 +15,6 @@
> #define dsi_phy_read(offset) msm_readl((offset))
> #define dsi_phy_write(offset, data) msm_writel((data), (offset))
>
> -struct msm_dsi_pll {
> - struct clk_hw clk_hw;
> - bool pll_on;
> -
> - const struct msm_dsi_phy_cfg *cfg;
> -};
> -
> -#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
> -
> struct msm_dsi_phy_ops {
> int (*pll_init)(struct msm_dsi_phy *phy);
> int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
> @@ -107,7 +99,8 @@ struct msm_dsi_phy {
> enum msm_dsi_phy_usecase usecase;
> bool regulator_ldo_mode;
>
> - struct msm_dsi_pll *pll;
> + struct clk_hw *vco_hw;
> + bool pll_on;
>
> struct clk_hw_onecell_data *provided_clocks;
>
> @@ -127,6 +120,27 @@ int msm_dsi_dphy_timing_calc_v4(struct
> msm_dsi_dphy_timing *timing,
> struct msm_dsi_phy_clk_request *clk_req);
> void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
> reg,
> u32 bit_mask);
> +/* PLL accessors */
> +static inline void pll_write(void __iomem *reg, u32 data)
> +{
> + msm_writel(data, reg);
> +}
> +
> +static inline u32 pll_read(const void __iomem *reg)
> +{
> + return msm_readl(reg);
> +}
> +
> +static inline void pll_write_udelay(void __iomem *reg, u32 data, u32
> delay_us)
> +{
> + pll_write(reg, data);
> + udelay(delay_us);
> +}
> +
> +static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32
> delay_ns)
> +{
> + pll_write((reg), data);
> + ndelay(delay_ns);
> +}
>
> #endif /* __DSI_PHY_H__ */
> -
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 25fd4d860c4d..dec9beadddaa 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -7,7 +7,6 @@
> #include <linux/clk-provider.h>
> #include <linux/iopoll.h>
>
> -#include "dsi_pll.h"
> #include "dsi_phy.h"
> #include "dsi.xml.h"
>
> @@ -85,11 +84,13 @@ struct pll_10nm_cached_state {
> };
>
> struct dsi_pll_10nm {
> - struct msm_dsi_pll base;
> + struct clk_hw clk_hw;
>
> int id;
> struct platform_device *pdev;
>
> + struct msm_dsi_phy *phy;
> +
> void __iomem *phy_cmn_mmio;
> void __iomem *mmio;
>
> @@ -104,11 +105,10 @@ struct dsi_pll_10nm {
>
> struct pll_10nm_cached_state cached_state;
>
> - enum msm_dsi_phy_usecase uc;
> struct dsi_pll_10nm *slave;
> };
>
> -#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base)
> +#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw)
>
> /*
> * Global list of private DSI PLL struct pointers. We need this for
> Dual DSI
> @@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm
> *pll)
> static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>
> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
> parent_rate);
> @@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct
> dsi_pll_10nm *pll)
>
> static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> struct device *dev = &pll_10nm->pdev->dev;
> int rc;
>
> @@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> goto error;
> }
>
> - pll->pll_on = true;
> + pll_10nm->phy->pll_on = true;
>
> dsi_pll_enable_global_clk(pll_10nm);
> if (pll_10nm->slave)
> @@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_10nm
> *pll)
>
> static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>
> /*
> * To avoid any stray glitches while abruptly powering down the PLL
> @@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct
> clk_hw *hw)
> }
> /* flush, ensure all register writes are done */
> wmb();
> - pll->pll_on = false;
> + pll_10nm->phy->pll_on = false;
> }
>
> static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> struct dsi_pll_config *config = &pll_10nm->pll_configuration;
> void __iomem *base = pll_10nm->mmio;
> u64 ref_clk = pll_10nm->vco_ref_clk_rate;
> @@ -506,8 +502,21 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> return (unsigned long)vco_rate;
> }
>
> +static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> +
> + if (rate < pll_10nm->phy->cfg->min_pll_rate)
> + return pll_10nm->phy->cfg->min_pll_rate;
> + else if (rate > pll_10nm->phy->cfg->max_pll_rate)
> + return pll_10nm->phy->cfg->max_pll_rate;
> + else
> + return rate;
> +}
> +
> static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_10nm_clk_round_rate,
> .set_rate = dsi_pll_10nm_vco_set_rate,
> .recalc_rate = dsi_pll_10nm_vco_recalc_rate,
> .prepare = dsi_pll_10nm_vco_prepare,
> @@ -520,7 +529,7 @@ static const struct clk_ops
> clk_ops_dsi_pll_10nm_vco = {
>
> static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
> @@ -543,7 +552,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy
> *phy)
>
> static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> u32 val;
> @@ -562,7 +571,7 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> val |= cached->pll_mux;
> pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> if (ret) {
> DRM_DEV_ERROR(&pll_10nm->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> @@ -574,16 +583,15 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> return 0;
> }
>
> -static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
> - enum msm_dsi_phy_usecase uc)
> +static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> void __iomem *base = pll_10nm->phy_cmn_mmio;
> u32 data = 0x0; /* internal PLL */
>
> DBG("DSI PLL%d", pll_10nm->id);
>
> - switch (uc) {
> + switch (phy->usecase) {
> case MSM_DSI_PHY_STANDALONE:
> break;
> case MSM_DSI_PHY_MASTER:
> @@ -599,8 +607,6 @@ static int dsi_pll_10nm_set_usecase(struct
> msm_dsi_pll *pll,
> /* set PLL src */
> pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
>
> - pll_10nm->uc = uc;
> -
> return 0;
> }
>
> @@ -628,9 +634,9 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> DBG("DSI%d", pll_10nm->id);
>
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
> - pll_10nm->base.clk_hw.init = &vco_init;
> + pll_10nm->clk_hw.init = &vco_init;
>
> - ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
> if (ret)
> return ret;
>
> @@ -740,7 +746,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> struct platform_device *pdev = phy->pdev;
> int id = phy->id;
> struct dsi_pll_10nm *pll_10nm;
> - struct msm_dsi_pll *pll;
> int ret;
>
> pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
> @@ -767,8 +772,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
>
> spin_lock_init(&pll_10nm->postdiv_lock);
>
> - pll = &pll_10nm->base;
> - pll->cfg = phy->cfg;
> + pll_10nm->phy = phy;
>
> ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
> if (ret) {
> @@ -776,7 +780,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> return ret;
> }
>
> - phy->pll = pll;
> + phy->vco_hw = &pll_10nm->clk_hw;
>
> /* TODO: Remove this when we have proper display handover support */
> msm_dsi_phy_save_state(phy);
> @@ -951,7 +955,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> /* Select full-rate mode */
> dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
>
> - ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
> + ret = dsi_10nm_set_usecase(phy);
> if (ret) {
> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
> __func__, ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index c7c462bfe96d..86f9aedd790f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -8,7 +8,6 @@
> #include <linux/delay.h>
>
> #include "dsi_phy.h"
> -#include "dsi_pll.h"
> #include "dsi.xml.h"
>
> #define PHY_14NM_CKLN_IDX 4
> @@ -114,7 +113,7 @@ struct pll_14nm_cached_state {
> };
>
> struct dsi_pll_14nm {
> - struct msm_dsi_pll base;
> + struct clk_hw clk_hw;
>
> int id;
> struct platform_device *pdev;
> @@ -122,6 +121,8 @@ struct dsi_pll_14nm {
> void __iomem *phy_cmn_mmio;
> void __iomem *mmio;
>
> + struct msm_dsi_phy *phy;
> +
> struct dsi_pll_input in;
> struct dsi_pll_output out;
>
> @@ -133,11 +134,10 @@ struct dsi_pll_14nm {
>
> struct pll_14nm_cached_state cached_state;
>
> - enum msm_dsi_phy_usecase uc;
> struct dsi_pll_14nm *slave;
> };
>
> -#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
> +#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw)
>
> /*
> * Private struct for N1/N2 post-divider clocks. These clocks are
> similar to
> @@ -564,8 +564,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm
> *pll,
> static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> struct dsi_pll_input *pin = &pll_14nm->in;
> struct dsi_pll_output *pout = &pll_14nm->out;
>
> @@ -600,7 +599,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
> * don't lock the slave PLL. We just ensure that the PLL/PHY
> registers
> * of the master and slave are identical
> */
> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
> + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>
> pll_db_commit_14nm(pll_14nm_slave, pin, pout);
> @@ -614,8 +613,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
> static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> void __iomem *base = pll_14nm->mmio;
> u64 vco_rate, multiplier = BIT(20);
> u32 div_frac_start;
> @@ -654,15 +652,14 @@ static unsigned long
> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
>
> static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> void __iomem *base = pll_14nm->mmio;
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> bool locked;
>
> DBG("");
>
> - if (unlikely(pll->pll_on))
> + if (unlikely(pll_14nm->phy->pll_on))
> return 0;
>
> pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
> @@ -677,29 +674,41 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw
> *hw)
> }
>
> DBG("DSI PLL lock success");
> - pll->pll_on = true;
> + pll_14nm->phy->pll_on = true;
>
> return 0;
> }
>
> static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
>
> DBG("");
>
> - if (unlikely(!pll->pll_on))
> + if (unlikely(!pll_14nm->phy->pll_on))
> return;
>
> pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
>
> - pll->pll_on = false;
> + pll_14nm->phy->pll_on = false;
> +}
> +
> +static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> +
> + if (rate < pll_14nm->phy->cfg->min_pll_rate)
> + return pll_14nm->phy->cfg->min_pll_rate;
> + else if (rate > pll_14nm->phy->cfg->max_pll_rate)
> + return pll_14nm->phy->cfg->max_pll_rate;
> + else
> + return rate;
> }
>
> static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_14nm_clk_round_rate,
> .set_rate = dsi_pll_14nm_vco_set_rate,
> .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
> .prepare = dsi_pll_14nm_vco_prepare,
> @@ -773,7 +782,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
> /* If we're master in dual DSI mode, then the slave PLL's
> post-dividers
> * follow the master's post dividers
> */
> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
> + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>
> @@ -797,7 +806,7 @@ static const struct clk_ops
> clk_ops_dsi_pll_14nm_postdiv = {
>
> static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> u32 data;
> @@ -810,18 +819,18 @@ static void dsi_14nm_save_state(struct
> msm_dsi_phy *phy)
> DBG("DSI%d PLL save state %x %x", pll_14nm->id,
> cached_state->n1postdiv, cached_state->n2postdiv);
>
> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> }
>
> static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> u32 data;
> int ret;
>
> - ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
> + ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_14nm->pdev->dev,
> @@ -837,7 +846,7 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
>
> /* also restore post-dividers for slave DSI PLL */
> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
> + if (phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>
> @@ -847,14 +856,13 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> return 0;
> }
>
> -static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
> - enum msm_dsi_phy_usecase uc)
> +static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> void __iomem *base = pll_14nm->mmio;
> u32 clkbuflr_en, bandgap = 0;
>
> - switch (uc) {
> + switch (phy->usecase) {
> case MSM_DSI_PHY_STANDALONE:
> clkbuflr_en = 0x1;
> break;
> @@ -874,8 +882,6 @@ static int dsi_pll_14nm_set_usecase(struct
> msm_dsi_pll *pll,
> if (bandgap)
> pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
>
> - pll_14nm->uc = uc;
> -
> return 0;
> }
>
> @@ -932,9 +938,9 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> DBG("DSI%d", pll_14nm->id);
>
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
> - pll_14nm->base.clk_hw.init = &vco_init;
> + pll_14nm->clk_hw.init = &vco_init;
>
> - ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
> if (ret)
> return ret;
>
> @@ -990,7 +996,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> struct platform_device *pdev = phy->pdev;
> int id = phy->id;
> struct dsi_pll_14nm *pll_14nm;
> - struct msm_dsi_pll *pll;
> int ret;
>
> if (!pdev)
> @@ -1020,8 +1025,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
>
> spin_lock_init(&pll_14nm->postdiv_lock);
>
> - pll = &pll_14nm->base;
> - pll->cfg = phy->cfg;
> + pll_14nm->phy = phy;
>
> ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
> if (ret) {
> @@ -1029,7 +1033,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> return ret;
> }
>
> - phy->pll = pll;
> + phy->vco_hw = &pll_14nm->clk_hw;
>
> return 0;
> }
> @@ -1131,7 +1135,7 @@ static int dsi_14nm_phy_enable(struct
> msm_dsi_phy *phy, int src_pll_id,
> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
> DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>
> - ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase);
> + ret = dsi_14nm_set_usecase(phy);
> if (ret) {
> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
> __func__, ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index bfd110eb25fc..1b95ea75235c 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -7,7 +7,6 @@
> #include <linux/clk-provider.h>
>
> #include "dsi_phy.h"
> -#include "dsi_pll.h"
> #include "dsi.xml.h"
>
> /*
> @@ -66,16 +65,19 @@ struct pll_28nm_cached_state {
> };
>
> struct dsi_pll_28nm {
> - struct msm_dsi_pll base;
> + struct clk_hw clk_hw;
>
> int id;
> struct platform_device *pdev;
> +
> + struct msm_dsi_phy *phy;
> +
> void __iomem *mmio;
>
> struct pll_28nm_cached_state cached_state;
> };
>
> -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
> +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
>
> static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
> u32 nb_tries, u32 timeout_us)
> @@ -116,8 +118,7 @@ static void pll_28nm_software_reset(struct
> dsi_pll_28nm *pll_28nm)
> static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> void __iomem *base = pll_28nm->mmio;
> unsigned long div_fbx1000, gen_vco_clk;
> @@ -210,7 +211,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
> pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
>
> /* Add hardware recommended delay for correct PLL configuration */
> - if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> udelay(1000);
> else
> udelay(1);
> @@ -233,8 +234,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
>
> static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
> POLL_TIMEOUT_US);
> @@ -243,8 +243,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct
> clk_hw *hw)
> static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> void __iomem *base = pll_28nm->mmio;
> u32 sdm0, doubler, sdm_byp_div;
> u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> @@ -289,9 +288,8 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> return vco_rate;
> }
>
> -static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
> +static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm
> *pll_28nm)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> struct device *dev = &pll_28nm->pdev->dev;
> void __iomem *base = pll_28nm->mmio;
> u32 max_reads = 5, timeout_us = 100;
> @@ -366,16 +364,16 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct
> msm_dsi_pll *pll)
>
> static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> int i, ret;
>
> - if (unlikely(pll->pll_on))
> + if (unlikely(pll_28nm->phy->pll_on))
> return 0;
>
> for (i = 0; i < 3; i++) {
> - ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
> + ret = _dsi_pll_28nm_vco_prepare_hpm(pll_28nm);
> if (!ret) {
> - pll->pll_on = true;
> + pll_28nm->phy->pll_on = true;
> return 0;
> }
> }
> @@ -385,8 +383,7 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct
> clk_hw *hw)
>
> static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> void __iomem *base = pll_28nm->mmio;
> bool locked;
> @@ -395,7 +392,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
> clk_hw *hw)
>
> DBG("id=%d", pll_28nm->id);
>
> - if (unlikely(pll->pll_on))
> + if (unlikely(pll_28nm->phy->pll_on))
> return 0;
>
> pll_28nm_software_reset(pll_28nm);
> @@ -428,28 +425,40 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
> clk_hw *hw)
> }
>
> DBG("DSI PLL lock success");
> - pll->pll_on = true;
> + pll_28nm->phy->pll_on = true;
>
> return 0;
> }
>
> static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> DBG("id=%d", pll_28nm->id);
>
> - if (unlikely(!pll->pll_on))
> + if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
>
> - pll->pll_on = false;
> + pll_28nm->phy->pll_on = false;
> +}
> +
> +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> +
> + if (rate < pll_28nm->phy->cfg->min_pll_rate)
> + return pll_28nm->phy->cfg->min_pll_rate;
> + else if (rate > pll_28nm->phy->cfg->max_pll_rate)
> + return pll_28nm->phy->cfg->max_pll_rate;
> + else
> + return rate;
> }
>
> static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_28nm_clk_round_rate,
> .set_rate = dsi_pll_28nm_clk_set_rate,
> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> .prepare = dsi_pll_28nm_vco_prepare_hpm,
> @@ -458,7 +467,7 @@ static const struct clk_ops
> clk_ops_dsi_pll_28nm_vco_hpm = {
> };
>
> static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_28nm_clk_round_rate,
> .set_rate = dsi_pll_28nm_clk_set_rate,
> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> .prepare = dsi_pll_28nm_vco_prepare_lp,
> @@ -472,7 +481,7 @@ static const struct clk_ops
> clk_ops_dsi_pll_28nm_vco_lp = {
>
> static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
>
> @@ -481,20 +490,20 @@ static void dsi_28nm_save_state(struct
> msm_dsi_phy *phy)
> cached_state->postdiv1 =
> pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
> cached_state->byte_mux = pll_read(base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG);
> - if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw))
> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> + if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> else
> cached_state->vco_rate = 0;
> }
>
> static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
> int ret;
>
> - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
> + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> @@ -527,14 +536,14 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>
> DBG("%d", pll_28nm->id);
>
> - if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> else
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
>
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> - pll_28nm->base.clk_hw.init = &vco_init;
> - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
> + pll_28nm->clk_hw.init = &vco_init;
> + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
> if (ret)
> return ret;
>
> @@ -593,7 +602,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
> struct platform_device *pdev = phy->pdev;
> int id = phy->id;
> struct dsi_pll_28nm *pll_28nm;
> - struct msm_dsi_pll *pll;
> int ret;
>
> if (!pdev)
> @@ -612,8 +620,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
> return -ENOMEM;
> }
>
> - pll = &pll_28nm->base;
> - pll->cfg = phy->cfg;
> + pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> if (ret) {
> @@ -621,7 +628,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
> return ret;
> }
>
> - phy->pll = pll;
> + phy->vco_hw = &pll_28nm->clk_hw;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index c71c5f07666d..3e63a3b70818 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -7,7 +7,6 @@
> #include <linux/delay.h>
>
> #include "dsi_phy.h"
> -#include "dsi_pll.h"
> #include "dsi.xml.h"
>
> /*
> @@ -58,16 +57,19 @@ struct clk_bytediv {
> };
>
> struct dsi_pll_28nm {
> - struct msm_dsi_pll base;
> + struct clk_hw clk_hw;
>
> int id;
> struct platform_device *pdev;
> +
> + struct msm_dsi_phy *phy;
> +
> void __iomem *mmio;
>
> struct pll_28nm_cached_state cached_state;
> };
>
> -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
> +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
>
> static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
> int nb_tries, int timeout_us)
> @@ -95,8 +97,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
> static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> void __iomem *base = pll_28nm->mmio;
> u32 val, temp, fb_divider;
>
> @@ -136,8 +137,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
>
> static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
> POLL_TIMEOUT_US);
> @@ -146,8 +146,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct
> clk_hw *hw)
> static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> void __iomem *base = pll_28nm->mmio;
> unsigned long vco_rate;
> u32 status, fb_divider, temp, ref_divider;
> @@ -180,8 +179,7 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>
> static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> void __iomem *base = pll_28nm->mmio;
> bool locked;
> @@ -191,7 +189,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw
> *hw)
>
> DBG("id=%d", pll_28nm->id);
>
> - if (unlikely(pll->pll_on))
> + if (unlikely(pll_28nm->phy->pll_on))
> return 0;
>
> /*
> @@ -222,28 +220,40 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw
> *hw)
> }
>
> DBG("DSI PLL lock success");
> - pll->pll_on = true;
> + pll_28nm->phy->pll_on = true;
>
> return 0;
> }
>
> static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> DBG("id=%d", pll_28nm->id);
>
> - if (unlikely(!pll->pll_on))
> + if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
>
> - pll->pll_on = false;
> + pll_28nm->phy->pll_on = false;
> +}
> +
> +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> +
> + if (rate < pll_28nm->phy->cfg->min_pll_rate)
> + return pll_28nm->phy->cfg->min_pll_rate;
> + else if (rate > pll_28nm->phy->cfg->max_pll_rate)
> + return pll_28nm->phy->cfg->max_pll_rate;
> + else
> + return rate;
> }
>
> static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_28nm_clk_round_rate,
> .set_rate = dsi_pll_28nm_clk_set_rate,
> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
> .prepare = dsi_pll_28nm_vco_prepare,
> @@ -336,7 +346,7 @@ static const struct clk_ops clk_bytediv_ops = {
> */
> static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
>
> @@ -347,17 +357,17 @@ static void dsi_28nm_save_state(struct
> msm_dsi_phy *phy)
> cached_state->postdiv1 =
> pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
>
> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> }
>
> static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> void __iomem *base = pll_28nm->mmio;
> int ret;
>
> - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
> + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> @@ -407,9 +417,9 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> vco_init.name = vco_name;
>
> - pll_28nm->base.clk_hw.init = &vco_init;
> + pll_28nm->clk_hw.init = &vco_init;
>
> - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
> if (ret)
> return ret;
>
> @@ -450,7 +460,6 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
> struct platform_device *pdev = phy->pdev;
> int id = phy->id;
> struct dsi_pll_28nm *pll_28nm;
> - struct msm_dsi_pll *pll;
> int ret;
>
> if (!pdev)
> @@ -469,9 +478,7 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
> return -ENOMEM;
> }
>
> - pll = &pll_28nm->base;
> -
> - pll->cfg = phy->cfg;
> + pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> if (ret) {
> @@ -479,7 +486,7 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
> return ret;
> }
>
> - phy->pll = pll;
> + phy->vco_hw = &pll_28nm->clk_hw;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 015e099d7b7f..c922e46f5241 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -7,7 +7,6 @@
> #include <linux/clk-provider.h>
> #include <linux/iopoll.h>
>
> -#include "dsi_pll.h"
> #include "dsi_phy.h"
> #include "dsi.xml.h"
>
> @@ -85,11 +84,13 @@ struct pll_7nm_cached_state {
> };
>
> struct dsi_pll_7nm {
> - struct msm_dsi_pll base;
> + struct clk_hw clk_hw;
>
> int id;
> struct platform_device *pdev;
>
> + struct msm_dsi_phy *phy;
> +
> void __iomem *phy_cmn_mmio;
> void __iomem *mmio;
>
> @@ -104,11 +105,10 @@ struct dsi_pll_7nm {
>
> struct pll_7nm_cached_state cached_state;
>
> - enum msm_dsi_phy_usecase uc;
> struct dsi_pll_7nm *slave;
> };
>
> -#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base)
> +#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
>
> /*
> * Global list of private DSI PLL struct pointers. We need this for
> Dual DSI
> @@ -164,7 +164,7 @@ static void dsi_pll_calc_dec_frac(struct
> dsi_pll_7nm *pll)
>
> dec = div_u64(dec_multiple, multiplier);
>
> - if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
> regs->pll_clock_inverters = 0x28;
> else if (pll_freq <= 1000000000ULL)
> regs->pll_clock_inverters = 0xa0;
> @@ -259,7 +259,7 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_7nm *pll)
> void __iomem *base = pll->mmio;
> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>
> - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> if (pll->vco_current_rate >= 3100000000ULL)
> analog_controls_five_1 = 0x03;
>
> @@ -293,9 +293,9 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_7nm *pll)
> pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
> pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
> pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
> - pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
> + pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
>
> - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> if (pll->slave)
> pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE,
> 0x22);
> @@ -321,8 +321,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll)
> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>
> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
> parent_rate);
> @@ -420,8 +419,7 @@ static void dsi_pll_phy_dig_reset(struct
> dsi_pll_7nm *pll)
>
> static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> int rc;
>
> dsi_pll_enable_pll_bias(pll_7nm);
> @@ -444,7 +442,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
> goto error;
> }
>
> - pll->pll_on = true;
> + pll_7nm->phy->pll_on = true;
>
> /*
> * assert power on reset for PHY digital in case the PLL is
> @@ -471,8 +469,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_7nm
> *pll)
>
> static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>
> /*
> * To avoid any stray glitches while abruptly powering down the PLL
> @@ -488,14 +485,13 @@ static void dsi_pll_7nm_vco_unprepare(struct
> clk_hw *hw)
> }
> /* flush, ensure all register writes are done */
> wmb();
> - pll->pll_on = false;
> + pll_7nm->phy->pll_on = false;
> }
>
> static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> struct dsi_pll_config *config = &pll_7nm->pll_configuration;
> void __iomem *base = pll_7nm->mmio;
> u64 ref_clk = pll_7nm->vco_ref_clk_rate;
> @@ -531,8 +527,21 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> return (unsigned long)vco_rate;
> }
>
> +static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *parent_rate)
> +{
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> +
> + if (rate < pll_7nm->phy->cfg->min_pll_rate)
> + return pll_7nm->phy->cfg->min_pll_rate;
> + else if (rate > pll_7nm->phy->cfg->max_pll_rate)
> + return pll_7nm->phy->cfg->max_pll_rate;
> + else
> + return rate;
> +}
> +
> static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
> + .round_rate = dsi_pll_7nm_clk_round_rate,
> .set_rate = dsi_pll_7nm_vco_set_rate,
> .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
> .prepare = dsi_pll_7nm_vco_prepare,
> @@ -545,7 +554,7 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco
> = {
>
> static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
> @@ -568,7 +577,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy
> *phy)
>
> static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> u32 val;
> @@ -587,7 +596,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy
> *phy)
> val |= cached->pll_mux;
> pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> if (ret) {
> DRM_DEV_ERROR(&pll_7nm->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> @@ -599,16 +608,15 @@ static int dsi_7nm_restore_state(struct
> msm_dsi_phy *phy)
> return 0;
> }
>
> -static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
> - enum msm_dsi_phy_usecase uc)
> +static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
> {
> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> void __iomem *base = pll_7nm->phy_cmn_mmio;
> u32 data = 0x0; /* internal PLL */
>
> DBG("DSI PLL%d", pll_7nm->id);
>
> - switch (uc) {
> + switch (phy->usecase) {
> case MSM_DSI_PHY_STANDALONE:
> break;
> case MSM_DSI_PHY_MASTER:
> @@ -624,8 +632,6 @@ static int dsi_pll_7nm_set_usecase(struct
> msm_dsi_pll *pll,
> /* set PLL src */
> pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
>
> - pll_7nm->uc = uc;
> -
> return 0;
> }
>
> @@ -653,9 +659,9 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> DBG("DSI%d", pll_7nm->id);
>
> snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
> - pll_7nm->base.clk_hw.init = &vco_init;
> + pll_7nm->clk_hw.init = &vco_init;
>
> - ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw);
> + ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
> if (ret)
> return ret;
>
> @@ -765,7 +771,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> struct platform_device *pdev = phy->pdev;
> int id = phy->id;
> struct dsi_pll_7nm *pll_7nm;
> - struct msm_dsi_pll *pll;
> int ret;
>
> pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
> @@ -792,8 +797,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
>
> spin_lock_init(&pll_7nm->postdiv_lock);
>
> - pll = &pll_7nm->base;
> - pll->cfg = phy->cfg;
> + pll_7nm->phy = phy;
>
> ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
> if (ret) {
> @@ -801,7 +805,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> return ret;
> }
>
> - phy->pll = pll;
> + phy->vco_hw = &pll_7nm->clk_hw;
>
> /* TODO: Remove this when we have proper display handover support */
> msm_dsi_phy_save_state(phy);
> @@ -966,7 +970,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> /* Select full-rate mode */
> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
>
> - ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase);
> + ret = dsi_7nm_set_usecase(phy);
> if (ret) {
> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
> __func__, ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> deleted file mode 100644
> index cae668b669a4..000000000000
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
> - */
> -
> -#include "dsi_phy.h"
> -#include "dsi_pll.h"
> -
> -/*
> - * DSI PLL Helper functions
> - */
> -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
> - unsigned long rate, unsigned long *parent_rate)
> -{
> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> -
> - if (rate < pll->cfg->min_pll_rate)
> - return pll->cfg->min_pll_rate;
> - else if (rate > pll->cfg->max_pll_rate)
> - return pll->cfg->max_pll_rate;
> - else
> - return rate;
> -}
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> deleted file mode 100644
> index da83e4c11f4f..000000000000
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
> - */
> -
> -#ifndef __DSI_PLL_H__
> -#define __DSI_PLL_H__
> -
> -#include <linux/delay.h>
> -
> -#include "dsi.h"
> -
> -static inline void pll_write(void __iomem *reg, u32 data)
> -{
> - msm_writel(data, reg);
> -}
> -
> -static inline u32 pll_read(const void __iomem *reg)
> -{
> - return msm_readl(reg);
> -}
> -
> -static inline void pll_write_udelay(void __iomem *reg, u32 data, u32
> delay_us)
> -{
> - pll_write(reg, data);
> - udelay(delay_us);
> -}
> -
> -static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32
> delay_ns)
> -{
> - pll_write((reg), data);
> - ndelay(delay_ns);
> -}
> -
> -/*
> - * DSI PLL Helper functions
> - */
> -
> -/* clock callbacks */
> -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
> - unsigned long rate, unsigned long *parent_rate);
> -
> -#endif /* __DSI_PLL_H__ */
> -
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton
2021-03-30 3:13 ` [Freedreno] " abhinavk
@ 2021-03-30 3:35 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Jonathan Marek, Stephen Boyd, linux-arm-msm,
Michael Turquette, dri-devel, David Airlie, Rob Clark,
Daniel Vetter, Sean Paul, linux-clk
On 2021-03-29 20:13, abhinavk@codeaurora.org wrote:
> On 2021-03-27 04:02, Dmitry Baryshkov wrote:
>> Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
>> directly into struct msm_dsi_phy.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Forgot to mention, please fix the typo "abstraction" in the subject
line.
With that fixed:
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>> ---
>> drivers/gpu/drm/msm/Kconfig | 8 --
>> drivers/gpu/drm/msm/Makefile | 2 -
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 36 +++++---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 66 ++++++++-------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 78 ++++++++---------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 83
>> ++++++++++---------
>> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 65 ++++++++-------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 74 +++++++++--------
>> drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 23 -----
>> drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 44 ----------
>> 10 files changed, 221 insertions(+), 258 deletions(-)
>> delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
>> delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
>>
>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
>> index dabb4a1ccdcf..1f0b3f0e7149 100644
>> --- a/drivers/gpu/drm/msm/Kconfig
>> +++ b/drivers/gpu/drm/msm/Kconfig
>> @@ -76,14 +76,6 @@ config DRM_MSM_DSI
>> Choose this option if you have a need for MIPI DSI connector
>> support.
>>
>> -config DRM_MSM_DSI_PLL
>> - bool "Enable DSI PLL driver in MSM DRM"
>> - depends on DRM_MSM_DSI && COMMON_CLK
>> - default y
>> - help
>> - Choose this option to enable DSI PLL driver which provides DSI
>> - source clocks under common clock framework.
>> -
>> config DRM_MSM_DSI_28NM_PHY
>> bool "Enable DSI 28nm PHY driver in MSM DRM"
>> depends on DRM_MSM_DSI
>> diff --git a/drivers/gpu/drm/msm/Makefile
>> b/drivers/gpu/drm/msm/Makefile
>> index 1be6996b80b7..610d630326bb 100644
>> --- a/drivers/gpu/drm/msm/Makefile
>> +++ b/drivers/gpu/drm/msm/Makefile
>> @@ -136,6 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) +=
>> dsi/phy/dsi_phy_14nm.o
>> msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
>> msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
>>
>> -msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o
>> -
>> obj-$(CONFIG_DRM_MSM) += msm.o
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index fa09f4c2c071..4fe410c97d3a 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -7,6 +7,7 @@
>> #define __DSI_PHY_H__
>>
>> #include <linux/clk-provider.h>
>> +#include <linux/delay.h>
>> #include <linux/regulator/consumer.h>
>>
>> #include "dsi.h"
>> @@ -14,15 +15,6 @@
>> #define dsi_phy_read(offset) msm_readl((offset))
>> #define dsi_phy_write(offset, data) msm_writel((data), (offset))
>>
>> -struct msm_dsi_pll {
>> - struct clk_hw clk_hw;
>> - bool pll_on;
>> -
>> - const struct msm_dsi_phy_cfg *cfg;
>> -};
>> -
>> -#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
>> -
>> struct msm_dsi_phy_ops {
>> int (*pll_init)(struct msm_dsi_phy *phy);
>> int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
>> @@ -107,7 +99,8 @@ struct msm_dsi_phy {
>> enum msm_dsi_phy_usecase usecase;
>> bool regulator_ldo_mode;
>>
>> - struct msm_dsi_pll *pll;
>> + struct clk_hw *vco_hw;
>> + bool pll_on;
>>
>> struct clk_hw_onecell_data *provided_clocks;
>>
>> @@ -127,6 +120,27 @@ int msm_dsi_dphy_timing_calc_v4(struct
>> msm_dsi_dphy_timing *timing,
>> struct msm_dsi_phy_clk_request *clk_req);
>> void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
>> reg,
>> u32 bit_mask);
>> +/* PLL accessors */
>> +static inline void pll_write(void __iomem *reg, u32 data)
>> +{
>> + msm_writel(data, reg);
>> +}
>> +
>> +static inline u32 pll_read(const void __iomem *reg)
>> +{
>> + return msm_readl(reg);
>> +}
>> +
>> +static inline void pll_write_udelay(void __iomem *reg, u32 data, u32
>> delay_us)
>> +{
>> + pll_write(reg, data);
>> + udelay(delay_us);
>> +}
>> +
>> +static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32
>> delay_ns)
>> +{
>> + pll_write((reg), data);
>> + ndelay(delay_ns);
>> +}
>>
>> #endif /* __DSI_PHY_H__ */
>> -
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> index 25fd4d860c4d..dec9beadddaa 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> @@ -7,7 +7,6 @@
>> #include <linux/clk-provider.h>
>> #include <linux/iopoll.h>
>>
>> -#include "dsi_pll.h"
>> #include "dsi_phy.h"
>> #include "dsi.xml.h"
>>
>> @@ -85,11 +84,13 @@ struct pll_10nm_cached_state {
>> };
>>
>> struct dsi_pll_10nm {
>> - struct msm_dsi_pll base;
>> + struct clk_hw clk_hw;
>>
>> int id;
>> struct platform_device *pdev;
>>
>> + struct msm_dsi_phy *phy;
>> +
>> void __iomem *phy_cmn_mmio;
>> void __iomem *mmio;
>>
>> @@ -104,11 +105,10 @@ struct dsi_pll_10nm {
>>
>> struct pll_10nm_cached_state cached_state;
>>
>> - enum msm_dsi_phy_usecase uc;
>> struct dsi_pll_10nm *slave;
>> };
>>
>> -#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base)
>> +#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw)
>>
>> /*
>> * Global list of private DSI PLL struct pointers. We need this for
>> Dual DSI
>> @@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm
>> *pll)
>> static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>>
>> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
>> parent_rate);
>> @@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct
>> dsi_pll_10nm *pll)
>>
>> static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>> struct device *dev = &pll_10nm->pdev->dev;
>> int rc;
>>
>> @@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
>> *hw)
>> goto error;
>> }
>>
>> - pll->pll_on = true;
>> + pll_10nm->phy->pll_on = true;
>>
>> dsi_pll_enable_global_clk(pll_10nm);
>> if (pll_10nm->slave)
>> @@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct
>> dsi_pll_10nm *pll)
>>
>> static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>>
>> /*
>> * To avoid any stray glitches while abruptly powering down the PLL
>> @@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct
>> clk_hw *hw)
>> }
>> /* flush, ensure all register writes are done */
>> wmb();
>> - pll->pll_on = false;
>> + pll_10nm->phy->pll_on = false;
>> }
>>
>> static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>> struct dsi_pll_config *config = &pll_10nm->pll_configuration;
>> void __iomem *base = pll_10nm->mmio;
>> u64 ref_clk = pll_10nm->vco_ref_clk_rate;
>> @@ -506,8 +502,21 @@ static unsigned long
>> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
>> return (unsigned long)vco_rate;
>> }
>>
>> +static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
>> + unsigned long rate, unsigned long *parent_rate)
>> +{
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>> +
>> + if (rate < pll_10nm->phy->cfg->min_pll_rate)
>> + return pll_10nm->phy->cfg->min_pll_rate;
>> + else if (rate > pll_10nm->phy->cfg->max_pll_rate)
>> + return pll_10nm->phy->cfg->max_pll_rate;
>> + else
>> + return rate;
>> +}
>> +
>> static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_10nm_clk_round_rate,
>> .set_rate = dsi_pll_10nm_vco_set_rate,
>> .recalc_rate = dsi_pll_10nm_vco_recalc_rate,
>> .prepare = dsi_pll_10nm_vco_prepare,
>> @@ -520,7 +529,7 @@ static const struct clk_ops
>> clk_ops_dsi_pll_10nm_vco = {
>>
>> static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
>> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
>> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
>> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>> @@ -543,7 +552,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy
>> *phy)
>>
>> static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
>> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
>> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
>> u32 val;
>> @@ -562,7 +571,7 @@ static int dsi_10nm_restore_state(struct
>> msm_dsi_phy *phy)
>> val |= cached->pll_mux;
>> pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>>
>> - ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw,
>> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
>> + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
>> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_10nm->pdev->dev,
>> "restore vco rate failed. ret=%d\n", ret);
>> @@ -574,16 +583,15 @@ static int dsi_10nm_restore_state(struct
>> msm_dsi_phy *phy)
>> return 0;
>> }
>>
>> -static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
>> - enum msm_dsi_phy_usecase uc)
>> +static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
>> + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
>> void __iomem *base = pll_10nm->phy_cmn_mmio;
>> u32 data = 0x0; /* internal PLL */
>>
>> DBG("DSI PLL%d", pll_10nm->id);
>>
>> - switch (uc) {
>> + switch (phy->usecase) {
>> case MSM_DSI_PHY_STANDALONE:
>> break;
>> case MSM_DSI_PHY_MASTER:
>> @@ -599,8 +607,6 @@ static int dsi_pll_10nm_set_usecase(struct
>> msm_dsi_pll *pll,
>> /* set PLL src */
>> pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
>>
>> - pll_10nm->uc = uc;
>> -
>> return 0;
>> }
>>
>> @@ -628,9 +634,9 @@ static int pll_10nm_register(struct dsi_pll_10nm
>> *pll_10nm, struct clk_hw **prov
>> DBG("DSI%d", pll_10nm->id);
>>
>> snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
>> - pll_10nm->base.clk_hw.init = &vco_init;
>> + pll_10nm->clk_hw.init = &vco_init;
>>
>> - ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
>> + ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
>> if (ret)
>> return ret;
>>
>> @@ -740,7 +746,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
>> *phy)
>> struct platform_device *pdev = phy->pdev;
>> int id = phy->id;
>> struct dsi_pll_10nm *pll_10nm;
>> - struct msm_dsi_pll *pll;
>> int ret;
>>
>> pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
>> @@ -767,8 +772,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
>> *phy)
>>
>> spin_lock_init(&pll_10nm->postdiv_lock);
>>
>> - pll = &pll_10nm->base;
>> - pll->cfg = phy->cfg;
>> + pll_10nm->phy = phy;
>>
>> ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
>> if (ret) {
>> @@ -776,7 +780,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
>> *phy)
>> return ret;
>> }
>>
>> - phy->pll = pll;
>> + phy->vco_hw = &pll_10nm->clk_hw;
>>
>> /* TODO: Remove this when we have proper display handover support */
>> msm_dsi_phy_save_state(phy);
>> @@ -951,7 +955,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>> /* Select full-rate mode */
>> dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
>>
>> - ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
>> + ret = dsi_10nm_set_usecase(phy);
>> if (ret) {
>> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
>> __func__, ret);
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> index c7c462bfe96d..86f9aedd790f 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> @@ -8,7 +8,6 @@
>> #include <linux/delay.h>
>>
>> #include "dsi_phy.h"
>> -#include "dsi_pll.h"
>> #include "dsi.xml.h"
>>
>> #define PHY_14NM_CKLN_IDX 4
>> @@ -114,7 +113,7 @@ struct pll_14nm_cached_state {
>> };
>>
>> struct dsi_pll_14nm {
>> - struct msm_dsi_pll base;
>> + struct clk_hw clk_hw;
>>
>> int id;
>> struct platform_device *pdev;
>> @@ -122,6 +121,8 @@ struct dsi_pll_14nm {
>> void __iomem *phy_cmn_mmio;
>> void __iomem *mmio;
>>
>> + struct msm_dsi_phy *phy;
>> +
>> struct dsi_pll_input in;
>> struct dsi_pll_output out;
>>
>> @@ -133,11 +134,10 @@ struct dsi_pll_14nm {
>>
>> struct pll_14nm_cached_state cached_state;
>>
>> - enum msm_dsi_phy_usecase uc;
>> struct dsi_pll_14nm *slave;
>> };
>>
>> -#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
>> +#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw)
>>
>> /*
>> * Private struct for N1/N2 post-divider clocks. These clocks are
>> similar to
>> @@ -564,8 +564,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm
>> *pll,
>> static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> struct dsi_pll_input *pin = &pll_14nm->in;
>> struct dsi_pll_output *pout = &pll_14nm->out;
>>
>> @@ -600,7 +599,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>> * don't lock the slave PLL. We just ensure that the PLL/PHY
>> registers
>> * of the master and slave are identical
>> */
>> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
>> + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
>> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>>
>> pll_db_commit_14nm(pll_14nm_slave, pin, pout);
>> @@ -614,8 +613,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>> static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> void __iomem *base = pll_14nm->mmio;
>> u64 vco_rate, multiplier = BIT(20);
>> u32 div_frac_start;
>> @@ -654,15 +652,14 @@ static unsigned long
>> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
>>
>> static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> void __iomem *base = pll_14nm->mmio;
>> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
>> bool locked;
>>
>> DBG("");
>>
>> - if (unlikely(pll->pll_on))
>> + if (unlikely(pll_14nm->phy->pll_on))
>> return 0;
>>
>> pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
>> @@ -677,29 +674,41 @@ static int dsi_pll_14nm_vco_prepare(struct
>> clk_hw *hw)
>> }
>>
>> DBG("DSI PLL lock success");
>> - pll->pll_on = true;
>> + pll_14nm->phy->pll_on = true;
>>
>> return 0;
>> }
>>
>> static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
>>
>> DBG("");
>>
>> - if (unlikely(!pll->pll_on))
>> + if (unlikely(!pll_14nm->phy->pll_on))
>> return;
>>
>> pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
>>
>> - pll->pll_on = false;
>> + pll_14nm->phy->pll_on = false;
>> +}
>> +
>> +static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
>> + unsigned long rate, unsigned long *parent_rate)
>> +{
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> +
>> + if (rate < pll_14nm->phy->cfg->min_pll_rate)
>> + return pll_14nm->phy->cfg->min_pll_rate;
>> + else if (rate > pll_14nm->phy->cfg->max_pll_rate)
>> + return pll_14nm->phy->cfg->max_pll_rate;
>> + else
>> + return rate;
>> }
>>
>> static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_14nm_clk_round_rate,
>> .set_rate = dsi_pll_14nm_vco_set_rate,
>> .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
>> .prepare = dsi_pll_14nm_vco_prepare,
>> @@ -773,7 +782,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
>> clk_hw *hw, unsigned long rate,
>> /* If we're master in dual DSI mode, then the slave PLL's
>> post-dividers
>> * follow the master's post dividers
>> */
>> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
>> + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
>> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>>
>> @@ -797,7 +806,7 @@ static const struct clk_ops
>> clk_ops_dsi_pll_14nm_postdiv = {
>>
>> static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
>> struct pll_14nm_cached_state *cached_state =
>> &pll_14nm->cached_state;
>> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
>> u32 data;
>> @@ -810,18 +819,18 @@ static void dsi_14nm_save_state(struct
>> msm_dsi_phy *phy)
>> DBG("DSI%d PLL save state %x %x", pll_14nm->id,
>> cached_state->n1postdiv, cached_state->n2postdiv);
>>
>> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
>> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
>> }
>>
>> static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
>> struct pll_14nm_cached_state *cached_state =
>> &pll_14nm->cached_state;
>> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
>> u32 data;
>> int ret;
>>
>> - ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
>> + ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
>> cached_state->vco_rate, 0);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_14nm->pdev->dev,
>> @@ -837,7 +846,7 @@ static int dsi_14nm_restore_state(struct
>> msm_dsi_phy *phy)
>> pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
>>
>> /* also restore post-dividers for slave DSI PLL */
>> - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
>> + if (phy->usecase == MSM_DSI_PHY_MASTER) {
>> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>>
>> @@ -847,14 +856,13 @@ static int dsi_14nm_restore_state(struct
>> msm_dsi_phy *phy)
>> return 0;
>> }
>>
>> -static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
>> - enum msm_dsi_phy_usecase uc)
>> +static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
>> + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
>> void __iomem *base = pll_14nm->mmio;
>> u32 clkbuflr_en, bandgap = 0;
>>
>> - switch (uc) {
>> + switch (phy->usecase) {
>> case MSM_DSI_PHY_STANDALONE:
>> clkbuflr_en = 0x1;
>> break;
>> @@ -874,8 +882,6 @@ static int dsi_pll_14nm_set_usecase(struct
>> msm_dsi_pll *pll,
>> if (bandgap)
>> pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
>>
>> - pll_14nm->uc = uc;
>> -
>> return 0;
>> }
>>
>> @@ -932,9 +938,9 @@ static int pll_14nm_register(struct dsi_pll_14nm
>> *pll_14nm, struct clk_hw **prov
>> DBG("DSI%d", pll_14nm->id);
>>
>> snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
>> - pll_14nm->base.clk_hw.init = &vco_init;
>> + pll_14nm->clk_hw.init = &vco_init;
>>
>> - ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
>> + ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
>> if (ret)
>> return ret;
>>
>> @@ -990,7 +996,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
>> *phy)
>> struct platform_device *pdev = phy->pdev;
>> int id = phy->id;
>> struct dsi_pll_14nm *pll_14nm;
>> - struct msm_dsi_pll *pll;
>> int ret;
>>
>> if (!pdev)
>> @@ -1020,8 +1025,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
>> *phy)
>>
>> spin_lock_init(&pll_14nm->postdiv_lock);
>>
>> - pll = &pll_14nm->base;
>> - pll->cfg = phy->cfg;
>> + pll_14nm->phy = phy;
>>
>> ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
>> if (ret) {
>> @@ -1029,7 +1033,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
>> *phy)
>> return ret;
>> }
>>
>> - phy->pll = pll;
>> + phy->vco_hw = &pll_14nm->clk_hw;
>>
>> return 0;
>> }
>> @@ -1131,7 +1135,7 @@ static int dsi_14nm_phy_enable(struct
>> msm_dsi_phy *phy, int src_pll_id,
>> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
>> DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>>
>> - ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase);
>> + ret = dsi_14nm_set_usecase(phy);
>> if (ret) {
>> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
>> __func__, ret);
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> index bfd110eb25fc..1b95ea75235c 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> @@ -7,7 +7,6 @@
>> #include <linux/clk-provider.h>
>>
>> #include "dsi_phy.h"
>> -#include "dsi_pll.h"
>> #include "dsi.xml.h"
>>
>> /*
>> @@ -66,16 +65,19 @@ struct pll_28nm_cached_state {
>> };
>>
>> struct dsi_pll_28nm {
>> - struct msm_dsi_pll base;
>> + struct clk_hw clk_hw;
>>
>> int id;
>> struct platform_device *pdev;
>> +
>> + struct msm_dsi_phy *phy;
>> +
>> void __iomem *mmio;
>>
>> struct pll_28nm_cached_state cached_state;
>> };
>>
>> -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
>> +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
>>
>> static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
>> u32 nb_tries, u32 timeout_us)
>> @@ -116,8 +118,7 @@ static void pll_28nm_software_reset(struct
>> dsi_pll_28nm *pll_28nm)
>> static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> struct device *dev = &pll_28nm->pdev->dev;
>> void __iomem *base = pll_28nm->mmio;
>> unsigned long div_fbx1000, gen_vco_clk;
>> @@ -210,7 +211,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>> pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
>>
>> /* Add hardware recommended delay for correct PLL configuration */
>> - if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>> + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>> udelay(1000);
>> else
>> udelay(1);
>> @@ -233,8 +234,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>>
>> static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>>
>> return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
>> POLL_TIMEOUT_US);
>> @@ -243,8 +243,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct
>> clk_hw *hw)
>> static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> void __iomem *base = pll_28nm->mmio;
>> u32 sdm0, doubler, sdm_byp_div;
>> u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
>> @@ -289,9 +288,8 @@ static unsigned long
>> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>> return vco_rate;
>> }
>>
>> -static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
>> +static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm
>> *pll_28nm)
>> {
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> struct device *dev = &pll_28nm->pdev->dev;
>> void __iomem *base = pll_28nm->mmio;
>> u32 max_reads = 5, timeout_us = 100;
>> @@ -366,16 +364,16 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct
>> msm_dsi_pll *pll)
>>
>> static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> int i, ret;
>>
>> - if (unlikely(pll->pll_on))
>> + if (unlikely(pll_28nm->phy->pll_on))
>> return 0;
>>
>> for (i = 0; i < 3; i++) {
>> - ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
>> + ret = _dsi_pll_28nm_vco_prepare_hpm(pll_28nm);
>> if (!ret) {
>> - pll->pll_on = true;
>> + pll_28nm->phy->pll_on = true;
>> return 0;
>> }
>> }
>> @@ -385,8 +383,7 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct
>> clk_hw *hw)
>>
>> static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> struct device *dev = &pll_28nm->pdev->dev;
>> void __iomem *base = pll_28nm->mmio;
>> bool locked;
>> @@ -395,7 +392,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
>> clk_hw *hw)
>>
>> DBG("id=%d", pll_28nm->id);
>>
>> - if (unlikely(pll->pll_on))
>> + if (unlikely(pll_28nm->phy->pll_on))
>> return 0;
>>
>> pll_28nm_software_reset(pll_28nm);
>> @@ -428,28 +425,40 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
>> clk_hw *hw)
>> }
>>
>> DBG("DSI PLL lock success");
>> - pll->pll_on = true;
>> + pll_28nm->phy->pll_on = true;
>>
>> return 0;
>> }
>>
>> static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>>
>> DBG("id=%d", pll_28nm->id);
>>
>> - if (unlikely(!pll->pll_on))
>> + if (unlikely(!pll_28nm->phy->pll_on))
>> return;
>>
>> pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
>>
>> - pll->pll_on = false;
>> + pll_28nm->phy->pll_on = false;
>> +}
>> +
>> +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
>> + unsigned long rate, unsigned long *parent_rate)
>> +{
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> +
>> + if (rate < pll_28nm->phy->cfg->min_pll_rate)
>> + return pll_28nm->phy->cfg->min_pll_rate;
>> + else if (rate > pll_28nm->phy->cfg->max_pll_rate)
>> + return pll_28nm->phy->cfg->max_pll_rate;
>> + else
>> + return rate;
>> }
>>
>> static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_28nm_clk_round_rate,
>> .set_rate = dsi_pll_28nm_clk_set_rate,
>> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
>> .prepare = dsi_pll_28nm_vco_prepare_hpm,
>> @@ -458,7 +467,7 @@ static const struct clk_ops
>> clk_ops_dsi_pll_28nm_vco_hpm = {
>> };
>>
>> static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_28nm_clk_round_rate,
>> .set_rate = dsi_pll_28nm_clk_set_rate,
>> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
>> .prepare = dsi_pll_28nm_vco_prepare_lp,
>> @@ -472,7 +481,7 @@ static const struct clk_ops
>> clk_ops_dsi_pll_28nm_vco_lp = {
>>
>> static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
>> struct pll_28nm_cached_state *cached_state =
>> &pll_28nm->cached_state;
>> void __iomem *base = pll_28nm->mmio;
>>
>> @@ -481,20 +490,20 @@ static void dsi_28nm_save_state(struct
>> msm_dsi_phy *phy)
>> cached_state->postdiv1 =
>> pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
>> cached_state->byte_mux = pll_read(base +
>> REG_DSI_28nm_PHY_PLL_VREG_CFG);
>> - if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw))
>> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
>> + if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
>> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
>> else
>> cached_state->vco_rate = 0;
>> }
>>
>> static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
>> struct pll_28nm_cached_state *cached_state =
>> &pll_28nm->cached_state;
>> void __iomem *base = pll_28nm->mmio;
>> int ret;
>>
>> - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
>> + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
>> cached_state->vco_rate, 0);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
>> @@ -527,14 +536,14 @@ static int pll_28nm_register(struct dsi_pll_28nm
>> *pll_28nm, struct clk_hw **prov
>>
>> DBG("%d", pll_28nm->id);
>>
>> - if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>> + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
>> else
>> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
>>
>> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
>> - pll_28nm->base.clk_hw.init = &vco_init;
>> - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
>> + pll_28nm->clk_hw.init = &vco_init;
>> + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
>> if (ret)
>> return ret;
>>
>> @@ -593,7 +602,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
>> *phy)
>> struct platform_device *pdev = phy->pdev;
>> int id = phy->id;
>> struct dsi_pll_28nm *pll_28nm;
>> - struct msm_dsi_pll *pll;
>> int ret;
>>
>> if (!pdev)
>> @@ -612,8 +620,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
>> *phy)
>> return -ENOMEM;
>> }
>>
>> - pll = &pll_28nm->base;
>> - pll->cfg = phy->cfg;
>> + pll_28nm->phy = phy;
>>
>> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
>> if (ret) {
>> @@ -621,7 +628,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
>> *phy)
>> return ret;
>> }
>>
>> - phy->pll = pll;
>> + phy->vco_hw = &pll_28nm->clk_hw;
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> index c71c5f07666d..3e63a3b70818 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> @@ -7,7 +7,6 @@
>> #include <linux/delay.h>
>>
>> #include "dsi_phy.h"
>> -#include "dsi_pll.h"
>> #include "dsi.xml.h"
>>
>> /*
>> @@ -58,16 +57,19 @@ struct clk_bytediv {
>> };
>>
>> struct dsi_pll_28nm {
>> - struct msm_dsi_pll base;
>> + struct clk_hw clk_hw;
>>
>> int id;
>> struct platform_device *pdev;
>> +
>> + struct msm_dsi_phy *phy;
>> +
>> void __iomem *mmio;
>>
>> struct pll_28nm_cached_state cached_state;
>> };
>>
>> -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
>> +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)
>>
>> static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
>> int nb_tries, int timeout_us)
>> @@ -95,8 +97,7 @@ static bool pll_28nm_poll_for_ready(struct
>> dsi_pll_28nm *pll_28nm,
>> static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> void __iomem *base = pll_28nm->mmio;
>> u32 val, temp, fb_divider;
>>
>> @@ -136,8 +137,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
>> *hw, unsigned long rate,
>>
>> static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>>
>> return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
>> POLL_TIMEOUT_US);
>> @@ -146,8 +146,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct
>> clk_hw *hw)
>> static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> void __iomem *base = pll_28nm->mmio;
>> unsigned long vco_rate;
>> u32 status, fb_divider, temp, ref_divider;
>> @@ -180,8 +179,7 @@ static unsigned long
>> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>>
>> static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> struct device *dev = &pll_28nm->pdev->dev;
>> void __iomem *base = pll_28nm->mmio;
>> bool locked;
>> @@ -191,7 +189,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw
>> *hw)
>>
>> DBG("id=%d", pll_28nm->id);
>>
>> - if (unlikely(pll->pll_on))
>> + if (unlikely(pll_28nm->phy->pll_on))
>> return 0;
>>
>> /*
>> @@ -222,28 +220,40 @@ static int dsi_pll_28nm_vco_prepare(struct
>> clk_hw *hw)
>> }
>>
>> DBG("DSI PLL lock success");
>> - pll->pll_on = true;
>> + pll_28nm->phy->pll_on = true;
>>
>> return 0;
>> }
>>
>> static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>>
>> DBG("id=%d", pll_28nm->id);
>>
>> - if (unlikely(!pll->pll_on))
>> + if (unlikely(!pll_28nm->phy->pll_on))
>> return;
>>
>> pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
>>
>> - pll->pll_on = false;
>> + pll_28nm->phy->pll_on = false;
>> +}
>> +
>> +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
>> + unsigned long rate, unsigned long *parent_rate)
>> +{
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>> +
>> + if (rate < pll_28nm->phy->cfg->min_pll_rate)
>> + return pll_28nm->phy->cfg->min_pll_rate;
>> + else if (rate > pll_28nm->phy->cfg->max_pll_rate)
>> + return pll_28nm->phy->cfg->max_pll_rate;
>> + else
>> + return rate;
>> }
>>
>> static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_28nm_clk_round_rate,
>> .set_rate = dsi_pll_28nm_clk_set_rate,
>> .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
>> .prepare = dsi_pll_28nm_vco_prepare,
>> @@ -336,7 +346,7 @@ static const struct clk_ops clk_bytediv_ops = {
>> */
>> static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
>> struct pll_28nm_cached_state *cached_state =
>> &pll_28nm->cached_state;
>> void __iomem *base = pll_28nm->mmio;
>>
>> @@ -347,17 +357,17 @@ static void dsi_28nm_save_state(struct
>> msm_dsi_phy *phy)
>> cached_state->postdiv1 =
>> pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
>>
>> - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
>> + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
>> }
>>
>> static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll);
>> + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
>> struct pll_28nm_cached_state *cached_state =
>> &pll_28nm->cached_state;
>> void __iomem *base = pll_28nm->mmio;
>> int ret;
>>
>> - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw,
>> + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
>> cached_state->vco_rate, 0);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_28nm->pdev->dev,
>> @@ -407,9 +417,9 @@ static int pll_28nm_register(struct dsi_pll_28nm
>> *pll_28nm, struct clk_hw **prov
>> snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
>> vco_init.name = vco_name;
>>
>> - pll_28nm->base.clk_hw.init = &vco_init;
>> + pll_28nm->clk_hw.init = &vco_init;
>>
>> - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw);
>> + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
>> if (ret)
>> return ret;
>>
>> @@ -450,7 +460,6 @@ static int dsi_pll_28nm_8960_init(struct
>> msm_dsi_phy *phy)
>> struct platform_device *pdev = phy->pdev;
>> int id = phy->id;
>> struct dsi_pll_28nm *pll_28nm;
>> - struct msm_dsi_pll *pll;
>> int ret;
>>
>> if (!pdev)
>> @@ -469,9 +478,7 @@ static int dsi_pll_28nm_8960_init(struct
>> msm_dsi_phy *phy)
>> return -ENOMEM;
>> }
>>
>> - pll = &pll_28nm->base;
>> -
>> - pll->cfg = phy->cfg;
>> + pll_28nm->phy = phy;
>>
>> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
>> if (ret) {
>> @@ -479,7 +486,7 @@ static int dsi_pll_28nm_8960_init(struct
>> msm_dsi_phy *phy)
>> return ret;
>> }
>>
>> - phy->pll = pll;
>> + phy->vco_hw = &pll_28nm->clk_hw;
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 015e099d7b7f..c922e46f5241 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -7,7 +7,6 @@
>> #include <linux/clk-provider.h>
>> #include <linux/iopoll.h>
>>
>> -#include "dsi_pll.h"
>> #include "dsi_phy.h"
>> #include "dsi.xml.h"
>>
>> @@ -85,11 +84,13 @@ struct pll_7nm_cached_state {
>> };
>>
>> struct dsi_pll_7nm {
>> - struct msm_dsi_pll base;
>> + struct clk_hw clk_hw;
>>
>> int id;
>> struct platform_device *pdev;
>>
>> + struct msm_dsi_phy *phy;
>> +
>> void __iomem *phy_cmn_mmio;
>> void __iomem *mmio;
>>
>> @@ -104,11 +105,10 @@ struct dsi_pll_7nm {
>>
>> struct pll_7nm_cached_state cached_state;
>>
>> - enum msm_dsi_phy_usecase uc;
>> struct dsi_pll_7nm *slave;
>> };
>>
>> -#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base)
>> +#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
>>
>> /*
>> * Global list of private DSI PLL struct pointers. We need this for
>> Dual DSI
>> @@ -164,7 +164,7 @@ static void dsi_pll_calc_dec_frac(struct
>> dsi_pll_7nm *pll)
>>
>> dec = div_u64(dec_multiple, multiplier);
>>
>> - if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
>> regs->pll_clock_inverters = 0x28;
>> else if (pll_freq <= 1000000000ULL)
>> regs->pll_clock_inverters = 0xa0;
>> @@ -259,7 +259,7 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_7nm *pll)
>> void __iomem *base = pll->mmio;
>> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>>
>> - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> if (pll->vco_current_rate >= 3100000000ULL)
>> analog_controls_five_1 = 0x03;
>>
>> @@ -293,9 +293,9 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_7nm *pll)
>> pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
>> pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
>> pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
>> - pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
>> + pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
>>
>> - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
>> if (pll->slave)
>> pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE,
>> 0x22);
>> @@ -321,8 +321,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm
>> *pll)
>> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>>
>> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
>> parent_rate);
>> @@ -420,8 +419,7 @@ static void dsi_pll_phy_dig_reset(struct
>> dsi_pll_7nm *pll)
>>
>> static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>> int rc;
>>
>> dsi_pll_enable_pll_bias(pll_7nm);
>> @@ -444,7 +442,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
>> *hw)
>> goto error;
>> }
>>
>> - pll->pll_on = true;
>> + pll_7nm->phy->pll_on = true;
>>
>> /*
>> * assert power on reset for PHY digital in case the PLL is
>> @@ -471,8 +469,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_7nm
>> *pll)
>>
>> static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>>
>> /*
>> * To avoid any stray glitches while abruptly powering down the PLL
>> @@ -488,14 +485,13 @@ static void dsi_pll_7nm_vco_unprepare(struct
>> clk_hw *hw)
>> }
>> /* flush, ensure all register writes are done */
>> wmb();
>> - pll->pll_on = false;
>> + pll_7nm->phy->pll_on = false;
>> }
>>
>> static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>> struct dsi_pll_config *config = &pll_7nm->pll_configuration;
>> void __iomem *base = pll_7nm->mmio;
>> u64 ref_clk = pll_7nm->vco_ref_clk_rate;
>> @@ -531,8 +527,21 @@ static unsigned long
>> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
>> return (unsigned long)vco_rate;
>> }
>>
>> +static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
>> + unsigned long rate, unsigned long *parent_rate)
>> +{
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>> +
>> + if (rate < pll_7nm->phy->cfg->min_pll_rate)
>> + return pll_7nm->phy->cfg->min_pll_rate;
>> + else if (rate > pll_7nm->phy->cfg->max_pll_rate)
>> + return pll_7nm->phy->cfg->max_pll_rate;
>> + else
>> + return rate;
>> +}
>> +
>> static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
>> - .round_rate = msm_dsi_pll_helper_clk_round_rate,
>> + .round_rate = dsi_pll_7nm_clk_round_rate,
>> .set_rate = dsi_pll_7nm_vco_set_rate,
>> .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
>> .prepare = dsi_pll_7nm_vco_prepare,
>> @@ -545,7 +554,7 @@ static const struct clk_ops
>> clk_ops_dsi_pll_7nm_vco = {
>>
>> static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
>> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
>> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
>> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>> @@ -568,7 +577,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy
>> *phy)
>>
>> static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
>> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
>> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
>> u32 val;
>> @@ -587,7 +596,7 @@ static int dsi_7nm_restore_state(struct
>> msm_dsi_phy *phy)
>> val |= cached->pll_mux;
>> pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>>
>> - ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw,
>> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
>> + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
>> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_7nm->pdev->dev,
>> "restore vco rate failed. ret=%d\n", ret);
>> @@ -599,16 +608,15 @@ static int dsi_7nm_restore_state(struct
>> msm_dsi_phy *phy)
>> return 0;
>> }
>>
>> -static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
>> - enum msm_dsi_phy_usecase uc)
>> +static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
>> {
>> - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
>> + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
>> void __iomem *base = pll_7nm->phy_cmn_mmio;
>> u32 data = 0x0; /* internal PLL */
>>
>> DBG("DSI PLL%d", pll_7nm->id);
>>
>> - switch (uc) {
>> + switch (phy->usecase) {
>> case MSM_DSI_PHY_STANDALONE:
>> break;
>> case MSM_DSI_PHY_MASTER:
>> @@ -624,8 +632,6 @@ static int dsi_pll_7nm_set_usecase(struct
>> msm_dsi_pll *pll,
>> /* set PLL src */
>> pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
>>
>> - pll_7nm->uc = uc;
>> -
>> return 0;
>> }
>>
>> @@ -653,9 +659,9 @@ static int pll_7nm_register(struct dsi_pll_7nm
>> *pll_7nm, struct clk_hw **provide
>> DBG("DSI%d", pll_7nm->id);
>>
>> snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
>> - pll_7nm->base.clk_hw.init = &vco_init;
>> + pll_7nm->clk_hw.init = &vco_init;
>>
>> - ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw);
>> + ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
>> if (ret)
>> return ret;
>>
>> @@ -765,7 +771,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
>> *phy)
>> struct platform_device *pdev = phy->pdev;
>> int id = phy->id;
>> struct dsi_pll_7nm *pll_7nm;
>> - struct msm_dsi_pll *pll;
>> int ret;
>>
>> pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
>> @@ -792,8 +797,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
>> *phy)
>>
>> spin_lock_init(&pll_7nm->postdiv_lock);
>>
>> - pll = &pll_7nm->base;
>> - pll->cfg = phy->cfg;
>> + pll_7nm->phy = phy;
>>
>> ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
>> if (ret) {
>> @@ -801,7 +805,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
>> *phy)
>> return ret;
>> }
>>
>> - phy->pll = pll;
>> + phy->vco_hw = &pll_7nm->clk_hw;
>>
>> /* TODO: Remove this when we have proper display handover support */
>> msm_dsi_phy_save_state(phy);
>> @@ -966,7 +970,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>> /* Select full-rate mode */
>> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
>>
>> - ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase);
>> + ret = dsi_7nm_set_usecase(phy);
>> if (ret) {
>> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
>> __func__, ret);
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
>> deleted file mode 100644
>> index cae668b669a4..000000000000
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
>> +++ /dev/null
>> @@ -1,23 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0-only
>> -/*
>> - * Copyright (c) 2012-2015, The Linux Foundation. All rights
>> reserved.
>> - */
>> -
>> -#include "dsi_phy.h"
>> -#include "dsi_pll.h"
>> -
>> -/*
>> - * DSI PLL Helper functions
>> - */
>> -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
>> - unsigned long rate, unsigned long *parent_rate)
>> -{
>> - struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
>> -
>> - if (rate < pll->cfg->min_pll_rate)
>> - return pll->cfg->min_pll_rate;
>> - else if (rate > pll->cfg->max_pll_rate)
>> - return pll->cfg->max_pll_rate;
>> - else
>> - return rate;
>> -}
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
>> deleted file mode 100644
>> index da83e4c11f4f..000000000000
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
>> +++ /dev/null
>> @@ -1,44 +0,0 @@
>> -/* SPDX-License-Identifier: GPL-2.0-only */
>> -/*
>> - * Copyright (c) 2012-2015, The Linux Foundation. All rights
>> reserved.
>> - */
>> -
>> -#ifndef __DSI_PLL_H__
>> -#define __DSI_PLL_H__
>> -
>> -#include <linux/delay.h>
>> -
>> -#include "dsi.h"
>> -
>> -static inline void pll_write(void __iomem *reg, u32 data)
>> -{
>> - msm_writel(data, reg);
>> -}
>> -
>> -static inline u32 pll_read(const void __iomem *reg)
>> -{
>> - return msm_readl(reg);
>> -}
>> -
>> -static inline void pll_write_udelay(void __iomem *reg, u32 data, u32
>> delay_us)
>> -{
>> - pll_write(reg, data);
>> - udelay(delay_us);
>> -}
>> -
>> -static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32
>> delay_ns)
>> -{
>> - pll_write((reg), data);
>> - ndelay(delay_ns);
>> -}
>> -
>> -/*
>> - * DSI PLL Helper functions
>> - */
>> -
>> -/* clock callbacks */
>> -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
>> - unsigned long rate, unsigned long *parent_rate);
>> -
>> -#endif /* __DSI_PLL_H__ */
>> -
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (17 preceding siblings ...)
2021-03-27 11:02 ` [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 3:16 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov
` (5 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY
accessors, reducing duplication.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 124 ++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 126 ++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 118 +++++++--------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 54 +++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 140 +++++++++---------
6 files changed, 283 insertions(+), 303 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 4fe410c97d3a..d7031a35e2da 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -14,6 +14,8 @@
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
+#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
+#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
@@ -120,27 +122,5 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask);
-/* PLL accessors */
-static inline void pll_write(void __iomem *reg, u32 data)
-{
- msm_writel(data, reg);
-}
-
-static inline u32 pll_read(const void __iomem *reg)
-{
- return msm_readl(reg);
-}
-
-static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
-{
- pll_write(reg, data);
- udelay(delay_us);
-}
-
-static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
-{
- pll_write((reg), data);
- ndelay(delay_ns);
-}
#endif /* __DSI_PHY_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index dec9beadddaa..73afbb597a9f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -234,19 +234,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
if (pll->pll_configuration.enable_ssc) {
pr_debug("SSC is enabled\n");
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
regs->ssc_stepsize_low);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
regs->ssc_stepsize_high);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
regs->ssc_div_per_low);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
regs->ssc_div_per_high);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
regs->ssc_adjper_low);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
regs->ssc_adjper_high);
- pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
SSC_EN | regs->ssc_control);
}
}
@@ -255,26 +255,26 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
{
void __iomem *base = pll->mmio;
- pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
- pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
- pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
- pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
- pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
- pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
- pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
0xba);
- pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
- pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
- pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
0x4c);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
- pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
}
static void dsi_pll_commit(struct dsi_pll_10nm *pll)
@@ -282,20 +282,20 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll)
void __iomem *base = pll->mmio;
struct dsi_pll_regs *reg = &pll->reg_setup;
- pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
- pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
reg->decimal_div_start);
- pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
reg->frac_div_start_low);
- pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
reg->frac_div_start_mid);
- pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
reg->frac_div_start_high);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
reg->pll_lockdet_rate);
- pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
- pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
- pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
reg->pll_clock_inverters);
}
@@ -351,21 +351,21 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
{
- u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
- pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
- pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
+ dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
data & ~BIT(5));
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
{
- u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
- pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
data | BIT(5));
- pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
+ dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
ndelay(250);
}
@@ -373,8 +373,8 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
{
u32 data;
- data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
- pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
data & ~BIT(5));
}
@@ -382,8 +382,8 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
{
u32 data;
- data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
- pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
data | BIT(5));
}
@@ -404,7 +404,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
}
/* Start PLL */
- pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
+ dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
0x01);
/*
@@ -426,10 +426,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_global_clk(pll_10nm->slave);
- pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
+ dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
0x01);
if (pll_10nm->slave)
- pll_write(pll_10nm->slave->phy_cmn_mmio +
+ dsi_phy_write(pll_10nm->slave->phy_cmn_mmio +
REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
error:
@@ -438,7 +438,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
{
- pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
dsi_pll_disable_pll_bias(pll);
}
@@ -452,7 +452,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
* powering down the PLL
*/
dsi_pll_disable_global_clk(pll_10nm);
- pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
dsi_pll_disable_sub(pll_10nm);
if (pll_10nm->slave) {
dsi_pll_disable_global_clk(pll_10nm->slave);
@@ -476,13 +476,13 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
u32 dec;
u64 pll_freq, tmp64;
- dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
+ dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
dec &= 0xff;
- frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
- frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
+ frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
+ frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
0xff) << 8);
- frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
+ frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
0x3) << 16);
/*
@@ -534,15 +534,15 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
- cached->pll_out_div = pll_read(pll_10nm->mmio +
+ cached->pll_out_div = dsi_phy_read(pll_10nm->mmio +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
cached->pll_out_div &= 0x3;
- cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
+ cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
- cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
cached->pll_mux = cmn_clk_cfg1 & 0x3;
DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
@@ -558,18 +558,18 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
u32 val;
int ret;
- val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
val |= cached->pll_out_div;
- pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
+ dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
- pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
+ dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
cached->bit_clk_div | (cached->pix_clk_div << 4));
- val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
val &= ~0x3;
val |= cached->pll_mux;
- pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
+ dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
if (ret) {
@@ -605,7 +605,7 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
}
/* set PLL src */
- pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
+ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 86f9aedd790f..408192ae1456 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -172,7 +172,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
tries = nb_tries;
while (tries--) {
- val = pll_read(base +
+ val = dsi_phy_read(base +
REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
pll_locked = !!(val & BIT(5));
@@ -185,7 +185,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
if (!pll_locked) {
tries = nb_tries;
while (tries--) {
- val = pll_read(base +
+ val = dsi_phy_read(base +
REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
pll_locked = !!(val & BIT(0));
@@ -387,29 +387,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
data = pin->ssc_adj_period;
data &= 0x0ff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
data = (pin->ssc_adj_period >> 8);
data &= 0x03;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
data = pout->ssc_period;
data &= 0x0ff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
data = (pout->ssc_period >> 8);
data &= 0x0ff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
data = pout->ssc_step_size;
data &= 0x0ff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
data = (pout->ssc_step_size >> 8);
data &= 0x0ff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
data = (pin->ssc_center & 0x01);
data <<= 1;
data |= 0x01; /* enable */
- pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
wmb(); /* make sure register committed */
}
@@ -423,57 +423,57 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
/* confgiure the non frequency dependent pll registers */
data = 0;
- pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
data = pout->pll_txclk_en;
- pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
data = pout->pll_resetsm_cntrl;
- pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
data = pout->pll_resetsm_cntrl2;
- pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
data = pout->pll_resetsm_cntrl5;
- pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
data = pout->pll_vco_div_ref & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
data = (pout->pll_vco_div_ref >> 8) & 0x3;
- pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
data = pout->pll_kvco_div_ref & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
data = (pout->pll_kvco_div_ref >> 8) & 0x3;
- pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
data = pout->pll_misc1;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
data = pin->pll_ie_trim;
- pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
data = pin->pll_ip_trim;
- pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
- pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
data = pin->pll_icpmset << 3 | pin->pll_icpcset;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
data = pin->pll_iptat_trim;
- pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
}
static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
@@ -483,13 +483,13 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
/* de assert pll start and apply pll sw reset */
/* stop pll */
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
/* pll sw reset */
- pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
+ dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
wmb(); /* make sure register committed */
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
wmb(); /* make sure register committed */
}
@@ -504,53 +504,53 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
DBG("DSI%d PLL", pll->id);
data = pout->cmn_ldo_cntrl;
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
pll_db_commit_common(pll, pin, pout);
pll_14nm_software_reset(pll);
data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
data = 0xff; /* data, clk, pll normal operation */
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
/* configure the frequency dependent pll registers */
data = pout->dec_start;
- pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
data = pout->div_frac_start & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
data = (pout->div_frac_start >> 8) & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
data = (pout->div_frac_start >> 16) & 0xf;
- pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
data = pout->plllock_cmp & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
data = (pout->plllock_cmp >> 8) & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
data = (pout->plllock_cmp >> 16) & 0x3;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
data = pout->pll_vco_count & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
data = (pout->pll_vco_count >> 8) & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
data = pout->pll_kvco_count & 0xff;
- pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
data = (pout->pll_kvco_count >> 8) & 0x3;
- pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
if (pin->ssc_en)
pll_db_commit_ssc(pll);
@@ -620,16 +620,16 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
u32 dec_start;
u64 ref_clk = parent_rate;
- dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
+ dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
dec_start &= 0x0ff;
DBG("dec_start = %x", dec_start);
- div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
+ div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
& 0xf) << 16;
- div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
+ div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
& 0xff) << 8;
- div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
+ div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
& 0xff;
DBG("div_frac_start = %x", div_frac_start);
@@ -662,8 +662,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
if (unlikely(pll_14nm->phy->pll_on))
return 0;
- pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
POLL_TIMEOUT_US);
@@ -689,7 +689,7 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
if (unlikely(!pll_14nm->phy->pll_on))
return;
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
pll_14nm->phy->pll_on = false;
}
@@ -731,7 +731,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
- val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
+ val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
val &= div_mask(width);
return divider_recalc_rate(hw, parent_rate, val, NULL,
@@ -773,11 +773,11 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(lock, flags);
- val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+ val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
val &= ~(div_mask(width) << shift);
val |= value << shift;
- pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
/* If we're master in dual DSI mode, then the slave PLL's post-dividers
* follow the master's post dividers
@@ -786,7 +786,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
- pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
+ dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
}
spin_unlock_irqrestore(lock, flags);
@@ -811,7 +811,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
u32 data;
- data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+ data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
cached_state->n1postdiv = data & 0xf;
cached_state->n2postdiv = (data >> 4) & 0xf;
@@ -843,14 +843,14 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
cached_state->n1postdiv, cached_state->n2postdiv);
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
/* also restore post-dividers for slave DSI PLL */
if (phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
- pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
+ dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
}
return 0;
@@ -878,9 +878,9 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
return -EINVAL;
}
- pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
if (bandgap)
- pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 1b95ea75235c..e964ea210c0b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -86,7 +86,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
u32 val;
while (nb_tries--) {
- val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
+ val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
if (pll_locked)
@@ -107,9 +107,9 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
* Add HW recommended delays after toggling the software
* reset bit off and back on.
*/
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1);
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
}
/*
@@ -131,7 +131,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
VERB("rate=%lu, parent's=%lu", rate, parent_rate);
/* Force postdiv2 to be div-4 */
- pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
/* Configure the Loop filter resistance */
for (i = 0; i < LPFR_LUT_SIZE; i++)
@@ -142,11 +142,11 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
rate);
return -EINVAL;
}
- pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
/* Loop filter capacitance values : c1 and c2 */
- pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
- pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
rem = rate % VCO_REF_CLK_RATE;
if (rem) {
@@ -171,7 +171,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
DBG("Generated VCO Clock: %lu", gen_vco_clk);
rem = 0;
- sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
+ sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
if (frac_n_mode) {
sdm_cfg0 = 0x0;
@@ -198,17 +198,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000);
DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
- pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
- pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
- pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2));
- pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3));
- pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
/* Add hardware recommended delay for correct PLL configuration */
if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
@@ -216,18 +216,18 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
else
udelay(1);
- pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
- pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
- pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
- pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
- pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
- pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
return 0;
}
@@ -253,27 +253,27 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
VERB("parent_rate=%lu", parent_rate);
/* Check to see if the ref clk doubler is enabled */
- doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
+ doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
ref_clk += (doubler * VCO_REF_CLK_RATE);
/* see if it is integer mode or sdm mode */
- sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
+ sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) {
/* integer mode */
sdm_byp_div = FIELD(
- pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
+ dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1;
vco_rate = ref_clk * sdm_byp_div;
} else {
/* sdm mode */
sdm_dc_off = FIELD(
- pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
+ dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET);
DBG("sdm_dc_off = %d", sdm_dc_off);
- sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
+ sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0);
- sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
+ sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8);
sdm_freq_seed = (sdm3 << 8) | sdm2;
DBG("sdm_freq_seed = %d", sdm_freq_seed);
@@ -306,22 +306,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
* Add necessary delays recommended by hardware.
*/
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
for (i = 0; i < 2; i++) {
/* DSI Uniphy lock detect setting */
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
0x0c, 100);
- pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
/* poll for PLL ready status */
locked = pll_28nm_poll_for_ready(pll_28nm,
@@ -336,22 +336,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
* Add necessary delays recommended by hardware.
*/
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
}
if (unlikely(!locked))
@@ -401,21 +401,21 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
* PLL power up sequence.
* Add necessary delays recommended by hardware.
*/
- pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
+ dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
- pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
+ dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
- pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
+ dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B |
DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
- pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
+ dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
/* DSI PLL toggle lock detect setting */
- pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
- pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
+ dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
@@ -439,7 +439,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
if (unlikely(!pll_28nm->phy->pll_on))
return;
- pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
+ dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
pll_28nm->phy->pll_on = false;
}
@@ -486,10 +486,10 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
void __iomem *base = pll_28nm->mmio;
cached_state->postdiv3 =
- pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
+ dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
cached_state->postdiv1 =
- pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
- cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
+ dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
+ cached_state->byte_mux = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
else
@@ -511,11 +511,11 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
return ret;
}
- pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
cached_state->postdiv3);
- pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
cached_state->postdiv1);
- pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
+ dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
cached_state->byte_mux);
return 0;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 3e63a3b70818..faefae5ec23c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -78,7 +78,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
u32 val;
while (nb_tries--) {
- val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
+ val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
if (pll_locked)
@@ -107,29 +107,29 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
val = VCO_REF_CLK_RATE / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
fb_divider & 0xff);
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
+ val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
val |= (fb_divider >> 8) & 0x07;
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
val);
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
+ val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
val);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
0xf);
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
val |= 0x7 << 4;
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
val);
return 0;
@@ -153,16 +153,16 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
VERB("parent_rate=%lu", parent_rate);
- status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
+ status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {
- fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
+ fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
fb_divider &= 0xff;
- temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
+ temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
fb_divider = (temp << 8) | fb_divider;
fb_divider += 1;
- ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
+ ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
ref_divider &= 0x3f;
ref_divider += 1;
@@ -199,17 +199,17 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
* 2: divide by 8 to get bit clock divider
* 3: write it to POSTDIV1
*/
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
byte_div = val + 1;
bit_div = byte_div / 8;
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
val &= ~0xf;
val |= (bit_div - 1);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
/* enable the PLL */
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
@@ -234,7 +234,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
if (unlikely(!pll_28nm->phy->pll_on))
return;
- pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
+ dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
pll_28nm->phy->pll_on = false;
}
@@ -281,7 +281,7 @@ static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw,
struct clk_bytediv *bytediv = to_clk_bytediv(hw);
unsigned int div;
- div = pll_read(bytediv->reg) & 0xff;
+ div = dsi_phy_read(bytediv->reg) & 0xff;
return parent_rate / (div + 1);
}
@@ -327,9 +327,9 @@ static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate,
factor = get_vco_mul_factor(rate);
- val = pll_read(bytediv->reg);
+ val = dsi_phy_read(bytediv->reg);
val |= (factor - 1) & 0xff;
- pll_write(bytediv->reg, val);
+ dsi_phy_write(bytediv->reg, val);
return 0;
}
@@ -351,11 +351,11 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
void __iomem *base = pll_28nm->mmio;
cached_state->postdiv3 =
- pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
+ dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
cached_state->postdiv2 =
- pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
cached_state->postdiv1 =
- pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
}
@@ -375,11 +375,11 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
return ret;
}
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
cached_state->postdiv3);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
cached_state->postdiv2);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
+ dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
cached_state->postdiv1);
return 0;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index c922e46f5241..b873b2f67e3a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -237,19 +237,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
if (pll->pll_configuration.enable_ssc) {
pr_debug("SSC is enabled\n");
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
regs->ssc_stepsize_low);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
regs->ssc_stepsize_high);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
regs->ssc_div_per_low);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
regs->ssc_div_per_high);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
regs->ssc_adjper_low);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
regs->ssc_adjper_high);
- pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
SSC_EN | regs->ssc_control);
}
}
@@ -269,36 +269,36 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
vco_config_1 = 0x01;
}
- pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog_controls_five_1);
- pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
- pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
- pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
- pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
- pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
- pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
- pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
- pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
- pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
- pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
- pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
- pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
- pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
- pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
- pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
+ dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
}
}
@@ -307,15 +307,15 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll)
void __iomem *base = pll->mmio;
struct dsi_pll_regs *reg = &pll->reg_setup;
- pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
- pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start);
- pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low);
- pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid);
- pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate);
- pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
- pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
- pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
}
static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -369,19 +369,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
{
- u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
- pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
+ dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
{
- u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
- pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
+ dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
ndelay(250);
}
@@ -389,18 +389,18 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
{
u32 data;
- data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
+ data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
}
static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
{
u32 data;
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
- data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
data | BIT(5) | BIT(4));
}
@@ -411,9 +411,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
* coming out of a CX or analog rail power collapse while
* ensuring that the pads maintain LP00 or LP11 state
*/
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
wmb(); /* Ensure that the reset is deasserted */
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
wmb(); /* Ensure that the reset is deasserted */
}
@@ -427,7 +427,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
dsi_pll_enable_pll_bias(pll_7nm->slave);
/* Start PLL */
- pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
+ dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
/*
* ensure all PLL configurations are written prior to checking
@@ -463,7 +463,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
{
- pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
+ dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
dsi_pll_disable_pll_bias(pll);
}
@@ -477,7 +477,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
* powering down the PLL
*/
dsi_pll_disable_global_clk(pll_7nm);
- pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
dsi_pll_disable_sub(pll_7nm);
if (pll_7nm->slave) {
dsi_pll_disable_global_clk(pll_7nm->slave);
@@ -501,13 +501,13 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
u32 dec;
u64 pll_freq, tmp64;
- dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
+ dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
dec &= 0xff;
- frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
- frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
+ frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
+ frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
0xff) << 8);
- frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
+ frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
0x3) << 16);
/*
@@ -559,15 +559,15 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
- cached->pll_out_div = pll_read(pll_7nm->mmio +
+ cached->pll_out_div = dsi_phy_read(pll_7nm->mmio +
REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
cached->pll_out_div &= 0x3;
- cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
+ cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
- cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
cached->pll_mux = cmn_clk_cfg1 & 0x3;
DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
@@ -583,18 +583,18 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
u32 val;
int ret;
- val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val = dsi_phy_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
val |= cached->pll_out_div;
- pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
+ dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
- pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
+ dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
cached->bit_clk_div | (cached->pix_clk_div << 4));
- val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
val &= ~0x3;
val |= cached->pll_mux;
- pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
+ dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
if (ret) {
@@ -630,7 +630,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
}
/* set PLL src */
- pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
+ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
return 0;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions
2021-03-27 11:03 ` [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov
@ 2021-03-30 3:16 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY
> accessors, reducing duplication.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 124 ++++++++--------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 126 ++++++++--------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 118 +++++++--------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 54 +++----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 140 +++++++++---------
> 6 files changed, 283 insertions(+), 303 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 4fe410c97d3a..d7031a35e2da 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -14,6 +14,8 @@
>
> #define dsi_phy_read(offset) msm_readl((offset))
> #define dsi_phy_write(offset, data) msm_writel((data), (offset))
> +#define dsi_phy_write_udelay(offset, data, delay_us) {
> msm_writel((data), (offset)); udelay(delay_us); }
> +#define dsi_phy_write_ndelay(offset, data, delay_ns) {
> msm_writel((data), (offset)); ndelay(delay_ns); }
>
> struct msm_dsi_phy_ops {
> int (*pll_init)(struct msm_dsi_phy *phy);
> @@ -120,27 +122,5 @@ int msm_dsi_dphy_timing_calc_v4(struct
> msm_dsi_dphy_timing *timing,
> struct msm_dsi_phy_clk_request *clk_req);
> void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
> reg,
> u32 bit_mask);
> -/* PLL accessors */
> -static inline void pll_write(void __iomem *reg, u32 data)
> -{
> - msm_writel(data, reg);
> -}
> -
> -static inline u32 pll_read(const void __iomem *reg)
> -{
> - return msm_readl(reg);
> -}
> -
> -static inline void pll_write_udelay(void __iomem *reg, u32 data, u32
> delay_us)
> -{
> - pll_write(reg, data);
> - udelay(delay_us);
> -}
> -
> -static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32
> delay_ns)
> -{
> - pll_write((reg), data);
> - ndelay(delay_ns);
> -}
>
> #endif /* __DSI_PHY_H__ */
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index dec9beadddaa..73afbb597a9f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -234,19 +234,19 @@ static void dsi_pll_ssc_commit(struct
> dsi_pll_10nm *pll)
> if (pll->pll_configuration.enable_ssc) {
> pr_debug("SSC is enabled\n");
>
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> regs->ssc_stepsize_low);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> regs->ssc_stepsize_high);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> regs->ssc_div_per_low);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> regs->ssc_div_per_high);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
> regs->ssc_adjper_low);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
> regs->ssc_adjper_high);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
> SSC_EN | regs->ssc_control);
> }
> }
> @@ -255,26 +255,26 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_10nm *pll)
> {
> void __iomem *base = pll->mmio;
>
> - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE,
> 0x00);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS,
> 0x40);
> + dsi_phy_write(base +
> REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
> 0xba);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
> 0x0c);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0xfa);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
> 0x0c);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
> 0x08);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1,
> 0x08);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0xfa);
> + dsi_phy_write(base +
> REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
> 0x4c);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
> }
>
> static void dsi_pll_commit(struct dsi_pll_10nm *pll)
> @@ -282,20 +282,20 @@ static void dsi_pll_commit(struct dsi_pll_10nm
> *pll)
> void __iomem *base = pll->mmio;
> struct dsi_pll_regs *reg = &pll->reg_setup;
>
> - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
> reg->decimal_div_start);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> reg->frac_div_start_low);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
> reg->frac_div_start_mid);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> reg->frac_div_start_high);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> reg->pll_lockdet_rate);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
> - pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
> reg->pll_clock_inverters);
> }
>
> @@ -351,21 +351,21 @@ static int dsi_pll_10nm_lock_status(struct
> dsi_pll_10nm *pll)
>
> static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
> {
> - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
>
> - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> + dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> data & ~BIT(5));
> ndelay(250);
> }
>
> static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
> {
> - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
>
> - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> data | BIT(5));
> - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> + dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> ndelay(250);
> }
>
> @@ -373,8 +373,8 @@ static void dsi_pll_disable_global_clk(struct
> dsi_pll_10nm *pll)
> {
> u32 data;
>
> - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> data & ~BIT(5));
> }
>
> @@ -382,8 +382,8 @@ static void dsi_pll_enable_global_clk(struct
> dsi_pll_10nm *pll)
> {
> u32 data;
>
> - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> data | BIT(5));
> }
>
> @@ -404,7 +404,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> }
>
> /* Start PLL */
> - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> + dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> 0x01);
>
> /*
> @@ -426,10 +426,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> if (pll_10nm->slave)
> dsi_pll_enable_global_clk(pll_10nm->slave);
>
> - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
> + dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
> 0x01);
> if (pll_10nm->slave)
> - pll_write(pll_10nm->slave->phy_cmn_mmio +
> + dsi_phy_write(pll_10nm->slave->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
>
> error:
> @@ -438,7 +438,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
>
> static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
> {
> - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
> dsi_pll_disable_pll_bias(pll);
> }
>
> @@ -452,7 +452,7 @@ static void dsi_pll_10nm_vco_unprepare(struct
> clk_hw *hw)
> * powering down the PLL
> */
> dsi_pll_disable_global_clk(pll_10nm);
> - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> 0);
> + dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
> dsi_pll_disable_sub(pll_10nm);
> if (pll_10nm->slave) {
> dsi_pll_disable_global_clk(pll_10nm->slave);
> @@ -476,13 +476,13 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> u32 dec;
> u64 pll_freq, tmp64;
>
> - dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
> + dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
> dec &= 0xff;
>
> - frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
> - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1)
> &
> + frac = dsi_phy_read(base +
> REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
> + frac |= ((dsi_phy_read(base +
> REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
> 0xff) << 8);
> - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1)
> &
> + frac |= ((dsi_phy_read(base +
> REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
> 0x3) << 16);
>
> /*
> @@ -534,15 +534,15 @@ static void dsi_10nm_save_state(struct
> msm_dsi_phy *phy)
> void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>
> - cached->pll_out_div = pll_read(pll_10nm->mmio +
> + cached->pll_out_div = dsi_phy_read(pll_10nm->mmio +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> cached->pll_out_div &= 0x3;
>
> - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
> + cmn_clk_cfg0 = dsi_phy_read(phy_base +
> REG_DSI_10nm_PHY_CMN_CLK_CFG0);
> cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
> cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
>
> - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + cmn_clk_cfg1 = dsi_phy_read(phy_base +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> cached->pll_mux = cmn_clk_cfg1 & 0x3;
>
> DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
> @@ -558,18 +558,18 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> u32 val;
> int ret;
>
> - val = pll_read(pll_10nm->mmio +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> + val = dsi_phy_read(pll_10nm->mmio +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> val &= ~0x3;
> val |= cached->pll_out_div;
> - pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
> val);
> + dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
> val);
>
> - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> + dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> cached->bit_clk_div | (cached->pix_clk_div << 4));
>
> - val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> val &= ~0x3;
> val |= cached->pll_mux;
> - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
> + dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>
> ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> if (ret) {
> @@ -605,7 +605,7 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy
> *phy)
> }
>
> /* set PLL src */
> - pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
> + dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 86f9aedd790f..408192ae1456 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -172,7 +172,7 @@ static bool pll_14nm_poll_for_ready(struct
> dsi_pll_14nm *pll_14nm,
>
> tries = nb_tries;
> while (tries--) {
> - val = pll_read(base +
> + val = dsi_phy_read(base +
> REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
> pll_locked = !!(val & BIT(5));
>
> @@ -185,7 +185,7 @@ static bool pll_14nm_poll_for_ready(struct
> dsi_pll_14nm *pll_14nm,
> if (!pll_locked) {
> tries = nb_tries;
> while (tries--) {
> - val = pll_read(base +
> + val = dsi_phy_read(base +
> REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
> pll_locked = !!(val & BIT(0));
>
> @@ -387,29 +387,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm
> *pll)
>
> data = pin->ssc_adj_period;
> data &= 0x0ff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
> data = (pin->ssc_adj_period >> 8);
> data &= 0x03;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
>
> data = pout->ssc_period;
> data &= 0x0ff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
> data = (pout->ssc_period >> 8);
> data &= 0x0ff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
>
> data = pout->ssc_step_size;
> data &= 0x0ff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
> data = (pout->ssc_step_size >> 8);
> data &= 0x0ff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
>
> data = (pin->ssc_center & 0x01);
> data <<= 1;
> data |= 0x01; /* enable */
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
>
> wmb(); /* make sure register committed */
> }
> @@ -423,57 +423,57 @@ static void pll_db_commit_common(struct
> dsi_pll_14nm *pll,
>
> /* confgiure the non frequency dependent pll registers */
> data = 0;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
>
> data = pout->pll_txclk_en;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
>
> data = pout->pll_resetsm_cntrl;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
> data = pout->pll_resetsm_cntrl2;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
> data = pout->pll_resetsm_cntrl5;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
>
> data = pout->pll_vco_div_ref & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
> data = (pout->pll_vco_div_ref >> 8) & 0x3;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
>
> data = pout->pll_kvco_div_ref & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
> data = (pout->pll_kvco_div_ref >> 8) & 0x3;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
>
> data = pout->pll_misc1;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
>
> data = pin->pll_ie_trim;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
>
> data = pin->pll_ip_trim;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
>
> data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
>
> data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
>
> data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
>
> data = pin->pll_icpmset << 3 | pin->pll_icpcset;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
>
> data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
>
> data = pin->pll_iptat_trim;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
>
> data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
> }
>
> static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
> @@ -483,13 +483,13 @@ static void pll_14nm_software_reset(struct
> dsi_pll_14nm *pll_14nm)
> /* de assert pll start and apply pll sw reset */
>
> /* stop pll */
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
>
> /* pll sw reset */
> - pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
> + dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20,
> 10);
> wmb(); /* make sure register committed */
>
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
> wmb(); /* make sure register committed */
> }
>
> @@ -504,53 +504,53 @@ static void pll_db_commit_14nm(struct
> dsi_pll_14nm *pll,
> DBG("DSI%d PLL", pll->id);
>
> data = pout->cmn_ldo_cntrl;
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
>
> pll_db_commit_common(pll, pin, pout);
>
> pll_14nm_software_reset(pll);
>
> data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
>
> data = 0xff; /* data, clk, pll normal operation */
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
>
> /* configure the frequency dependent pll registers */
> data = pout->dec_start;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
>
> data = pout->div_frac_start & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
> data = (pout->div_frac_start >> 8) & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
> data = (pout->div_frac_start >> 16) & 0xf;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
>
> data = pout->plllock_cmp & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
>
> data = (pout->plllock_cmp >> 8) & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
>
> data = (pout->plllock_cmp >> 16) & 0x3;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
>
> data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
>
> data = pout->pll_vco_count & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
> data = (pout->pll_vco_count >> 8) & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
>
> data = pout->pll_kvco_count & 0xff;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
> data = (pout->pll_kvco_count >> 8) & 0x3;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
>
> data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
>
> if (pin->ssc_en)
> pll_db_commit_ssc(pll);
> @@ -620,16 +620,16 @@ static unsigned long
> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
> u32 dec_start;
> u64 ref_clk = parent_rate;
>
> - dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
> + dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
> dec_start &= 0x0ff;
>
> DBG("dec_start = %x", dec_start);
>
> - div_frac_start = (pll_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
> + div_frac_start = (dsi_phy_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
> & 0xf) << 16;
> - div_frac_start |= (pll_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
> + div_frac_start |= (dsi_phy_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
> & 0xff) << 8;
> - div_frac_start |= pll_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
> + div_frac_start |= dsi_phy_read(base +
> REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
> & 0xff;
>
> DBG("div_frac_start = %x", div_frac_start);
> @@ -662,8 +662,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw
> *hw)
> if (unlikely(pll_14nm->phy->pll_on))
> return 0;
>
> - pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
>
> locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
> POLL_TIMEOUT_US);
> @@ -689,7 +689,7 @@ static void dsi_pll_14nm_vco_unprepare(struct
> clk_hw *hw)
> if (unlikely(!pll_14nm->phy->pll_on))
> return;
>
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
>
> pll_14nm->phy->pll_on = false;
> }
> @@ -731,7 +731,7 @@ static unsigned long
> dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
>
> DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
>
> - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
> + val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
> val &= div_mask(width);
>
> return divider_recalc_rate(hw, parent_rate, val, NULL,
> @@ -773,11 +773,11 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
>
> spin_lock_irqsave(lock, flags);
>
> - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
> + val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
> val &= ~(div_mask(width) << shift);
>
> val |= value << shift;
> - pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
>
> /* If we're master in dual DSI mode, then the slave PLL's
> post-dividers
> * follow the master's post dividers
> @@ -786,7 +786,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>
> - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
> + dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
> }
>
> spin_unlock_irqrestore(lock, flags);
> @@ -811,7 +811,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy
> *phy)
> void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> u32 data;
>
> - data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
> + data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
>
> cached_state->n1postdiv = data & 0xf;
> cached_state->n2postdiv = (data >> 4) & 0xf;
> @@ -843,14 +843,14 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
> cached_state->n1postdiv, cached_state->n2postdiv);
>
> - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
>
> /* also restore post-dividers for slave DSI PLL */
> if (phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
>
> - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
> + dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
> }
>
> return 0;
> @@ -878,9 +878,9 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy
> *phy)
> return -EINVAL;
> }
>
> - pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
> if (bandgap)
> - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 1b95ea75235c..e964ea210c0b 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -86,7 +86,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
> u32 val;
>
> while (nb_tries--) {
> - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
> + val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
> pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
>
> if (pll_locked)
> @@ -107,9 +107,9 @@ static void pll_28nm_software_reset(struct
> dsi_pll_28nm *pll_28nm)
> * Add HW recommended delays after toggling the software
> * reset bit off and back on.
> */
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
> DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1);
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
> }
>
> /*
> @@ -131,7 +131,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
> VERB("rate=%lu, parent's=%lu", rate, parent_rate);
>
> /* Force postdiv2 to be div-4 */
> - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
>
> /* Configure the Loop filter resistance */
> for (i = 0; i < LPFR_LUT_SIZE; i++)
> @@ -142,11 +142,11 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
> rate);
> return -EINVAL;
> }
> - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG,
> lpfr_lut[i].resistance);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG,
> lpfr_lut[i].resistance);
>
> /* Loop filter capacitance values : c1 and c2 */
> - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
>
> rem = rate % VCO_REF_CLK_RATE;
> if (rem) {
> @@ -171,7 +171,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
>
> DBG("Generated VCO Clock: %lu", gen_vco_clk);
> rem = 0;
> - sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
> + sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
> sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
> if (frac_n_mode) {
> sdm_cfg0 = 0x0;
> @@ -198,17 +198,17 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
> cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000);
> DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11);
>
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
>
> - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
> DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2));
> - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
> DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3));
> - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
>
> /* Add hardware recommended delay for correct PLL configuration */
> if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> @@ -216,18 +216,18 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
> else
> udelay(1);
>
> - pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 &
> 0xff);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 &
> 0xff);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
>
> return 0;
> }
> @@ -253,27 +253,27 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> VERB("parent_rate=%lu", parent_rate);
>
> /* Check to see if the ref clk doubler is enabled */
> - doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
> + doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
> DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> ref_clk += (doubler * VCO_REF_CLK_RATE);
>
> /* see if it is integer mode or sdm mode */
> - sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> + sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) {
> /* integer mode */
> sdm_byp_div = FIELD(
> - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
> + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
> DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1;
> vco_rate = ref_clk * sdm_byp_div;
> } else {
> /* sdm mode */
> sdm_dc_off = FIELD(
> - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
> + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
> DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET);
> DBG("sdm_dc_off = %d", sdm_dc_off);
> - sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
> + sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
> DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0);
> - sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
> + sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
> DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8);
> sdm_freq_seed = (sdm3 << 8) | sdm2;
> DBG("sdm_freq_seed = %d", sdm_freq_seed);
> @@ -306,22 +306,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct
> dsi_pll_28nm *pll_28nm)
> * Add necessary delays recommended by hardware.
> */
> val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
>
> for (i = 0; i < 2; i++) {
> /* DSI Uniphy lock detect setting */
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
> 0x0c, 100);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
>
> /* poll for PLL ready status */
> locked = pll_28nm_poll_for_ready(pll_28nm,
> @@ -336,22 +336,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct
> dsi_pll_28nm *pll_28nm)
> * Add necessary delays recommended by hardware.
> */
> val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
>
> val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
> }
>
> if (unlikely(!locked))
> @@ -401,21 +401,21 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
> clk_hw *hw)
> * PLL power up sequence.
> * Add necessary delays recommended by hardware.
> */
> - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
> + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34,
> 500);
>
> val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
> - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
> + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
> - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
> + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
>
> val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B |
> DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
> - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
> + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
>
> /* DSI PLL toggle lock detect setting */
> - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
> - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
> + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04,
> 500);
> + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05,
> 512);
>
> locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
>
> @@ -439,7 +439,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> - pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
> + dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
>
> pll_28nm->phy->pll_on = false;
> }
> @@ -486,10 +486,10 @@ static void dsi_28nm_save_state(struct
> msm_dsi_phy *phy)
> void __iomem *base = pll_28nm->mmio;
>
> cached_state->postdiv3 =
> - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
> + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
> cached_state->postdiv1 =
> - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
> - cached_state->byte_mux = pll_read(base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG);
> + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
> + cached_state->byte_mux = dsi_phy_read(base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG);
> if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
> cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> else
> @@ -511,11 +511,11 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> return ret;
> }
>
> - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> cached_state->postdiv3);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
> cached_state->postdiv1);
> - pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
> + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
> cached_state->byte_mux);
>
> return 0;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 3e63a3b70818..faefae5ec23c 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -78,7 +78,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
> u32 val;
>
> while (nb_tries--) {
> - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
> + val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
> pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
>
> if (pll_locked)
> @@ -107,29 +107,29 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
> val = VCO_REF_CLK_RATE / 10;
> fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
> fb_divider = fb_divider / 2 - 1;
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
> fb_divider & 0xff);
>
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
> + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
>
> val |= (fb_divider >> 8) & 0x07;
>
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
> val);
>
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
> + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
>
> val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;
>
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
> val);
>
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
> 0xf);
>
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> val |= 0x7 << 4;
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
> val);
>
> return 0;
> @@ -153,16 +153,16 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>
> VERB("parent_rate=%lu", parent_rate);
>
> - status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
> + status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
>
> if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {
> - fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
> + fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
> fb_divider &= 0xff;
> - temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
> + temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
> fb_divider = (temp << 8) | fb_divider;
> fb_divider += 1;
>
> - ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
> + ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
> ref_divider &= 0x3f;
> ref_divider += 1;
>
> @@ -199,17 +199,17 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw
> *hw)
> * 2: divide by 8 to get bit clock divider
> * 3: write it to POSTDIV1
> */
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> byte_div = val + 1;
> bit_div = byte_div / 8;
>
> - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> val &= ~0xf;
> val |= (bit_div - 1);
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
>
> /* enable the PLL */
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
>
> locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
> @@ -234,7 +234,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> - pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
> + dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> 0x00);
>
> pll_28nm->phy->pll_on = false;
> }
> @@ -281,7 +281,7 @@ static unsigned long
> clk_bytediv_recalc_rate(struct clk_hw *hw,
> struct clk_bytediv *bytediv = to_clk_bytediv(hw);
> unsigned int div;
>
> - div = pll_read(bytediv->reg) & 0xff;
> + div = dsi_phy_read(bytediv->reg) & 0xff;
>
> return parent_rate / (div + 1);
> }
> @@ -327,9 +327,9 @@ static int clk_bytediv_set_rate(struct clk_hw *hw,
> unsigned long rate,
>
> factor = get_vco_mul_factor(rate);
>
> - val = pll_read(bytediv->reg);
> + val = dsi_phy_read(bytediv->reg);
> val |= (factor - 1) & 0xff;
> - pll_write(bytediv->reg, val);
> + dsi_phy_write(bytediv->reg, val);
>
> return 0;
> }
> @@ -351,11 +351,11 @@ static void dsi_28nm_save_state(struct
> msm_dsi_phy *phy)
> void __iomem *base = pll_28nm->mmio;
>
> cached_state->postdiv3 =
> - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
> + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
> cached_state->postdiv2 =
> - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
> cached_state->postdiv1 =
> - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
> + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
>
> cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> }
> @@ -375,11 +375,11 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> return ret;
> }
>
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
> cached_state->postdiv3);
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
> cached_state->postdiv2);
> - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
> + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
> cached_state->postdiv1);
>
> return 0;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index c922e46f5241..b873b2f67e3a 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -237,19 +237,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm
> *pll)
> if (pll->pll_configuration.enable_ssc) {
> pr_debug("SSC is enabled\n");
>
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> regs->ssc_stepsize_low);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> regs->ssc_stepsize_high);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> regs->ssc_div_per_low);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> regs->ssc_div_per_high);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
> regs->ssc_adjper_low);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
> regs->ssc_adjper_high);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
> SSC_EN | regs->ssc_control);
> }
> }
> @@ -269,36 +269,36 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_7nm *pll)
> vco_config_1 = 0x01;
> }
>
> - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> analog_controls_five_1);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
> 0xba);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0x84);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0x82);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
> 0x4c);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE,
> 0x00);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
> 0xba);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
> 0x0c);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
> 0x08);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0x84);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
> 0x82);
> + dsi_phy_write(base +
> REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
> pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
>
> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> if (pll->slave)
> - pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE,
> 0x22);
> + dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE,
> 0x22);
> }
> }
>
> @@ -307,15 +307,15 @@ static void dsi_pll_commit(struct dsi_pll_7nm
> *pll)
> void __iomem *base = pll->mmio;
> struct dsi_pll_regs *reg = &pll->reg_setup;
>
> - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
> reg->decimal_div_start);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> reg->frac_div_start_low);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
> reg->frac_div_start_mid);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> reg->frac_div_start_high);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> reg->pll_lockdet_rate);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> - pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00
> for CPHY */
> - pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
> reg->pll_clock_inverters);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
> reg->decimal_div_start);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> reg->frac_div_start_low);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
> reg->frac_div_start_mid);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> reg->frac_div_start_high);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> reg->pll_lockdet_rate);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO:
> 0x00 for CPHY */
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
> reg->pll_clock_inverters);
> }
>
> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> @@ -369,19 +369,19 @@ static int dsi_pll_7nm_lock_status(struct
> dsi_pll_7nm *pll)
>
> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> {
> - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data &
> ~BIT(5));
> + dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data &
> ~BIT(5));
> ndelay(250);
> }
>
> static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
> {
> - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data |
> BIT(5));
> - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data |
> BIT(5));
> + dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> ndelay(250);
> }
>
> @@ -389,18 +389,18 @@ static void dsi_pll_disable_global_clk(struct
> dsi_pll_7nm *pll)
> {
> u32 data;
>
> - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data &
> ~BIT(5));
> + data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data
> & ~BIT(5));
> }
>
> static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
> {
> u32 data;
>
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
>
> - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> data | BIT(5) | BIT(4));
> }
>
> @@ -411,9 +411,9 @@ static void dsi_pll_phy_dig_reset(struct
> dsi_pll_7nm *pll)
> * coming out of a CX or analog rail power collapse while
> * ensuring that the pads maintain LP00 or LP11 state
> */
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4,
> BIT(0));
> + dsi_phy_write(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
> wmb(); /* Ensure that the reset is deasserted */
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4,
> 0x0);
> + dsi_phy_write(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
> wmb(); /* Ensure that the reset is deasserted */
> }
>
> @@ -427,7 +427,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
> dsi_pll_enable_pll_bias(pll_7nm->slave);
>
> /* Start PLL */
> - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0x01);
> + dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0x01);
>
> /*
> * ensure all PLL configurations are written prior to checking
> @@ -463,7 +463,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
>
> static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
> {
> - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
> + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
> dsi_pll_disable_pll_bias(pll);
> }
>
> @@ -477,7 +477,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw
> *hw)
> * powering down the PLL
> */
> dsi_pll_disable_global_clk(pll_7nm);
> - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
> + dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0);
> dsi_pll_disable_sub(pll_7nm);
> if (pll_7nm->slave) {
> dsi_pll_disable_global_clk(pll_7nm->slave);
> @@ -501,13 +501,13 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> u32 dec;
> u64 pll_freq, tmp64;
>
> - dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
> + dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
> dec &= 0xff;
>
> - frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
> - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
> + frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
> + frac |= ((dsi_phy_read(base +
> REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
> 0xff) << 8);
> - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1)
> &
> + frac |= ((dsi_phy_read(base +
> REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
> 0x3) << 16);
>
> /*
> @@ -559,15 +559,15 @@ static void dsi_7nm_save_state(struct msm_dsi_phy
> *phy)
> void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>
> - cached->pll_out_div = pll_read(pll_7nm->mmio +
> + cached->pll_out_div = dsi_phy_read(pll_7nm->mmio +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> cached->pll_out_div &= 0x3;
>
> - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
> + cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
> cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
> cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
>
> - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> cached->pll_mux = cmn_clk_cfg1 & 0x3;
>
> DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
> @@ -583,18 +583,18 @@ static int dsi_7nm_restore_state(struct
> msm_dsi_phy *phy)
> u32 val;
> int ret;
>
> - val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> + val = dsi_phy_read(pll_7nm->mmio +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> val &= ~0x3;
> val |= cached->pll_out_div;
> - pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
> + dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
> val);
>
> - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> + dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> cached->bit_clk_div | (cached->pix_clk_div << 4));
>
> - val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> val &= ~0x3;
> val |= cached->pll_mux;
> - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
> + dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>
> ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> if (ret) {
> @@ -630,7 +630,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy
> *phy)
> }
>
> /* set PLL src */
> - pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
> + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
>
> return 0;
> }
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (18 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 3:18 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov
` (4 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
All PHY drivers would map dsi_pll area. Some PHY drivers would also
map dsi_phy area again (a leftover from old PHY/PLL separation). Move
all ioremaps to the common dsi_phy driver code and drop individual
ioremapped areas from PHY drivers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 7 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 75 +++++++-----------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 49 ++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 33 +++-----
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 27 +++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++-----------
7 files changed, 108 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f21f3babec68..74cc11c84d71 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -682,6 +682,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail;
}
+ phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
+ if (IS_ERR(phy->pll_base)) {
+ DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
+ ret = -ENOMEM;
+ goto fail;
+ }
+
if (phy->cfg->has_phy_lane) {
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
if (IS_ERR(phy->lane_base)) {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index d7031a35e2da..8e828c5ca8f4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -88,6 +88,7 @@ struct msm_dsi_dphy_timing {
struct msm_dsi_phy {
struct platform_device *pdev;
void __iomem *base;
+ void __iomem *pll_base;
void __iomem *reg_base;
void __iomem *lane_base;
int id;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 73afbb597a9f..8a15ae91d44b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -91,9 +91,6 @@ struct dsi_pll_10nm {
struct msm_dsi_phy *phy;
- void __iomem *phy_cmn_mmio;
- void __iomem *mmio;
-
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -228,7 +225,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
struct dsi_pll_regs *regs = &pll->reg_setup;
if (pll->pll_configuration.enable_ssc) {
@@ -253,7 +250,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
@@ -279,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
static void dsi_pll_commit(struct dsi_pll_10nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
struct dsi_pll_regs *reg = &pll->reg_setup;
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
@@ -336,7 +333,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
u32 const delay_us = 100;
u32 const timeout_us = 5000;
- rc = readl_poll_timeout_atomic(pll->mmio +
+ rc = readl_poll_timeout_atomic(pll->phy->pll_base +
REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,
status,
((status & BIT(0)) > 0),
@@ -351,21 +348,21 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
{
- u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
- dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
+ dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
+ dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
data & ~BIT(5));
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
{
- u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
+ dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
data | BIT(5));
- dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
+ dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
ndelay(250);
}
@@ -373,8 +370,8 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
{
u32 data;
- data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
data & ~BIT(5));
}
@@ -382,8 +379,8 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
{
u32 data;
- data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
data | BIT(5));
}
@@ -404,7 +401,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
}
/* Start PLL */
- dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
+ dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
0x01);
/*
@@ -426,10 +423,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_global_clk(pll_10nm->slave);
- dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
+ dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
0x01);
if (pll_10nm->slave)
- dsi_phy_write(pll_10nm->slave->phy_cmn_mmio +
+ dsi_phy_write(pll_10nm->slave->phy->base +
REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
error:
@@ -438,7 +435,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
{
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
+ dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
dsi_pll_disable_pll_bias(pll);
}
@@ -452,7 +449,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
* powering down the PLL
*/
dsi_pll_disable_global_clk(pll_10nm);
- dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
dsi_pll_disable_sub(pll_10nm);
if (pll_10nm->slave) {
dsi_pll_disable_global_clk(pll_10nm->slave);
@@ -468,7 +465,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
struct dsi_pll_config *config = &pll_10nm->pll_configuration;
- void __iomem *base = pll_10nm->mmio;
+ void __iomem *base = pll_10nm->phy->pll_base;
u64 ref_clk = pll_10nm->vco_ref_clk_rate;
u64 vco_rate = 0x0;
u64 multiplier;
@@ -531,10 +528,10 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
- void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
+ void __iomem *phy_base = pll_10nm->phy->base;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
- cached->pll_out_div = dsi_phy_read(pll_10nm->mmio +
+ cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
cached->pll_out_div &= 0x3;
@@ -554,14 +551,14 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
- void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
+ void __iomem *phy_base = pll_10nm->phy->base;
u32 val;
int ret;
- val = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
val |= cached->pll_out_div;
- dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
+ dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
cached->bit_clk_div | (cached->pix_clk_div << 4));
@@ -586,7 +583,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
- void __iomem *base = pll_10nm->phy_cmn_mmio;
+ void __iomem *base = phy->base;
u32 data = 0x0; /* internal PLL */
DBG("DSI PLL%d", pll_10nm->id);
@@ -645,7 +642,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
- pll_10nm->mmio +
+ pll_10nm->phy->pll_base +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
if (IS_ERR(hw)) {
@@ -659,7 +656,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT,
- pll_10nm->phy_cmn_mmio +
+ pll_10nm->phy->base +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
0, 4, CLK_DIVIDER_ONE_BASED,
&pll_10nm->postdiv_lock);
@@ -710,7 +707,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent, parent2, parent3, parent4
- }), 4, 0, pll_10nm->phy_cmn_mmio +
+ }), 4, 0, pll_10nm->phy->base +
REG_DSI_10nm_PHY_CMN_CLK_CFG1,
0, 2, 0, NULL);
if (IS_ERR(hw)) {
@@ -723,7 +720,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
/* PIX CLK DIV : DIV_CTRL_7_4*/
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
- 0, pll_10nm->phy_cmn_mmio +
+ 0, pll_10nm->phy->base +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
4, 4, CLK_DIVIDER_ONE_BASED,
&pll_10nm->postdiv_lock);
@@ -758,18 +755,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
- pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
- if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return -ENOMEM;
- }
-
- pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
- if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return -ENOMEM;
- }
-
spin_lock_init(&pll_10nm->postdiv_lock);
pll_10nm->phy = phy;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 408192ae1456..5a92c2c1e815 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -118,9 +118,6 @@ struct dsi_pll_14nm {
int id;
struct platform_device *pdev;
- void __iomem *phy_cmn_mmio;
- void __iomem *mmio;
-
struct msm_dsi_phy *phy;
struct dsi_pll_input in;
@@ -167,7 +164,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
u32 nb_tries, u32 timeout_us)
{
bool pll_locked = false;
- void __iomem *base = pll_14nm->mmio;
+ void __iomem *base = pll_14nm->phy->pll_base;
u32 tries, val;
tries = nb_tries;
@@ -380,7 +377,7 @@ static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
struct dsi_pll_input *pin = &pll->in;
struct dsi_pll_output *pout = &pll->out;
u8 data;
@@ -418,7 +415,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
struct dsi_pll_input *pin,
struct dsi_pll_output *pout)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
u8 data;
/* confgiure the non frequency dependent pll registers */
@@ -478,7 +475,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
{
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ void __iomem *cmn_base = pll_14nm->phy->base;
/* de assert pll start and apply pll sw reset */
@@ -497,8 +494,8 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
struct dsi_pll_input *pin,
struct dsi_pll_output *pout)
{
- void __iomem *base = pll->mmio;
- void __iomem *cmn_base = pll->phy_cmn_mmio;
+ void __iomem *base = pll->phy->pll_base;
+ void __iomem *cmn_base = pll->phy->base;
u8 data;
DBG("DSI%d PLL", pll->id);
@@ -614,7 +611,7 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
- void __iomem *base = pll_14nm->mmio;
+ void __iomem *base = pll_14nm->phy->pll_base;
u64 vco_rate, multiplier = BIT(20);
u32 div_frac_start;
u32 dec_start;
@@ -653,8 +650,8 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
- void __iomem *base = pll_14nm->mmio;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ void __iomem *base = pll_14nm->phy->pll_base;
+ void __iomem *cmn_base = pll_14nm->phy->base;
bool locked;
DBG("");
@@ -682,7 +679,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ void __iomem *cmn_base = pll_14nm->phy->base;
DBG("");
@@ -724,7 +721,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
- void __iomem *base = pll_14nm->phy_cmn_mmio;
+ void __iomem *base = pll_14nm->phy->base;
u8 shift = postdiv->shift;
u8 width = postdiv->width;
u32 val;
@@ -757,7 +754,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
- void __iomem *base = pll_14nm->phy_cmn_mmio;
+ void __iomem *base = pll_14nm->phy->base;
spinlock_t *lock = &pll_14nm->postdiv_lock;
u8 shift = postdiv->shift;
u8 width = postdiv->width;
@@ -784,7 +781,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
*/
if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
- void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
+ void __iomem *slave_base = pll_14nm_slave->phy->base;
dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
}
@@ -808,7 +805,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ void __iomem *cmn_base = pll_14nm->phy->base;
u32 data;
data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
@@ -826,7 +823,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ void __iomem *cmn_base = pll_14nm->phy->base;
u32 data;
int ret;
@@ -848,7 +845,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
/* also restore post-dividers for slave DSI PLL */
if (phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
- void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
+ void __iomem *slave_base = pll_14nm_slave->phy->base;
dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
}
@@ -859,7 +856,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
- void __iomem *base = pll_14nm->mmio;
+ void __iomem *base = phy->pll_base;
u32 clkbuflr_en, bandgap = 0;
switch (phy->usecase) {
@@ -1011,18 +1008,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
- pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
- if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return -ENOMEM;
- }
-
- pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
- if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return -ENOMEM;
- }
-
spin_lock_init(&pll_14nm->postdiv_lock);
pll_14nm->phy = phy;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index e964ea210c0b..bdb117938bcc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -72,8 +72,6 @@ struct dsi_pll_28nm {
struct msm_dsi_phy *phy;
- void __iomem *mmio;
-
struct pll_28nm_cached_state cached_state;
};
@@ -86,7 +84,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
u32 val;
while (nb_tries--) {
- val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
+ val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
if (pll_locked)
@@ -101,7 +99,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
{
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
/*
* Add HW recommended delays after toggling the software
@@ -120,7 +118,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
unsigned long div_fbx1000, gen_vco_clk;
u32 refclk_cfg, frac_n_mode, frac_n_value;
u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
@@ -244,7 +242,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
u32 ref_clk = VCO_REF_CLK_RATE;
@@ -291,7 +289,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
{
struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
u32 max_reads = 5, timeout_us = 100;
bool locked;
u32 val;
@@ -385,7 +383,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
bool locked;
u32 max_reads = 10, timeout_us = 50;
u32 val;
@@ -439,7 +437,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
if (unlikely(!pll_28nm->phy->pll_on))
return;
- dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
+ dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
pll_28nm->phy->pll_on = false;
}
@@ -483,7 +481,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
cached_state->postdiv3 =
dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
@@ -500,7 +498,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
int ret;
ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
@@ -551,7 +549,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
parent1, CLK_SET_RATE_PARENT,
- pll_28nm->mmio +
+ pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
0, 4, 0, NULL);
if (IS_ERR(hw))
@@ -568,7 +566,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
- parent1, 0, pll_28nm->mmio +
+ parent1, 0, pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
0, 8, 0, NULL);
if (IS_ERR(hw))
@@ -581,7 +579,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent1, parent2
- }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
+ }), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -613,13 +611,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
pll_28nm->pdev = pdev;
pll_28nm->id = id;
-
- pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
- if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
- return -ENOMEM;
- }
-
pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index faefae5ec23c..36ee3f15d1e0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -64,8 +64,6 @@ struct dsi_pll_28nm {
struct msm_dsi_phy *phy;
- void __iomem *mmio;
-
struct pll_28nm_cached_state cached_state;
};
@@ -78,7 +76,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
u32 val;
while (nb_tries--) {
- val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
+ val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);
pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
if (pll_locked)
@@ -98,7 +96,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
u32 val, temp, fb_divider;
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
@@ -147,7 +145,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
unsigned long vco_rate;
u32 status, fb_divider, temp, ref_divider;
@@ -181,7 +179,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
bool locked;
unsigned int bit_div, byte_div;
int max_reads = 1000, timeout_us = 100;
@@ -234,7 +232,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
if (unlikely(!pll_28nm->phy->pll_on))
return;
- dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
+ dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
pll_28nm->phy->pll_on = false;
}
@@ -348,7 +346,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
cached_state->postdiv3 =
dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
@@ -364,7 +362,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
- void __iomem *base = pll_28nm->mmio;
+ void __iomem *base = pll_28nm->phy->pll_base;
int ret;
ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
@@ -425,7 +423,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
/* prepare and register bytediv */
bytediv->hw.init = &bytediv_init;
- bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
+ bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
@@ -445,7 +443,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
/* DIV3 */
hw = devm_clk_hw_register_divider(dev, clk_name,
- parent_name, 0, pll_28nm->mmio +
+ parent_name, 0, pll_28nm->phy->pll_base +
REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
0, 8, 0, NULL);
if (IS_ERR(hw))
@@ -471,13 +469,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
-
- pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
- if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
- return -ENOMEM;
- }
-
pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index b873b2f67e3a..8e8cf9e63e8f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -91,9 +91,6 @@ struct dsi_pll_7nm {
struct msm_dsi_phy *phy;
- void __iomem *phy_cmn_mmio;
- void __iomem *mmio;
-
u64 vco_ref_clk_rate;
u64 vco_current_rate;
@@ -231,7 +228,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
struct dsi_pll_regs *regs = &pll->reg_setup;
if (pll->pll_configuration.enable_ssc) {
@@ -256,7 +253,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
@@ -298,13 +295,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
- dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
+ dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
}
}
static void dsi_pll_commit(struct dsi_pll_7nm *pll)
{
- void __iomem *base = pll->mmio;
+ void __iomem *base = pll->phy->pll_base;
struct dsi_pll_regs *reg = &pll->reg_setup;
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
@@ -354,7 +351,7 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
u32 const delay_us = 100;
u32 const timeout_us = 5000;
- rc = readl_poll_timeout_atomic(pll->mmio +
+ rc = readl_poll_timeout_atomic(pll->phy->pll_base +
REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
status,
((status & BIT(0)) > 0),
@@ -369,19 +366,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
{
- u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
- dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
+ dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
{
- u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
- dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
+ dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
ndelay(250);
}
@@ -389,18 +386,18 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
{
u32 data;
- data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
+ data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
}
static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
{
u32 data;
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
- data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
+ data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
data | BIT(5) | BIT(4));
}
@@ -411,9 +408,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
* coming out of a CX or analog rail power collapse while
* ensuring that the pads maintain LP00 or LP11 state
*/
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
wmb(); /* Ensure that the reset is deasserted */
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
wmb(); /* Ensure that the reset is deasserted */
}
@@ -427,7 +424,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
dsi_pll_enable_pll_bias(pll_7nm->slave);
/* Start PLL */
- dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
+ dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
/*
* ensure all PLL configurations are written prior to checking
@@ -463,7 +460,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
{
- dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
+ dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
dsi_pll_disable_pll_bias(pll);
}
@@ -477,7 +474,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
* powering down the PLL
*/
dsi_pll_disable_global_clk(pll_7nm);
- dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
+ dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
dsi_pll_disable_sub(pll_7nm);
if (pll_7nm->slave) {
dsi_pll_disable_global_clk(pll_7nm->slave);
@@ -493,7 +490,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
struct dsi_pll_config *config = &pll_7nm->pll_configuration;
- void __iomem *base = pll_7nm->mmio;
+ void __iomem *base = pll_7nm->phy->pll_base;
u64 ref_clk = pll_7nm->vco_ref_clk_rate;
u64 vco_rate = 0x0;
u64 multiplier;
@@ -556,10 +553,10 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
- void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
+ void __iomem *phy_base = pll_7nm->phy->base;
u32 cmn_clk_cfg0, cmn_clk_cfg1;
- cached->pll_out_div = dsi_phy_read(pll_7nm->mmio +
+ cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
cached->pll_out_div &= 0x3;
@@ -579,14 +576,14 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
- void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
+ void __iomem *phy_base = pll_7nm->phy->base;
u32 val;
int ret;
- val = dsi_phy_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
val |= cached->pll_out_div;
- dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
+ dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
cached->bit_clk_div | (cached->pix_clk_div << 4));
@@ -611,7 +608,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
- void __iomem *base = pll_7nm->phy_cmn_mmio;
+ void __iomem *base = phy->base;
u32 data = 0x0; /* internal PLL */
DBG("DSI PLL%d", pll_7nm->id);
@@ -670,7 +667,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
- pll_7nm->mmio +
+ pll_7nm->phy->pll_base +
REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
if (IS_ERR(hw)) {
@@ -684,7 +681,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT,
- pll_7nm->phy_cmn_mmio +
+ pll_7nm->phy->base +
REG_DSI_7nm_PHY_CMN_CLK_CFG0,
0, 4, CLK_DIVIDER_ONE_BASED,
&pll_7nm->postdiv_lock);
@@ -735,7 +732,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent, parent2, parent3, parent4
- }), 4, 0, pll_7nm->phy_cmn_mmio +
+ }), 4, 0, pll_7nm->phy->base +
REG_DSI_7nm_PHY_CMN_CLK_CFG1,
0, 2, 0, NULL);
if (IS_ERR(hw)) {
@@ -748,7 +745,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
/* PIX CLK DIV : DIV_CTRL_7_4*/
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
- 0, pll_7nm->phy_cmn_mmio +
+ 0, pll_7nm->phy->base +
REG_DSI_7nm_PHY_CMN_CLK_CFG0,
4, 4, CLK_DIVIDER_ONE_BASED,
&pll_7nm->postdiv_lock);
@@ -783,18 +780,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
pll_7nm->id = id;
pll_7nm_list[id] = pll_7nm;
- pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
- if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
- return -ENOMEM;
- }
-
- pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
- if (IS_ERR_OR_NULL(pll_7nm->mmio)) {
- DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
- return -ENOMEM;
- }
-
spin_lock_init(&pll_7nm->postdiv_lock);
pll_7nm->phy = phy;
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe
2021-03-27 11:03 ` [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov
@ 2021-03-30 3:18 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> All PHY drivers would map dsi_pll area. Some PHY drivers would also
> map dsi_phy area again (a leftover from old PHY/PLL separation). Move
> all ioremaps to the common dsi_phy driver code and drop individual
> ioremapped areas from PHY drivers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 7 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 75 +++++++-----------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 49 ++++--------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 33 +++-----
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 27 +++----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++-----------
> 7 files changed, 108 insertions(+), 163 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index f21f3babec68..74cc11c84d71 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -682,6 +682,13 @@ static int dsi_phy_driver_probe(struct
> platform_device *pdev)
> goto fail;
> }
>
> + phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> + if (IS_ERR(phy->pll_base)) {
> + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
> + ret = -ENOMEM;
> + goto fail;
> + }
> +
> if (phy->cfg->has_phy_lane) {
> phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
> if (IS_ERR(phy->lane_base)) {
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index d7031a35e2da..8e828c5ca8f4 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -88,6 +88,7 @@ struct msm_dsi_dphy_timing {
> struct msm_dsi_phy {
> struct platform_device *pdev;
> void __iomem *base;
> + void __iomem *pll_base;
> void __iomem *reg_base;
> void __iomem *lane_base;
> int id;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 73afbb597a9f..8a15ae91d44b 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -91,9 +91,6 @@ struct dsi_pll_10nm {
>
> struct msm_dsi_phy *phy;
>
> - void __iomem *phy_cmn_mmio;
> - void __iomem *mmio;
> -
> u64 vco_ref_clk_rate;
> u64 vco_current_rate;
>
> @@ -228,7 +225,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm
> *pll)
>
> static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> struct dsi_pll_regs *regs = &pll->reg_setup;
>
> if (pll->pll_configuration.enable_ssc) {
> @@ -253,7 +250,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm
> *pll)
>
> static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
>
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
> @@ -279,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_10nm *pll)
>
> static void dsi_pll_commit(struct dsi_pll_10nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> struct dsi_pll_regs *reg = &pll->reg_setup;
>
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> @@ -336,7 +333,7 @@ static int dsi_pll_10nm_lock_status(struct
> dsi_pll_10nm *pll)
> u32 const delay_us = 100;
> u32 const timeout_us = 5000;
>
> - rc = readl_poll_timeout_atomic(pll->mmio +
> + rc = readl_poll_timeout_atomic(pll->phy->pll_base +
> REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,
> status,
> ((status & BIT(0)) > 0),
> @@ -351,21 +348,21 @@ static int dsi_pll_10nm_lock_status(struct
> dsi_pll_10nm *pll)
>
> static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
> {
> - u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy->base +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
>
> - dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> + dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES,
> 0);
> + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
> data & ~BIT(5));
> ndelay(250);
> }
>
> static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
> {
> - u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy->base +
> REG_DSI_10nm_PHY_CMN_CTRL_0);
>
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
> + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
> data | BIT(5));
> - dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> + dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES,
> 0xc0);
> ndelay(250);
> }
>
> @@ -373,8 +370,8 @@ static void dsi_pll_disable_global_clk(struct
> dsi_pll_10nm *pll)
> {
> u32 data;
>
> - data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> data & ~BIT(5));
> }
>
> @@ -382,8 +379,8 @@ static void dsi_pll_enable_global_clk(struct
> dsi_pll_10nm *pll)
> {
> u32 data;
>
> - data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> data | BIT(5));
> }
>
> @@ -404,7 +401,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> }
>
> /* Start PLL */
> - dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> 0x01);
>
> /*
> @@ -426,10 +423,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> if (pll_10nm->slave)
> dsi_pll_enable_global_clk(pll_10nm->slave);
>
> - dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
> + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
> 0x01);
> if (pll_10nm->slave)
> - dsi_phy_write(pll_10nm->slave->phy_cmn_mmio +
> + dsi_phy_write(pll_10nm->slave->phy->base +
> REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
>
> error:
> @@ -438,7 +435,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
>
> static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
> {
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
> + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
> dsi_pll_disable_pll_bias(pll);
> }
>
> @@ -452,7 +449,7 @@ static void dsi_pll_10nm_vco_unprepare(struct
> clk_hw *hw)
> * powering down the PLL
> */
> dsi_pll_disable_global_clk(pll_10nm);
> - dsi_phy_write(pll_10nm->phy_cmn_mmio +
> REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
> + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
> 0);
> dsi_pll_disable_sub(pll_10nm);
> if (pll_10nm->slave) {
> dsi_pll_disable_global_clk(pll_10nm->slave);
> @@ -468,7 +465,7 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> struct dsi_pll_config *config = &pll_10nm->pll_configuration;
> - void __iomem *base = pll_10nm->mmio;
> + void __iomem *base = pll_10nm->phy->pll_base;
> u64 ref_clk = pll_10nm->vco_ref_clk_rate;
> u64 vco_rate = 0x0;
> u64 multiplier;
> @@ -531,10 +528,10 @@ static void dsi_10nm_save_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> - void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> + void __iomem *phy_base = pll_10nm->phy->base;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>
> - cached->pll_out_div = dsi_phy_read(pll_10nm->mmio +
> + cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> cached->pll_out_div &= 0x3;
>
> @@ -554,14 +551,14 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
> - void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
> + void __iomem *phy_base = pll_10nm->phy->base;
> u32 val;
> int ret;
>
> - val = dsi_phy_read(pll_10nm->mmio +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> + val = dsi_phy_read(pll_10nm->phy->pll_base +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
> val &= ~0x3;
> val |= cached->pll_out_div;
> - dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
> val);
> + dsi_phy_write(pll_10nm->phy->pll_base +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
>
> dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> cached->bit_clk_div | (cached->pix_clk_div << 4));
> @@ -586,7 +583,7 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
> - void __iomem *base = pll_10nm->phy_cmn_mmio;
> + void __iomem *base = phy->base;
> u32 data = 0x0; /* internal PLL */
>
> DBG("DSI PLL%d", pll_10nm->id);
> @@ -645,7 +642,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
>
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> - pll_10nm->mmio +
> + pll_10nm->phy->pll_base +
> REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
> 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
> if (IS_ERR(hw)) {
> @@ -659,7 +656,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> /* BIT CLK: DIV_CTRL_3_0 */
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> CLK_SET_RATE_PARENT,
> - pll_10nm->phy_cmn_mmio +
> + pll_10nm->phy->base +
> REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> 0, 4, CLK_DIVIDER_ONE_BASED,
> &pll_10nm->postdiv_lock);
> @@ -710,7 +707,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent, parent2, parent3, parent4
> - }), 4, 0, pll_10nm->phy_cmn_mmio +
> + }), 4, 0, pll_10nm->phy->base +
> REG_DSI_10nm_PHY_CMN_CLK_CFG1,
> 0, 2, 0, NULL);
> if (IS_ERR(hw)) {
> @@ -723,7 +720,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> - 0, pll_10nm->phy_cmn_mmio +
> + 0, pll_10nm->phy->base +
> REG_DSI_10nm_PHY_CMN_CLK_CFG0,
> 4, 4, CLK_DIVIDER_ONE_BASED,
> &pll_10nm->postdiv_lock);
> @@ -758,18 +755,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> pll_10nm->id = id;
> pll_10nm_list[id] = pll_10nm;
>
> - pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
> - if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
> - return -ENOMEM;
> - }
> -
> - pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> - if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
> - return -ENOMEM;
> - }
> -
> spin_lock_init(&pll_10nm->postdiv_lock);
>
> pll_10nm->phy = phy;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 408192ae1456..5a92c2c1e815 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -118,9 +118,6 @@ struct dsi_pll_14nm {
> int id;
> struct platform_device *pdev;
>
> - void __iomem *phy_cmn_mmio;
> - void __iomem *mmio;
> -
> struct msm_dsi_phy *phy;
>
> struct dsi_pll_input in;
> @@ -167,7 +164,7 @@ static bool pll_14nm_poll_for_ready(struct
> dsi_pll_14nm *pll_14nm,
> u32 nb_tries, u32 timeout_us)
> {
> bool pll_locked = false;
> - void __iomem *base = pll_14nm->mmio;
> + void __iomem *base = pll_14nm->phy->pll_base;
> u32 tries, val;
>
> tries = nb_tries;
> @@ -380,7 +377,7 @@ static void pll_14nm_calc_vco_count(struct
> dsi_pll_14nm *pll)
>
> static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> struct dsi_pll_input *pin = &pll->in;
> struct dsi_pll_output *pout = &pll->out;
> u8 data;
> @@ -418,7 +415,7 @@ static void pll_db_commit_common(struct
> dsi_pll_14nm *pll,
> struct dsi_pll_input *pin,
> struct dsi_pll_output *pout)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> u8 data;
>
> /* confgiure the non frequency dependent pll registers */
> @@ -478,7 +475,7 @@ static void pll_db_commit_common(struct
> dsi_pll_14nm *pll,
>
> static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
> {
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + void __iomem *cmn_base = pll_14nm->phy->base;
>
> /* de assert pll start and apply pll sw reset */
>
> @@ -497,8 +494,8 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm
> *pll,
> struct dsi_pll_input *pin,
> struct dsi_pll_output *pout)
> {
> - void __iomem *base = pll->mmio;
> - void __iomem *cmn_base = pll->phy_cmn_mmio;
> + void __iomem *base = pll->phy->pll_base;
> + void __iomem *cmn_base = pll->phy->base;
> u8 data;
>
> DBG("DSI%d PLL", pll->id);
> @@ -614,7 +611,7 @@ static unsigned long
> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> - void __iomem *base = pll_14nm->mmio;
> + void __iomem *base = pll_14nm->phy->pll_base;
> u64 vco_rate, multiplier = BIT(20);
> u32 div_frac_start;
> u32 dec_start;
> @@ -653,8 +650,8 @@ static unsigned long
> dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
> static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> - void __iomem *base = pll_14nm->mmio;
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + void __iomem *base = pll_14nm->phy->pll_base;
> + void __iomem *cmn_base = pll_14nm->phy->base;
> bool locked;
>
> DBG("");
> @@ -682,7 +679,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw
> *hw)
> static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + void __iomem *cmn_base = pll_14nm->phy->base;
>
> DBG("");
>
> @@ -724,7 +721,7 @@ static unsigned long
> dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
> {
> struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
> struct dsi_pll_14nm *pll_14nm = postdiv->pll;
> - void __iomem *base = pll_14nm->phy_cmn_mmio;
> + void __iomem *base = pll_14nm->phy->base;
> u8 shift = postdiv->shift;
> u8 width = postdiv->width;
> u32 val;
> @@ -757,7 +754,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
> {
> struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
> struct dsi_pll_14nm *pll_14nm = postdiv->pll;
> - void __iomem *base = pll_14nm->phy_cmn_mmio;
> + void __iomem *base = pll_14nm->phy->base;
> spinlock_t *lock = &pll_14nm->postdiv_lock;
> u8 shift = postdiv->shift;
> u8 width = postdiv->width;
> @@ -784,7 +781,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
> */
> if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
> + void __iomem *slave_base = pll_14nm_slave->phy->base;
>
> dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
> }
> @@ -808,7 +805,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy
> *phy)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + void __iomem *cmn_base = pll_14nm->phy->base;
> u32 data;
>
> data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
> @@ -826,7 +823,7 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
> - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
> + void __iomem *cmn_base = pll_14nm->phy->base;
> u32 data;
> int ret;
>
> @@ -848,7 +845,7 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> /* also restore post-dividers for slave DSI PLL */
> if (phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
> - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
> + void __iomem *slave_base = pll_14nm_slave->phy->base;
>
> dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
> }
> @@ -859,7 +856,7 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
> - void __iomem *base = pll_14nm->mmio;
> + void __iomem *base = phy->pll_base;
> u32 clkbuflr_en, bandgap = 0;
>
> switch (phy->usecase) {
> @@ -1011,18 +1008,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> pll_14nm->id = id;
> pll_14nm_list[id] = pll_14nm;
>
> - pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
> - if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
> - return -ENOMEM;
> - }
> -
> - pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> - if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
> - return -ENOMEM;
> - }
> -
> spin_lock_init(&pll_14nm->postdiv_lock);
>
> pll_14nm->phy = phy;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index e964ea210c0b..bdb117938bcc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -72,8 +72,6 @@ struct dsi_pll_28nm {
>
> struct msm_dsi_phy *phy;
>
> - void __iomem *mmio;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -86,7 +84,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
> u32 val;
>
> while (nb_tries--) {
> - val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
> + val = dsi_phy_read(pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_STATUS);
> pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
>
> if (pll_locked)
> @@ -101,7 +99,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
>
> static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
> {
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
>
> /*
> * Add HW recommended delays after toggling the software
> @@ -120,7 +118,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> unsigned long div_fbx1000, gen_vco_clk;
> u32 refclk_cfg, frac_n_mode, frac_n_value;
> u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
> @@ -244,7 +242,7 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> u32 sdm0, doubler, sdm_byp_div;
> u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> u32 ref_clk = VCO_REF_CLK_RATE;
> @@ -291,7 +289,7 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm
> *pll_28nm)
> {
> struct device *dev = &pll_28nm->pdev->dev;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> u32 max_reads = 5, timeout_us = 100;
> bool locked;
> u32 val;
> @@ -385,7 +383,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct
> clk_hw *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> bool locked;
> u32 max_reads = 10, timeout_us = 50;
> u32 val;
> @@ -439,7 +437,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> - dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
> + dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG,
> 0x00);
>
> pll_28nm->phy->pll_on = false;
> }
> @@ -483,7 +481,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy
> *phy)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
>
> cached_state->postdiv3 =
> dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
> @@ -500,7 +498,7 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> int ret;
>
> ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> @@ -551,7 +549,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT,
> - pll_28nm->mmio +
> + pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
> 0, 4, 0, NULL);
> if (IS_ERR(hw))
> @@ -568,7 +566,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> hw = devm_clk_hw_register_divider(dev, clk_name,
> - parent1, 0, pll_28nm->mmio +
> + parent1, 0, pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> 0, 8, 0, NULL);
> if (IS_ERR(hw))
> @@ -581,7 +579,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent1, parent2
> - }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
> + }), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
> @@ -613,13 +611,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
>
> pll_28nm->pdev = pdev;
> pll_28nm->id = id;
> -
> - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> - if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
> - return -ENOMEM;
> - }
> -
> pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index faefae5ec23c..36ee3f15d1e0 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -64,8 +64,6 @@ struct dsi_pll_28nm {
>
> struct msm_dsi_phy *phy;
>
> - void __iomem *mmio;
> -
> struct pll_28nm_cached_state cached_state;
> };
>
> @@ -78,7 +76,7 @@ static bool pll_28nm_poll_for_ready(struct
> dsi_pll_28nm *pll_28nm,
> u32 val;
>
> while (nb_tries--) {
> - val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
> + val = dsi_phy_read(pll_28nm->phy->pll_base +
> REG_DSI_28nm_8960_PHY_PLL_RDY);
> pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
>
> if (pll_locked)
> @@ -98,7 +96,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
> unsigned long parent_rate)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> u32 val, temp, fb_divider;
>
> DBG("rate=%lu, parent's=%lu", rate, parent_rate);
> @@ -147,7 +145,7 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> unsigned long vco_rate;
> u32 status, fb_divider, temp, ref_divider;
>
> @@ -181,7 +179,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw
> *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> struct device *dev = &pll_28nm->pdev->dev;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> bool locked;
> unsigned int bit_div, byte_div;
> int max_reads = 1000, timeout_us = 100;
> @@ -234,7 +232,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
>
> - dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
> 0x00);
> + dsi_phy_write(pll_28nm->phy->pll_base +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
>
> pll_28nm->phy->pll_on = false;
> }
> @@ -348,7 +346,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy
> *phy)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
>
> cached_state->postdiv3 =
> dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
> @@ -364,7 +362,7 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
> struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
> - void __iomem *base = pll_28nm->mmio;
> + void __iomem *base = pll_28nm->phy->pll_base;
> int ret;
>
> ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> @@ -425,7 +423,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>
> /* prepare and register bytediv */
> bytediv->hw.init = &bytediv_init;
> - bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
> + bytediv->reg = pll_28nm->phy->pll_base +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
>
> snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
> snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
> @@ -445,7 +443,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> /* DIV3 */
> hw = devm_clk_hw_register_divider(dev, clk_name,
> - parent_name, 0, pll_28nm->mmio +
> + parent_name, 0, pll_28nm->phy->pll_base +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
> 0, 8, 0, NULL);
> if (IS_ERR(hw))
> @@ -471,13 +469,6 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
>
> pll_28nm->pdev = pdev;
> pll_28nm->id = id + 1;
> -
> - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> - if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
> - return -ENOMEM;
> - }
> -
> pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index b873b2f67e3a..8e8cf9e63e8f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -91,9 +91,6 @@ struct dsi_pll_7nm {
>
> struct msm_dsi_phy *phy;
>
> - void __iomem *phy_cmn_mmio;
> - void __iomem *mmio;
> -
> u64 vco_ref_clk_rate;
> u64 vco_current_rate;
>
> @@ -231,7 +228,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm
> *pll)
>
> static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> struct dsi_pll_regs *regs = &pll->reg_setup;
>
> if (pll->pll_configuration.enable_ssc) {
> @@ -256,7 +253,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm
> *pll)
>
> static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>
> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> @@ -298,13 +295,13 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_7nm *pll)
> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> if (pll->slave)
> - dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE,
> 0x22);
> + dsi_phy_write(pll->slave->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> }
> }
>
> static void dsi_pll_commit(struct dsi_pll_7nm *pll)
> {
> - void __iomem *base = pll->mmio;
> + void __iomem *base = pll->phy->pll_base;
> struct dsi_pll_regs *reg = &pll->reg_setup;
>
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> @@ -354,7 +351,7 @@ static int dsi_pll_7nm_lock_status(struct
> dsi_pll_7nm *pll)
> u32 const delay_us = 100;
> u32 const timeout_us = 5000;
>
> - rc = readl_poll_timeout_atomic(pll->mmio +
> + rc = readl_poll_timeout_atomic(pll->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
> status,
> ((status & BIT(0)) > 0),
> @@ -369,19 +366,19 @@ static int dsi_pll_7nm_lock_status(struct
> dsi_pll_7nm *pll)
>
> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> {
> - u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> - dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data &
> ~BIT(5));
> + dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES,
> 0);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data &
> ~BIT(5));
> ndelay(250);
> }
>
> static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
> {
> - u32 data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CTRL_0);
> + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data |
> BIT(5));
> - dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data |
> BIT(5));
> + dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES,
> 0xc0);
> ndelay(250);
> }
>
> @@ -389,18 +386,18 @@ static void dsi_pll_disable_global_clk(struct
> dsi_pll_7nm *pll)
> {
> u32 data;
>
> - data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data
> & ~BIT(5));
> + data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data &
> ~BIT(5));
> }
>
> static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
> {
> u32 data;
>
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
>
> - data = dsi_phy_read(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> + data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> data | BIT(5) | BIT(4));
> }
>
> @@ -411,9 +408,9 @@ static void dsi_pll_phy_dig_reset(struct
> dsi_pll_7nm *pll)
> * coming out of a CX or analog rail power collapse while
> * ensuring that the pads maintain LP00 or LP11 state
> */
> - dsi_phy_write(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
> + dsi_phy_write(pll->phy->base +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
> wmb(); /* Ensure that the reset is deasserted */
> - dsi_phy_write(pll->phy_cmn_mmio +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
> + dsi_phy_write(pll->phy->base +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
> wmb(); /* Ensure that the reset is deasserted */
> }
>
> @@ -427,7 +424,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
> dsi_pll_enable_pll_bias(pll_7nm->slave);
>
> /* Start PLL */
> - dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0x01);
> + dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0x01);
>
> /*
> * ensure all PLL configurations are written prior to checking
> @@ -463,7 +460,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
>
> static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
> {
> - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
> + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
> dsi_pll_disable_pll_bias(pll);
> }
>
> @@ -477,7 +474,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw
> *hw)
> * powering down the PLL
> */
> dsi_pll_disable_global_clk(pll_7nm);
> - dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL,
> 0);
> + dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
> dsi_pll_disable_sub(pll_7nm);
> if (pll_7nm->slave) {
> dsi_pll_disable_global_clk(pll_7nm->slave);
> @@ -493,7 +490,7 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> struct dsi_pll_config *config = &pll_7nm->pll_configuration;
> - void __iomem *base = pll_7nm->mmio;
> + void __iomem *base = pll_7nm->phy->pll_base;
> u64 ref_clk = pll_7nm->vco_ref_clk_rate;
> u64 vco_rate = 0x0;
> u64 multiplier;
> @@ -556,10 +553,10 @@ static void dsi_7nm_save_state(struct msm_dsi_phy
> *phy)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> - void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> + void __iomem *phy_base = pll_7nm->phy->base;
> u32 cmn_clk_cfg0, cmn_clk_cfg1;
>
> - cached->pll_out_div = dsi_phy_read(pll_7nm->mmio +
> + cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> cached->pll_out_div &= 0x3;
>
> @@ -579,14 +576,14 @@ static int dsi_7nm_restore_state(struct
> msm_dsi_phy *phy)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
> - void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
> + void __iomem *phy_base = pll_7nm->phy->base;
> u32 val;
> int ret;
>
> - val = dsi_phy_read(pll_7nm->mmio +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> + val = dsi_phy_read(pll_7nm->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
> val &= ~0x3;
> val |= cached->pll_out_div;
> - dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
> val);
> + dsi_phy_write(pll_7nm->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
>
> dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> cached->bit_clk_div | (cached->pix_clk_div << 4));
> @@ -611,7 +608,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy
> *phy)
> static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
> - void __iomem *base = pll_7nm->phy_cmn_mmio;
> + void __iomem *base = phy->base;
> u32 data = 0x0; /* internal PLL */
>
> DBG("DSI PLL%d", pll_7nm->id);
> @@ -670,7 +667,7 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
>
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> - pll_7nm->mmio +
> + pll_7nm->phy->pll_base +
> REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
> 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
> if (IS_ERR(hw)) {
> @@ -684,7 +681,7 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> /* BIT CLK: DIV_CTRL_3_0 */
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> CLK_SET_RATE_PARENT,
> - pll_7nm->phy_cmn_mmio +
> + pll_7nm->phy->base +
> REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> 0, 4, CLK_DIVIDER_ONE_BASED,
> &pll_7nm->postdiv_lock);
> @@ -735,7 +732,7 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent, parent2, parent3, parent4
> - }), 4, 0, pll_7nm->phy_cmn_mmio +
> + }), 4, 0, pll_7nm->phy->base +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> 0, 2, 0, NULL);
> if (IS_ERR(hw)) {
> @@ -748,7 +745,7 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> - 0, pll_7nm->phy_cmn_mmio +
> + 0, pll_7nm->phy->base +
> REG_DSI_7nm_PHY_CMN_CLK_CFG0,
> 4, 4, CLK_DIVIDER_ONE_BASED,
> &pll_7nm->postdiv_lock);
> @@ -783,18 +780,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> pll_7nm->id = id;
> pll_7nm_list[id] = pll_7nm;
>
> - pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
> - if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
> - return -ENOMEM;
> - }
> -
> - pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
> - if (IS_ERR_OR_NULL(pll_7nm->mmio)) {
> - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
> - return -ENOMEM;
> - }
> -
> spin_lock_init(&pll_7nm->postdiv_lock);
>
> pll_7nm->phy = phy;
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (19 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 3:23 ` abhinavk
2021-03-27 11:03 ` [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov
` (3 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse
those fields from the provided msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 72 +++++++++----------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 54 +++++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 48 ++++++-------
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 26 +++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 68 ++++++++----------
5 files changed, 119 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 8a15ae91d44b..b937e77b3c37 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -86,9 +86,6 @@ struct pll_10nm_cached_state {
struct dsi_pll_10nm {
struct clk_hw clk_hw;
- int id;
- struct platform_device *pdev;
-
struct msm_dsi_phy *phy;
u64 vco_ref_clk_rate;
@@ -301,7 +298,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
- DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
+ DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
parent_rate);
pll_10nm->vco_current_rate = rate;
@@ -327,7 +324,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
{
- struct device *dev = &pll->pdev->dev;
+ struct device *dev = &pll->phy->pdev->dev;
int rc;
u32 status = 0;
u32 const delay_us = 100;
@@ -341,7 +338,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
timeout_us);
if (rc)
DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n",
- pll->id, status);
+ pll->phy->id, status);
return rc;
}
@@ -387,7 +384,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
- struct device *dev = &pll_10nm->pdev->dev;
+ struct device *dev = &pll_10nm->phy->pdev->dev;
int rc;
dsi_pll_enable_pll_bias(pll_10nm);
@@ -413,7 +410,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
/* Check for PLL lock */
rc = dsi_pll_10nm_lock_status(pll_10nm);
if (rc) {
- DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id);
+ DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id);
goto error;
}
@@ -494,7 +491,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
vco_rate = pll_freq;
DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
- pll_10nm->id, (unsigned long)vco_rate, dec, frac);
+ pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
return (unsigned long)vco_rate;
}
@@ -543,7 +540,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy)
cached->pll_mux = cmn_clk_cfg1 & 0x3;
DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
- pll_10nm->id, cached->pll_out_div, cached->bit_clk_div,
+ pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
cached->pix_clk_div, cached->pll_mux);
}
@@ -570,12 +567,12 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
if (ret) {
- DRM_DEV_ERROR(&pll_10nm->pdev->dev,
+ DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
- DBG("DSI PLL%d", pll_10nm->id);
+ DBG("DSI PLL%d", pll_10nm->phy->id);
return 0;
}
@@ -586,13 +583,13 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
void __iomem *base = phy->base;
u32 data = 0x0; /* internal PLL */
- DBG("DSI PLL%d", pll_10nm->id);
+ DBG("DSI PLL%d", pll_10nm->phy->id);
switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
break;
case MSM_DSI_PHY_MASTER:
- pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX];
+ pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX];
break;
case MSM_DSI_PHY_SLAVE:
data = 0x1; /* external PLL */
@@ -624,21 +621,21 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_10nm_vco,
};
- struct device *dev = &pll_10nm->pdev->dev;
+ struct device *dev = &pll_10nm->phy->pdev->dev;
struct clk_hw *hw;
int ret;
- DBG("DSI%d", pll_10nm->id);
+ DBG("DSI%d", pll_10nm->phy->id);
- snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
+ snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
pll_10nm->clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
if (ret)
return ret;
- snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
- snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
@@ -650,8 +647,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -665,8 +662,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
@@ -678,8 +675,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
- snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 2);
@@ -688,8 +685,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 4);
@@ -698,11 +695,11 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
- snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
- snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
- snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+ snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
+ snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+ snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
@@ -715,8 +712,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
- snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
+ snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
/* PIX CLK DIV : DIV_CTRL_7_4*/
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -741,7 +738,6 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
- int id = phy->id;
struct dsi_pll_10nm *pll_10nm;
int ret;
@@ -749,11 +745,9 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
if (!pll_10nm)
return -ENOMEM;
- DBG("DSI PLL%d", id);
+ DBG("DSI PLL%d", phy->id);
- pll_10nm->pdev = pdev;
- pll_10nm->id = id;
- pll_10nm_list[id] = pll_10nm;
+ pll_10nm_list[phy->id] = pll_10nm;
spin_lock_init(&pll_10nm->postdiv_lock);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 5a92c2c1e815..8b4865c5796d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -115,9 +115,6 @@ struct pll_14nm_cached_state {
struct dsi_pll_14nm {
struct clk_hw clk_hw;
- int id;
- struct platform_device *pdev;
-
struct msm_dsi_phy *phy;
struct dsi_pll_input in;
@@ -498,7 +495,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
void __iomem *cmn_base = pll->phy->base;
u8 data;
- DBG("DSI%d PLL", pll->id);
+ DBG("DSI%d PLL", pll->phy->id);
data = pout->cmn_ldo_cntrl;
dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
@@ -565,7 +562,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
struct dsi_pll_input *pin = &pll_14nm->in;
struct dsi_pll_output *pout = &pll_14nm->out;
- DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
+ DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
@@ -666,7 +663,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
POLL_TIMEOUT_US);
if (unlikely(!locked)) {
- DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
+ DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n");
return -EINVAL;
}
@@ -726,7 +723,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
u8 width = postdiv->width;
u32 val;
- DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
+ DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
val &= div_mask(width);
@@ -742,7 +739,7 @@ static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
- DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
+ DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);
return divider_round_rate(hw, rate, prate, NULL,
postdiv->width,
@@ -762,7 +759,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long flags = 0;
u32 val;
- DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
+ DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate,
parent_rate);
value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
@@ -813,7 +810,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy)
cached_state->n1postdiv = data & 0xf;
cached_state->n2postdiv = (data >> 4) & 0xf;
- DBG("DSI%d PLL save state %x %x", pll_14nm->id,
+ DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id,
cached_state->n1postdiv, cached_state->n2postdiv);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
@@ -830,14 +827,14 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy)
ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
- DRM_DEV_ERROR(&pll_14nm->pdev->dev,
+ DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
- DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
+ DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
cached_state->n1postdiv, cached_state->n2postdiv);
dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
@@ -865,7 +862,7 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
break;
case MSM_DSI_PHY_MASTER:
clkbuflr_en = 0x3;
- pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
+ pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX];
break;
case MSM_DSI_PHY_SLAVE:
clkbuflr_en = 0x0;
@@ -889,7 +886,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
u8 shift)
{
struct dsi_pll_14nm_postdiv *pll_postdiv;
- struct device *dev = &pll_14nm->pdev->dev;
+ struct device *dev = &pll_14nm->phy->pdev->dev;
struct clk_init_data postdiv_init = {
.parent_names = (const char *[]) { parent_name },
.num_parents = 1,
@@ -928,21 +925,21 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_14nm_vco,
};
- struct device *dev = &pll_14nm->pdev->dev;
+ struct device *dev = &pll_14nm->phy->pdev->dev;
struct clk_hw *hw;
int ret;
- DBG("DSI%d", pll_14nm->id);
+ DBG("DSI%d", pll_14nm->phy->id);
- snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
+ snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id);
pll_14nm->clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
if (ret)
return ret;
- snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
- snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
+ snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
+ snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id);
/* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
@@ -950,8 +947,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
- snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
+ snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id);
+ snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
/* DSI Byte clock = VCO_CLK / N1 / 8 */
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
@@ -961,8 +958,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
- snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
- snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
+ snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
+ snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
/*
* Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
@@ -972,8 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
- snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
+ snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id);
+ snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
/* DSI pixel clock = VCO_CLK / N1 / 2 / N2
* This is the output of N2 post-divider, bits 4-7 in
@@ -991,7 +988,6 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
- int id = phy->id;
struct dsi_pll_14nm *pll_14nm;
int ret;
@@ -1002,11 +998,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
if (!pll_14nm)
return -ENOMEM;
- DBG("PLL%d", id);
+ DBG("PLL%d", phy->id);
- pll_14nm->pdev = pdev;
- pll_14nm->id = id;
- pll_14nm_list[id] = pll_14nm;
+ pll_14nm_list[phy->id] = pll_14nm;
spin_lock_init(&pll_14nm->postdiv_lock);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index bdb117938bcc..0bcea3f3eca3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -67,9 +67,6 @@ struct pll_28nm_cached_state {
struct dsi_pll_28nm {
struct clk_hw clk_hw;
- int id;
- struct platform_device *pdev;
-
struct msm_dsi_phy *phy;
struct pll_28nm_cached_state cached_state;
@@ -117,7 +114,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
void __iomem *base = pll_28nm->phy->pll_base;
unsigned long div_fbx1000, gen_vco_clk;
u32 refclk_cfg, frac_n_mode, frac_n_value;
@@ -288,14 +285,14 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
{
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
void __iomem *base = pll_28nm->phy->pll_base;
u32 max_reads = 5, timeout_us = 100;
bool locked;
u32 val;
int i;
- DBG("id=%d", pll_28nm->id);
+ DBG("id=%d", pll_28nm->phy->id);
pll_28nm_software_reset(pll_28nm);
@@ -382,13 +379,13 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
void __iomem *base = pll_28nm->phy->pll_base;
bool locked;
u32 max_reads = 10, timeout_us = 50;
u32 val;
- DBG("id=%d", pll_28nm->id);
+ DBG("id=%d", pll_28nm->phy->id);
if (unlikely(pll_28nm->phy->pll_on))
return 0;
@@ -432,7 +429,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- DBG("id=%d", pll_28nm->id);
+ DBG("id=%d", pll_28nm->phy->id);
if (unlikely(!pll_28nm->phy->pll_on))
return;
@@ -504,7 +501,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
- DRM_DEV_ERROR(&pll_28nm->pdev->dev,
+ DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
@@ -528,25 +525,25 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
};
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
struct clk_hw *hw;
int ret;
- DBG("%d", pll_28nm->id);
+ DBG("%d", pll_28nm->phy->id);
if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
else
vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
- snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
+ snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
pll_28nm->clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
if (ret)
return ret;
- snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
- snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
+ snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
parent1, CLK_SET_RATE_PARENT,
pll_28nm->phy->pll_base +
@@ -555,16 +552,16 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
- snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);
+ snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
parent1, CLK_SET_RATE_PARENT,
1, 2);
if (IS_ERR(hw))
return PTR_ERR(hw);
- snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
- snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
+ snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
parent1, 0, pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
@@ -573,9 +570,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
return PTR_ERR(hw);
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
- snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
- snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
- snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
+ snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
+ snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent1, parent2
@@ -584,8 +581,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
if (IS_ERR(hw))
return PTR_ERR(hw);
- snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
- snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
+ snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
parent1, CLK_SET_RATE_PARENT, 1, 4);
if (IS_ERR(hw))
@@ -598,7 +595,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
- int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
int ret;
@@ -609,8 +605,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
if (!pll_28nm)
return -ENOMEM;
- pll_28nm->pdev = pdev;
- pll_28nm->id = id;
pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 36ee3f15d1e0..9ddd0adccce3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -59,9 +59,6 @@ struct clk_bytediv {
struct dsi_pll_28nm {
struct clk_hw clk_hw;
- int id;
- struct platform_device *pdev;
-
struct msm_dsi_phy *phy;
struct pll_28nm_cached_state cached_state;
@@ -178,14 +175,14 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
void __iomem *base = pll_28nm->phy->pll_base;
bool locked;
unsigned int bit_div, byte_div;
int max_reads = 1000, timeout_us = 100;
u32 val;
- DBG("id=%d", pll_28nm->id);
+ DBG("id=%d", pll_28nm->phy->id);
if (unlikely(pll_28nm->phy->pll_on))
return 0;
@@ -227,7 +224,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
- DBG("id=%d", pll_28nm->id);
+ DBG("id=%d", pll_28nm->phy->id);
if (unlikely(!pll_28nm->phy->pll_on))
return;
@@ -368,7 +365,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy)
ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
- DRM_DEV_ERROR(&pll_28nm->pdev->dev,
+ DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
@@ -392,13 +389,13 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_28nm_vco,
};
- struct device *dev = &pll_28nm->pdev->dev;
+ struct device *dev = &pll_28nm->phy->pdev->dev;
struct clk_hw *hw;
struct clk_bytediv *bytediv;
struct clk_init_data bytediv_init = { };
int ret;
- DBG("%d", pll_28nm->id);
+ DBG("%d", pll_28nm->phy->id);
bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL);
if (!bytediv)
@@ -412,7 +409,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
if (!clk_name)
return -ENOMEM;
- snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
+ snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
vco_init.name = vco_name;
pll_28nm->clk_hw.init = &vco_init;
@@ -425,8 +422,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
bytediv->hw.init = &bytediv_init;
bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
- snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
- snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
+ snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
+ snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
bytediv_init.name = clk_name;
bytediv_init.ops = &clk_bytediv_ops;
@@ -440,7 +437,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
return ret;
provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;
- snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
+ snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
/* DIV3 */
hw = devm_clk_hw_register_divider(dev, clk_name,
parent_name, 0, pll_28nm->phy->pll_base +
@@ -456,7 +453,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
- int id = phy->id;
struct dsi_pll_28nm *pll_28nm;
int ret;
@@ -467,8 +463,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
if (!pll_28nm)
return -ENOMEM;
- pll_28nm->pdev = pdev;
- pll_28nm->id = id + 1;
pll_28nm->phy = phy;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 8e8cf9e63e8f..4df237ad0eaf 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -86,9 +86,6 @@ struct pll_7nm_cached_state {
struct dsi_pll_7nm {
struct clk_hw clk_hw;
- int id;
- struct platform_device *pdev;
-
struct msm_dsi_phy *phy;
u64 vco_ref_clk_rate;
@@ -320,7 +317,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
- DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
+ DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
parent_rate);
pll_7nm->vco_current_rate = rate;
@@ -359,7 +356,7 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
timeout_us);
if (rc)
pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
- pll->id, status);
+ pll->phy->id, status);
return rc;
}
@@ -435,7 +432,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
/* Check for PLL lock */
rc = dsi_pll_7nm_lock_status(pll_7nm);
if (rc) {
- pr_err("PLL(%d) lock failed\n", pll_7nm->id);
+ pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
goto error;
}
@@ -519,7 +516,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
vco_rate = pll_freq;
DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
- pll_7nm->id, (unsigned long)vco_rate, dec, frac);
+ pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
return (unsigned long)vco_rate;
}
@@ -568,7 +565,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy)
cached->pll_mux = cmn_clk_cfg1 & 0x3;
DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
- pll_7nm->id, cached->pll_out_div, cached->bit_clk_div,
+ pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
cached->pix_clk_div, cached->pll_mux);
}
@@ -595,12 +592,12 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
if (ret) {
- DRM_DEV_ERROR(&pll_7nm->pdev->dev,
+ DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
- DBG("DSI PLL%d", pll_7nm->id);
+ DBG("DSI PLL%d", pll_7nm->phy->id);
return 0;
}
@@ -611,13 +608,13 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
void __iomem *base = phy->base;
u32 data = 0x0; /* internal PLL */
- DBG("DSI PLL%d", pll_7nm->id);
+ DBG("DSI PLL%d", pll_7nm->phy->id);
switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
break;
case MSM_DSI_PHY_MASTER:
- pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX];
+ pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
break;
case MSM_DSI_PHY_SLAVE:
data = 0x1; /* external PLL */
@@ -649,21 +646,21 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_7nm_vco,
};
- struct device *dev = &pll_7nm->pdev->dev;
+ struct device *dev = &pll_7nm->phy->pdev->dev;
struct clk_hw *hw;
int ret;
- DBG("DSI%d", pll_7nm->id);
+ DBG("DSI%d", pll_7nm->phy->id);
- snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
+ snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id);
pll_7nm->clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
if (ret)
return ret;
- snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
- snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);
hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
@@ -675,8 +672,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -690,8 +687,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
@@ -703,8 +700,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
- snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 2);
@@ -713,8 +710,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 4);
@@ -723,11 +720,11 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
- snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
- snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
- snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
+ snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
+ snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
+ snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
@@ -740,8 +737,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
goto fail;
}
- snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id);
- snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id);
+ snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
+ snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
/* PIX CLK DIV : DIV_CTRL_7_4*/
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -766,7 +763,6 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
- int id = phy->id;
struct dsi_pll_7nm *pll_7nm;
int ret;
@@ -774,11 +770,9 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
if (!pll_7nm)
return -ENOMEM;
- DBG("DSI PLL%d", id);
+ DBG("DSI PLL%d", phy->id);
- pll_7nm->pdev = pdev;
- pll_7nm->id = id;
- pll_7nm_list[id] = pll_7nm;
+ pll_7nm_list[phy->id] = pll_7nm;
spin_lock_init(&pll_7nm->postdiv_lock);
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances
2021-03-27 11:03 ` [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov
@ 2021-03-30 3:23 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie, freedreno,
linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse
> those fields from the provided msm_dsi_phy.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 72 +++++++++----------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 54 +++++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 48 ++++++-------
> .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 26 +++----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 68 ++++++++----------
> 5 files changed, 119 insertions(+), 149 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 8a15ae91d44b..b937e77b3c37 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -86,9 +86,6 @@ struct pll_10nm_cached_state {
> struct dsi_pll_10nm {
> struct clk_hw clk_hw;
>
> - int id;
> - struct platform_device *pdev;
> -
> struct msm_dsi_phy *phy;
>
> u64 vco_ref_clk_rate;
> @@ -301,7 +298,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>
> - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
> + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
> parent_rate);
>
> pll_10nm->vco_current_rate = rate;
> @@ -327,7 +324,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
>
> static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
> {
> - struct device *dev = &pll->pdev->dev;
> + struct device *dev = &pll->phy->pdev->dev;
> int rc;
> u32 status = 0;
> u32 const delay_us = 100;
> @@ -341,7 +338,7 @@ static int dsi_pll_10nm_lock_status(struct
> dsi_pll_10nm *pll)
> timeout_us);
> if (rc)
> DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n",
> - pll->id, status);
> + pll->phy->id, status);
>
> return rc;
> }
> @@ -387,7 +384,7 @@ static void dsi_pll_enable_global_clk(struct
> dsi_pll_10nm *pll)
> static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> - struct device *dev = &pll_10nm->pdev->dev;
> + struct device *dev = &pll_10nm->phy->pdev->dev;
> int rc;
>
> dsi_pll_enable_pll_bias(pll_10nm);
> @@ -413,7 +410,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw
> *hw)
> /* Check for PLL lock */
> rc = dsi_pll_10nm_lock_status(pll_10nm);
> if (rc) {
> - DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id);
> + DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id);
> goto error;
> }
>
> @@ -494,7 +491,7 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> vco_rate = pll_freq;
>
> DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
> - pll_10nm->id, (unsigned long)vco_rate, dec, frac);
> + pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
>
> return (unsigned long)vco_rate;
> }
> @@ -543,7 +540,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy
> *phy)
> cached->pll_mux = cmn_clk_cfg1 & 0x3;
>
> DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
> - pll_10nm->id, cached->pll_out_div, cached->bit_clk_div,
> + pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
> cached->pix_clk_div, cached->pll_mux);
> }
>
> @@ -570,12 +567,12 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
>
> ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> if (ret) {
> - DRM_DEV_ERROR(&pll_10nm->pdev->dev,
> + DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> return ret;
> }
>
> - DBG("DSI PLL%d", pll_10nm->id);
> + DBG("DSI PLL%d", pll_10nm->phy->id);
>
> return 0;
> }
> @@ -586,13 +583,13 @@ static int dsi_10nm_set_usecase(struct
> msm_dsi_phy *phy)
> void __iomem *base = phy->base;
> u32 data = 0x0; /* internal PLL */
>
> - DBG("DSI PLL%d", pll_10nm->id);
> + DBG("DSI PLL%d", pll_10nm->phy->id);
>
> switch (phy->usecase) {
> case MSM_DSI_PHY_STANDALONE:
> break;
> case MSM_DSI_PHY_MASTER:
> - pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX];
> + pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX];
> break;
> case MSM_DSI_PHY_SLAVE:
> data = 0x1; /* external PLL */
> @@ -624,21 +621,21 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> .flags = CLK_IGNORE_UNUSED,
> .ops = &clk_ops_dsi_pll_10nm_vco,
> };
> - struct device *dev = &pll_10nm->pdev->dev;
> + struct device *dev = &pll_10nm->phy->pdev->dev;
> struct clk_hw *hw;
> int ret;
>
> - DBG("DSI%d", pll_10nm->id);
> + DBG("DSI%d", pll_10nm->phy->id);
>
> - snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
> + snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
> pll_10nm->clk_hw.init = &vco_init;
>
> ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
> if (ret)
> return ret;
>
> - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> @@ -650,8 +647,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
>
> /* BIT CLK: DIV_CTRL_3_0 */
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> @@ -665,8 +662,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk",
> pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> @@ -678,8 +675,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
>
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 2);
> @@ -688,8 +685,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk",
> pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 4);
> @@ -698,11 +695,11 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
> - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
> - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
> - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
> + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
> + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
> + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk",
> pll_10nm->phy->id);
>
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> @@ -715,8 +712,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
> - snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk",
> pll_10nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> @@ -741,7 +738,6 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm, struct clk_hw **prov
> static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
> {
> struct platform_device *pdev = phy->pdev;
> - int id = phy->id;
> struct dsi_pll_10nm *pll_10nm;
> int ret;
>
> @@ -749,11 +745,9 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> if (!pll_10nm)
> return -ENOMEM;
>
> - DBG("DSI PLL%d", id);
> + DBG("DSI PLL%d", phy->id);
>
> - pll_10nm->pdev = pdev;
> - pll_10nm->id = id;
> - pll_10nm_list[id] = pll_10nm;
> + pll_10nm_list[phy->id] = pll_10nm;
>
> spin_lock_init(&pll_10nm->postdiv_lock);
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 5a92c2c1e815..8b4865c5796d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -115,9 +115,6 @@ struct pll_14nm_cached_state {
> struct dsi_pll_14nm {
> struct clk_hw clk_hw;
>
> - int id;
> - struct platform_device *pdev;
> -
> struct msm_dsi_phy *phy;
>
> struct dsi_pll_input in;
> @@ -498,7 +495,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm
> *pll,
> void __iomem *cmn_base = pll->phy->base;
> u8 data;
>
> - DBG("DSI%d PLL", pll->id);
> + DBG("DSI%d PLL", pll->phy->id);
>
> data = pout->cmn_ldo_cntrl;
> dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
> @@ -565,7 +562,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
> struct dsi_pll_input *pin = &pll_14nm->in;
> struct dsi_pll_output *pout = &pll_14nm->out;
>
> - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
> + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
> parent_rate);
>
> pll_14nm->vco_current_rate = rate;
> @@ -666,7 +663,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw
> *hw)
> POLL_TIMEOUT_US);
>
> if (unlikely(!locked)) {
> - DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
> + DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n");
> return -EINVAL;
> }
>
> @@ -726,7 +723,7 @@ static unsigned long
> dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
> u8 width = postdiv->width;
> u32 val;
>
> - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
> + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
>
> val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
> val &= div_mask(width);
> @@ -742,7 +739,7 @@ static long dsi_pll_14nm_postdiv_round_rate(struct
> clk_hw *hw,
> struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
> struct dsi_pll_14nm *pll_14nm = postdiv->pll;
>
> - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
> + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);
>
> return divider_round_rate(hw, rate, prate, NULL,
> postdiv->width,
> @@ -762,7 +759,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct
> clk_hw *hw, unsigned long rate,
> unsigned long flags = 0;
> u32 val;
>
> - DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
> + DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id,
> rate,
> parent_rate);
>
> value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
> @@ -813,7 +810,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy
> *phy)
> cached_state->n1postdiv = data & 0xf;
> cached_state->n2postdiv = (data >> 4) & 0xf;
>
> - DBG("DSI%d PLL save state %x %x", pll_14nm->id,
> + DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id,
> cached_state->n1postdiv, cached_state->n2postdiv);
>
> cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
> @@ -830,14 +827,14 @@ static int dsi_14nm_restore_state(struct
> msm_dsi_phy *phy)
> ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> - DRM_DEV_ERROR(&pll_14nm->pdev->dev,
> + DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> return ret;
> }
>
> data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
>
> - DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
> + DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
> cached_state->n1postdiv, cached_state->n2postdiv);
>
> dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
> @@ -865,7 +862,7 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy
> *phy)
> break;
> case MSM_DSI_PHY_MASTER:
> clkbuflr_en = 0x3;
> - pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
> + pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX];
> break;
> case MSM_DSI_PHY_SLAVE:
> clkbuflr_en = 0x0;
> @@ -889,7 +886,7 @@ static struct clk_hw
> *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
> u8 shift)
> {
> struct dsi_pll_14nm_postdiv *pll_postdiv;
> - struct device *dev = &pll_14nm->pdev->dev;
> + struct device *dev = &pll_14nm->phy->pdev->dev;
> struct clk_init_data postdiv_init = {
> .parent_names = (const char *[]) { parent_name },
> .num_parents = 1,
> @@ -928,21 +925,21 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> .flags = CLK_IGNORE_UNUSED,
> .ops = &clk_ops_dsi_pll_14nm_vco,
> };
> - struct device *dev = &pll_14nm->pdev->dev;
> + struct device *dev = &pll_14nm->phy->pdev->dev;
> struct clk_hw *hw;
> int ret;
>
> - DBG("DSI%d", pll_14nm->id);
> + DBG("DSI%d", pll_14nm->phy->id);
>
> - snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
> + snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id);
> pll_14nm->clk_hw.init = &vco_init;
>
> ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
> if (ret)
> return ret;
>
> - snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
> - snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
> + snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
> + snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id);
>
> /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
> hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
> @@ -950,8 +947,8 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
> - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
> + snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id);
> + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
>
> /* DSI Byte clock = VCO_CLK / N1 / 8 */
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> @@ -961,8 +958,8 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
>
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> - snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
> - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
> + snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
> + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
>
> /*
> * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
> @@ -972,8 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
> - snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
> + snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id);
> + snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
>
> /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
> * This is the output of N2 post-divider, bits 4-7 in
> @@ -991,7 +988,6 @@ static int pll_14nm_register(struct dsi_pll_14nm
> *pll_14nm, struct clk_hw **prov
> static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
> {
> struct platform_device *pdev = phy->pdev;
> - int id = phy->id;
> struct dsi_pll_14nm *pll_14nm;
> int ret;
>
> @@ -1002,11 +998,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> if (!pll_14nm)
> return -ENOMEM;
>
> - DBG("PLL%d", id);
> + DBG("PLL%d", phy->id);
>
> - pll_14nm->pdev = pdev;
> - pll_14nm->id = id;
> - pll_14nm_list[id] = pll_14nm;
> + pll_14nm_list[phy->id] = pll_14nm;
>
> spin_lock_init(&pll_14nm->postdiv_lock);
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index bdb117938bcc..0bcea3f3eca3 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -67,9 +67,6 @@ struct pll_28nm_cached_state {
> struct dsi_pll_28nm {
> struct clk_hw clk_hw;
>
> - int id;
> - struct platform_device *pdev;
> -
> struct msm_dsi_phy *phy;
>
> struct pll_28nm_cached_state cached_state;
> @@ -117,7 +114,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> *hw, unsigned long rate,
> unsigned long parent_rate)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> void __iomem *base = pll_28nm->phy->pll_base;
> unsigned long div_fbx1000, gen_vco_clk;
> u32 refclk_cfg, frac_n_mode, frac_n_value;
> @@ -288,14 +285,14 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>
> static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm
> *pll_28nm)
> {
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> void __iomem *base = pll_28nm->phy->pll_base;
> u32 max_reads = 5, timeout_us = 100;
> bool locked;
> u32 val;
> int i;
>
> - DBG("id=%d", pll_28nm->id);
> + DBG("id=%d", pll_28nm->phy->id);
>
> pll_28nm_software_reset(pll_28nm);
>
> @@ -382,13 +379,13 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct
> clk_hw *hw)
> static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> void __iomem *base = pll_28nm->phy->pll_base;
> bool locked;
> u32 max_reads = 10, timeout_us = 50;
> u32 val;
>
> - DBG("id=%d", pll_28nm->id);
> + DBG("id=%d", pll_28nm->phy->id);
>
> if (unlikely(pll_28nm->phy->pll_on))
> return 0;
> @@ -432,7 +429,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> - DBG("id=%d", pll_28nm->id);
> + DBG("id=%d", pll_28nm->phy->id);
>
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
> @@ -504,7 +501,7 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> - DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> + DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> return ret;
> }
> @@ -528,25 +525,25 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> .name = vco_name,
> .flags = CLK_IGNORE_UNUSED,
> };
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> struct clk_hw *hw;
> int ret;
>
> - DBG("%d", pll_28nm->id);
> + DBG("%d", pll_28nm->phy->id);
>
> if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp;
> else
> vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm;
>
> - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> pll_28nm->clk_hw.init = &vco_init;
> ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);
> if (ret)
> return ret;
>
> - snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
> + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT,
> pll_28nm->phy->pll_base +
> @@ -555,16 +552,16 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
> - snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk",
> pll_28nm->phy->id);
> + snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT,
> 1, 2);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
> + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent1, 0, pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> @@ -573,9 +570,9 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> return PTR_ERR(hw);
> provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> - snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
> - snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
> + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> + snprintf(parent2, 32, "dsi%dindirect_path_div2_clk",
> pll_28nm->phy->id);
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> parent1, parent2
> @@ -584,8 +581,8 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> if (IS_ERR(hw))
> return PTR_ERR(hw);
>
> - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
> - snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
> + snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> parent1, CLK_SET_RATE_PARENT, 1, 4);
> if (IS_ERR(hw))
> @@ -598,7 +595,6 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
> {
> struct platform_device *pdev = phy->pdev;
> - int id = phy->id;
> struct dsi_pll_28nm *pll_28nm;
> int ret;
>
> @@ -609,8 +605,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy
> *phy)
> if (!pll_28nm)
> return -ENOMEM;
>
> - pll_28nm->pdev = pdev;
> - pll_28nm->id = id;
> pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 36ee3f15d1e0..9ddd0adccce3 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -59,9 +59,6 @@ struct clk_bytediv {
> struct dsi_pll_28nm {
> struct clk_hw clk_hw;
>
> - int id;
> - struct platform_device *pdev;
> -
> struct msm_dsi_phy *phy;
>
> struct pll_28nm_cached_state cached_state;
> @@ -178,14 +175,14 @@ static unsigned long
> dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> void __iomem *base = pll_28nm->phy->pll_base;
> bool locked;
> unsigned int bit_div, byte_div;
> int max_reads = 1000, timeout_us = 100;
> u32 val;
>
> - DBG("id=%d", pll_28nm->id);
> + DBG("id=%d", pll_28nm->phy->id);
>
> if (unlikely(pll_28nm->phy->pll_on))
> return 0;
> @@ -227,7 +224,7 @@ static void dsi_pll_28nm_vco_unprepare(struct
> clk_hw *hw)
> {
> struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);
>
> - DBG("id=%d", pll_28nm->id);
> + DBG("id=%d", pll_28nm->phy->id);
>
> if (unlikely(!pll_28nm->phy->pll_on))
> return;
> @@ -368,7 +365,7 @@ static int dsi_28nm_restore_state(struct
> msm_dsi_phy *phy)
> ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
> cached_state->vco_rate, 0);
> if (ret) {
> - DRM_DEV_ERROR(&pll_28nm->pdev->dev,
> + DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> return ret;
> }
> @@ -392,13 +389,13 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> .flags = CLK_IGNORE_UNUSED,
> .ops = &clk_ops_dsi_pll_28nm_vco,
> };
> - struct device *dev = &pll_28nm->pdev->dev;
> + struct device *dev = &pll_28nm->phy->pdev->dev;
> struct clk_hw *hw;
> struct clk_bytediv *bytediv;
> struct clk_init_data bytediv_init = { };
> int ret;
>
> - DBG("%d", pll_28nm->id);
> + DBG("%d", pll_28nm->phy->id);
>
> bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL);
> if (!bytediv)
> @@ -412,7 +409,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> if (!clk_name)
> return -ENOMEM;
>
> - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
> + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> vco_init.name = vco_name;
>
> pll_28nm->clk_hw.init = &vco_init;
> @@ -425,8 +422,8 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> bytediv->hw.init = &bytediv_init;
> bytediv->reg = pll_28nm->phy->pll_base +
> REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
>
> - snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
> - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
> + snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
>
> bytediv_init.name = clk_name;
> bytediv_init.ops = &clk_bytediv_ops;
> @@ -440,7 +437,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> return ret;
> provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;
>
> - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
> + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
> /* DIV3 */
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent_name, 0, pll_28nm->phy->pll_base +
> @@ -456,7 +453,6 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
> static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
> {
> struct platform_device *pdev = phy->pdev;
> - int id = phy->id;
> struct dsi_pll_28nm *pll_28nm;
> int ret;
>
> @@ -467,8 +463,6 @@ static int dsi_pll_28nm_8960_init(struct
> msm_dsi_phy *phy)
> if (!pll_28nm)
> return -ENOMEM;
>
> - pll_28nm->pdev = pdev;
> - pll_28nm->id = id + 1;
> pll_28nm->phy = phy;
>
> ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 8e8cf9e63e8f..4df237ad0eaf 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -86,9 +86,6 @@ struct pll_7nm_cached_state {
> struct dsi_pll_7nm {
> struct clk_hw clk_hw;
>
> - int id;
> - struct platform_device *pdev;
> -
> struct msm_dsi_phy *phy;
>
> u64 vco_ref_clk_rate;
> @@ -320,7 +317,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw
> *hw, unsigned long rate,
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>
> - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate,
> + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
> parent_rate);
>
> pll_7nm->vco_current_rate = rate;
> @@ -359,7 +356,7 @@ static int dsi_pll_7nm_lock_status(struct
> dsi_pll_7nm *pll)
> timeout_us);
> if (rc)
> pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
> - pll->id, status);
> + pll->phy->id, status);
>
> return rc;
> }
> @@ -435,7 +432,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw
> *hw)
> /* Check for PLL lock */
> rc = dsi_pll_7nm_lock_status(pll_7nm);
> if (rc) {
> - pr_err("PLL(%d) lock failed\n", pll_7nm->id);
> + pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
> goto error;
> }
>
> @@ -519,7 +516,7 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> vco_rate = pll_freq;
>
> DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
> - pll_7nm->id, (unsigned long)vco_rate, dec, frac);
> + pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
>
> return (unsigned long)vco_rate;
> }
> @@ -568,7 +565,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy
> *phy)
> cached->pll_mux = cmn_clk_cfg1 & 0x3;
>
> DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
> - pll_7nm->id, cached->pll_out_div, cached->bit_clk_div,
> + pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
> cached->pix_clk_div, cached->pll_mux);
> }
>
> @@ -595,12 +592,12 @@ static int dsi_7nm_restore_state(struct
> msm_dsi_phy *phy)
>
> ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> if (ret) {
> - DRM_DEV_ERROR(&pll_7nm->pdev->dev,
> + DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> return ret;
> }
>
> - DBG("DSI PLL%d", pll_7nm->id);
> + DBG("DSI PLL%d", pll_7nm->phy->id);
>
> return 0;
> }
> @@ -611,13 +608,13 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy
> *phy)
> void __iomem *base = phy->base;
> u32 data = 0x0; /* internal PLL */
>
> - DBG("DSI PLL%d", pll_7nm->id);
> + DBG("DSI PLL%d", pll_7nm->phy->id);
>
> switch (phy->usecase) {
> case MSM_DSI_PHY_STANDALONE:
> break;
> case MSM_DSI_PHY_MASTER:
> - pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX];
> + pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
> break;
> case MSM_DSI_PHY_SLAVE:
> data = 0x1; /* external PLL */
> @@ -649,21 +646,21 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> .flags = CLK_IGNORE_UNUSED,
> .ops = &clk_ops_dsi_pll_7nm_vco,
> };
> - struct device *dev = &pll_7nm->pdev->dev;
> + struct device *dev = &pll_7nm->phy->pdev->dev;
> struct clk_hw *hw;
> int ret;
>
> - DBG("DSI%d", pll_7nm->id);
> + DBG("DSI%d", pll_7nm->phy->id);
>
> - snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
> + snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id);
> pll_7nm->clk_hw.init = &vco_init;
>
> ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
> if (ret)
> return ret;
>
> - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);
>
> hw = devm_clk_hw_register_divider(dev, clk_name,
> parent, CLK_SET_RATE_PARENT,
> @@ -675,8 +672,8 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
>
> /* BIT CLK: DIV_CTRL_3_0 */
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> @@ -690,8 +687,8 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk",
> pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> @@ -703,8 +700,8 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
>
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
>
> - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 2);
> @@ -713,8 +710,8 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk",
> pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
>
> hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
> 0, 1, 4);
> @@ -723,11 +720,11 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
> - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
> - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id);
> - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
> + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
> + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
> + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk",
> pll_7nm->phy->id);
>
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> @@ -740,8 +737,8 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> goto fail;
> }
>
> - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id);
> - snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
> + snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> hw = devm_clk_hw_register_divider(dev, clk_name, parent,
> @@ -766,7 +763,6 @@ static int pll_7nm_register(struct dsi_pll_7nm
> *pll_7nm, struct clk_hw **provide
> static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
> {
> struct platform_device *pdev = phy->pdev;
> - int id = phy->id;
> struct dsi_pll_7nm *pll_7nm;
> int ret;
>
> @@ -774,11 +770,9 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> if (!pll_7nm)
> return -ENOMEM;
>
> - DBG("DSI PLL%d", id);
> + DBG("DSI PLL%d", phy->id);
>
> - pll_7nm->pdev = pdev;
> - pll_7nm->id = id;
> - pll_7nm_list[id] = pll_7nm;
> + pll_7nm_list[phy->id] = pll_7nm;
>
> spin_lock_init(&pll_7nm->postdiv_lock);
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (20 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 3:26 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov
` (2 subsequent siblings)
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
The 7nm, 10nm and 14nm drivers would store interim data used during
VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data
structures to the onstack storage. While we are at it, drop
unused/static 'config' data, unused config fields, etc.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 167 ++++-------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 334 +++++++--------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 166 ++++------
3 files changed, 220 insertions(+), 447 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index b937e77b3c37..1fbb54f4df98 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -36,43 +36,25 @@
*/
#define VCO_REF_CLK_RATE 19200000
-
-struct dsi_pll_regs {
- u32 pll_prop_gain_rate;
- u32 pll_lockdet_rate;
- u32 decimal_div_start;
- u32 frac_div_start_low;
- u32 frac_div_start_mid;
- u32 frac_div_start_high;
- u32 pll_clock_inverters;
- u32 ssc_stepsize_low;
- u32 ssc_stepsize_high;
- u32 ssc_div_per_low;
- u32 ssc_div_per_high;
- u32 ssc_adjper_low;
- u32 ssc_adjper_high;
- u32 ssc_control;
-};
+#define FRAC_BITS 18
/* v3.0.0 10nm implementation that requires the old timings settings */
#define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0)
struct dsi_pll_config {
- u32 ref_freq;
- bool div_override;
- u32 output_div;
- bool ignore_frac;
- bool disable_prescaler;
bool enable_ssc;
bool ssc_center;
- u32 dec_bits;
- u32 frac_bits;
- u32 lock_timer;
u32 ssc_freq;
u32 ssc_offset;
u32 ssc_adj_per;
- u32 thresh_cycles;
- u32 refclk_cycles;
+
+ /* out */
+ u32 pll_prop_gain_rate;
+ u32 decimal_div_start;
+ u32 frac_div_start;
+ u32 pll_clock_inverters;
+ u32 ssc_stepsize;
+ u32 ssc_div_per;
};
struct pll_10nm_cached_state {
@@ -88,15 +70,11 @@ struct dsi_pll_10nm {
struct msm_dsi_phy *phy;
- u64 vco_ref_clk_rate;
u64 vco_current_rate;
/* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
- struct dsi_pll_config pll_configuration;
- struct dsi_pll_regs reg_setup;
-
struct pll_10nm_cached_state cached_state;
struct dsi_pll_10nm *slave;
@@ -110,34 +88,19 @@ struct dsi_pll_10nm {
*/
static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
-static void dsi_pll_setup_config(struct dsi_pll_10nm *pll)
+static void dsi_pll_setup_config(struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
-
- config->ref_freq = pll->vco_ref_clk_rate;
- config->output_div = 1;
- config->dec_bits = 8;
- config->frac_bits = 18;
- config->lock_timer = 64;
config->ssc_freq = 31500;
config->ssc_offset = 5000;
config->ssc_adj_per = 2;
- config->thresh_cycles = 32;
- config->refclk_cycles = 256;
-
- config->div_override = false;
- config->ignore_frac = false;
- config->disable_prescaler = false;
config->enable_ssc = false;
- config->ssc_center = 0;
+ config->ssc_center = false;
}
-static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
+static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
- struct dsi_pll_regs *regs = &pll->reg_setup;
- u64 fref = pll->vco_ref_clk_rate;
+ u64 fref = VCO_REF_CLK_RATE;
u64 pll_freq;
u64 divider;
u64 dec, dec_multiple;
@@ -146,40 +109,32 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
pll_freq = pll->vco_current_rate;
- if (config->disable_prescaler)
- divider = fref;
- else
- divider = fref * 2;
+ divider = fref * 2;
- multiplier = 1 << config->frac_bits;
+ multiplier = 1 << FRAC_BITS;
dec_multiple = div_u64(pll_freq * multiplier, divider);
dec = div_u64_rem(dec_multiple, multiplier, &frac);
if (pll_freq <= 1900000000UL)
- regs->pll_prop_gain_rate = 8;
+ config->pll_prop_gain_rate = 8;
else if (pll_freq <= 3000000000UL)
- regs->pll_prop_gain_rate = 10;
+ config->pll_prop_gain_rate = 10;
else
- regs->pll_prop_gain_rate = 12;
+ config->pll_prop_gain_rate = 12;
if (pll_freq < 1100000000UL)
- regs->pll_clock_inverters = 8;
+ config->pll_clock_inverters = 8;
else
- regs->pll_clock_inverters = 0;
+ config->pll_clock_inverters = 0;
- regs->pll_lockdet_rate = config->lock_timer;
- regs->decimal_div_start = dec;
- regs->frac_div_start_low = (frac & 0xff);
- regs->frac_div_start_mid = (frac & 0xff00) >> 8;
- regs->frac_div_start_high = (frac & 0x30000) >> 16;
+ config->decimal_div_start = dec;
+ config->frac_div_start = frac;
}
#define SSC_CENTER BIT(0)
#define SSC_EN BIT(1)
-static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
+static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
- struct dsi_pll_regs *regs = &pll->reg_setup;
u32 ssc_per;
u32 ssc_mod;
u64 ssc_step_size;
@@ -190,58 +145,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
return;
}
- ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
+ ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
ssc_per -= ssc_mod;
- frac = regs->frac_div_start_low |
- (regs->frac_div_start_mid << 8) |
- (regs->frac_div_start_high << 16);
- ssc_step_size = regs->decimal_div_start;
- ssc_step_size *= (1 << config->frac_bits);
+ frac = config->frac_div_start;
+ ssc_step_size = config->decimal_div_start;
+ ssc_step_size *= (1 << FRAC_BITS);
ssc_step_size += frac;
ssc_step_size *= config->ssc_offset;
ssc_step_size *= (config->ssc_adj_per + 1);
ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
- regs->ssc_div_per_low = ssc_per & 0xFF;
- regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
- regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
- regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
- regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
- regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
-
- regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
+ config->ssc_div_per = ssc_per;
+ config->ssc_stepsize = ssc_step_size;
pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
- regs->decimal_div_start, frac, config->frac_bits);
+ config->decimal_div_start, frac, FRAC_BITS);
pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
}
-static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
+static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
{
void __iomem *base = pll->phy->pll_base;
- struct dsi_pll_regs *regs = &pll->reg_setup;
- if (pll->pll_configuration.enable_ssc) {
+ if (config->enable_ssc) {
pr_debug("SSC is enabled\n");
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
- regs->ssc_stepsize_low);
+ config->ssc_stepsize & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
- regs->ssc_stepsize_high);
+ config->ssc_stepsize >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
- regs->ssc_div_per_low);
+ config->ssc_div_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
- regs->ssc_div_per_high);
+ config->ssc_div_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
- regs->ssc_adjper_low);
+ config->ssc_adj_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
- regs->ssc_adjper_high);
+ config->ssc_adj_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
- SSC_EN | regs->ssc_control);
+ SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
}
}
@@ -271,50 +217,48 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
}
-static void dsi_pll_commit(struct dsi_pll_10nm *pll)
+static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
{
void __iomem *base = pll->phy->pll_base;
- struct dsi_pll_regs *reg = &pll->reg_setup;
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
- reg->decimal_div_start);
+ config->decimal_div_start);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
- reg->frac_div_start_low);
+ config->frac_div_start & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
- reg->frac_div_start_mid);
+ (config->frac_div_start & 0xff00) >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
- reg->frac_div_start_high);
- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
- reg->pll_lockdet_rate);
+ (config->frac_div_start & 0x30000) >> 16);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
- reg->pll_clock_inverters);
+ config->pll_clock_inverters);
}
static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
+ struct dsi_pll_config config;
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
parent_rate);
pll_10nm->vco_current_rate = rate;
- pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
- dsi_pll_setup_config(pll_10nm);
+ dsi_pll_setup_config(&config);
- dsi_pll_calc_dec_frac(pll_10nm);
+ dsi_pll_calc_dec_frac(pll_10nm, &config);
- dsi_pll_calc_ssc(pll_10nm);
+ dsi_pll_calc_ssc(pll_10nm, &config);
- dsi_pll_commit(pll_10nm);
+ dsi_pll_commit(pll_10nm, &config);
dsi_pll_config_hzindep_reg(pll_10nm);
- dsi_pll_ssc_commit(pll_10nm);
+ dsi_pll_ssc_commit(pll_10nm, &config);
/* flush, ensure all register writes are done*/
wmb();
@@ -461,9 +405,8 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
- struct dsi_pll_config *config = &pll_10nm->pll_configuration;
void __iomem *base = pll_10nm->phy->pll_base;
- u64 ref_clk = pll_10nm->vco_ref_clk_rate;
+ u64 ref_clk = VCO_REF_CLK_RATE;
u64 vco_rate = 0x0;
u64 multiplier;
u32 frac;
@@ -483,7 +426,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
* TODO:
* 1. Assumes prescaler is disabled
*/
- multiplier = 1 << config->frac_bits;
+ multiplier = 1 << FRAC_BITS;
pll_freq = dec * (ref_clk * 2);
tmp64 = (ref_clk * 2 * frac);
pll_freq += div_u64(tmp64, multiplier);
@@ -565,7 +508,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy)
val |= cached->pll_mux;
dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
+ ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, VCO_REF_CLK_RATE);
if (ret) {
DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 8b4865c5796d..d08ad0c632b4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -37,51 +37,19 @@
#define VCO_MIN_RATE 1300000000UL
#define VCO_MAX_RATE 2600000000UL
-#define DSI_PLL_DEFAULT_VCO_POSTDIV 1
+struct dsi_pll_config {
+ u64 vco_current_rate;
-struct dsi_pll_input {
- u32 fref; /* reference clk */
- u32 fdata; /* bit clock rate */
- u32 dsiclk_sel; /* Mux configuration (see diagram) */
u32 ssc_en; /* SSC enable/disable */
- u32 ldo_en;
/* fixed params */
- u32 refclk_dbler_en;
- u32 vco_measure_time;
- u32 kvco_measure_time;
- u32 bandgap_timer;
- u32 pll_wakeup_timer;
u32 plllock_cnt;
- u32 plllock_rng;
u32 ssc_center;
u32 ssc_adj_period;
u32 ssc_spread;
u32 ssc_freq;
- u32 pll_ie_trim;
- u32 pll_ip_trim;
- u32 pll_iptat_trim;
- u32 pll_cpcset_cur;
- u32 pll_cpmset_cur;
-
- u32 pll_icpmset;
- u32 pll_icpcset;
-
- u32 pll_icpmset_p;
- u32 pll_icpmset_m;
-
- u32 pll_icpcset_p;
- u32 pll_icpcset_m;
-
- u32 pll_lpf_res1;
- u32 pll_lpf_cap1;
- u32 pll_lpf_cap2;
- u32 pll_c3ctrl;
- u32 pll_r3ctrl;
-};
-struct dsi_pll_output {
- u32 pll_txclk_en;
+ /* calculated */
u32 dec_start;
u32 div_frac_start;
u32 ssc_period;
@@ -91,19 +59,6 @@ struct dsi_pll_output {
u32 pll_vco_count;
u32 pll_kvco_div_ref;
u32 pll_kvco_count;
- u32 pll_misc1;
- u32 pll_lpf2_postdiv;
- u32 pll_resetsm_cntrl;
- u32 pll_resetsm_cntrl2;
- u32 pll_resetsm_cntrl5;
- u32 pll_kvco_code;
-
- u32 cmn_clk_cfg0;
- u32 cmn_clk_cfg1;
- u32 cmn_ldo_cntrl;
-
- u32 pll_postdiv;
- u32 fcvo;
};
struct pll_14nm_cached_state {
@@ -117,15 +72,9 @@ struct dsi_pll_14nm {
struct msm_dsi_phy *phy;
- struct dsi_pll_input in;
- struct dsi_pll_output out;
-
/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
- u64 vco_current_rate;
- u64 vco_ref_clk_rate;
-
struct pll_14nm_cached_state cached_state;
struct dsi_pll_14nm *slave;
@@ -195,78 +144,50 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
return pll_locked;
}
-static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
+static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
{
- pll->in.fref = pll->vco_ref_clk_rate;
- pll->in.fdata = 0;
- pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
- pll->in.ldo_en = 0; /* disabled for now */
-
/* fixed input */
- pll->in.refclk_dbler_en = 0;
- pll->in.vco_measure_time = 5;
- pll->in.kvco_measure_time = 5;
- pll->in.bandgap_timer = 4;
- pll->in.pll_wakeup_timer = 5;
- pll->in.plllock_cnt = 1;
- pll->in.plllock_rng = 0;
+ pconf->plllock_cnt = 1;
/*
* SSC is enabled by default. We might need DT props for configuring
* some SSC params like PPM and center/down spread etc.
*/
- pll->in.ssc_en = 1;
- pll->in.ssc_center = 0; /* down spread by default */
- pll->in.ssc_spread = 5; /* PPM / 1000 */
- pll->in.ssc_freq = 31500; /* default recommended */
- pll->in.ssc_adj_period = 37;
-
- pll->in.pll_ie_trim = 4;
- pll->in.pll_ip_trim = 4;
- pll->in.pll_cpcset_cur = 1;
- pll->in.pll_cpmset_cur = 1;
- pll->in.pll_icpmset = 4;
- pll->in.pll_icpcset = 4;
- pll->in.pll_icpmset_p = 0;
- pll->in.pll_icpmset_m = 0;
- pll->in.pll_icpcset_p = 0;
- pll->in.pll_icpcset_m = 0;
- pll->in.pll_lpf_res1 = 3;
- pll->in.pll_lpf_cap1 = 11;
- pll->in.pll_lpf_cap2 = 1;
- pll->in.pll_iptat_trim = 7;
- pll->in.pll_c3ctrl = 2;
- pll->in.pll_r3ctrl = 1;
+ pconf->ssc_en = 1;
+ pconf->ssc_center = 0; /* down spread by default */
+ pconf->ssc_spread = 5; /* PPM / 1000 */
+ pconf->ssc_freq = 31500; /* default recommended */
+ pconf->ssc_adj_period = 37;
}
#define CEIL(x, y) (((x) + ((y) - 1)) / (y))
-static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
+static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
u32 period, ssc_period;
u32 ref, rem;
u64 step_size;
- DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate);
+ DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
- ssc_period = pll->in.ssc_freq / 500;
- period = (u32)pll->vco_ref_clk_rate / 1000;
+ ssc_period = pconf->ssc_freq / 500;
+ period = (u32)VCO_REF_CLK_RATE / 1000;
ssc_period = CEIL(period, ssc_period);
ssc_period -= 1;
- pll->out.ssc_period = ssc_period;
+ pconf->ssc_period = ssc_period;
- DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
- pll->in.ssc_spread, pll->out.ssc_period);
+ DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
+ pconf->ssc_spread, pconf->ssc_period);
- step_size = (u32)pll->vco_current_rate;
- ref = pll->vco_ref_clk_rate;
+ step_size = (u32)pconf->vco_current_rate;
+ ref = VCO_REF_CLK_RATE;
ref /= 1000;
step_size = div_u64(step_size, ref);
step_size <<= 20;
step_size = div_u64(step_size, 1000);
- step_size *= pll->in.ssc_spread;
+ step_size *= pconf->ssc_spread;
step_size = div_u64(step_size, 1000);
- step_size *= (pll->in.ssc_adj_period + 1);
+ step_size *= (pconf->ssc_adj_period + 1);
rem = 0;
step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
@@ -277,18 +198,16 @@ static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
step_size &= 0x0ffff; /* take lower 16 bits */
- pll->out.ssc_step_size = step_size;
+ pconf->ssc_step_size = step_size;
}
-static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
+static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
- struct dsi_pll_input *pin = &pll->in;
- struct dsi_pll_output *pout = &pll->out;
u64 multiplier = BIT(20);
u64 dec_start_multiple, dec_start, pll_comp_val;
u32 duration, div_frac_start;
- u64 vco_clk_rate = pll->vco_current_rate;
- u64 fref = pll->vco_ref_clk_rate;
+ u64 vco_clk_rate = pconf->vco_current_rate;
+ u64 fref = VCO_REF_CLK_RATE;
DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
@@ -297,14 +216,14 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
dec_start = div_u64(dec_start_multiple, multiplier);
- pout->dec_start = (u32)dec_start;
- pout->div_frac_start = div_frac_start;
+ pconf->dec_start = (u32)dec_start;
+ pconf->div_frac_start = div_frac_start;
- if (pin->plllock_cnt == 0)
+ if (pconf->plllock_cnt == 0)
duration = 1024;
- else if (pin->plllock_cnt == 1)
+ else if (pconf->plllock_cnt == 1)
duration = 256;
- else if (pin->plllock_cnt == 2)
+ else if (pconf->plllock_cnt == 2)
duration = 128;
else
duration = 32;
@@ -313,10 +232,7 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
pll_comp_val = div_u64(pll_comp_val, multiplier);
do_div(pll_comp_val, 10);
- pout->plllock_cmp = (u32)pll_comp_val;
-
- pout->pll_txclk_en = 1;
- pout->cmn_ldo_cntrl = 0x3c;
+ pconf->plllock_cmp = (u32)pll_comp_val;
}
static u32 pll_14nm_kvco_slop(u32 vrate)
@@ -333,74 +249,66 @@ static u32 pll_14nm_kvco_slop(u32 vrate)
return slop;
}
-static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
+static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
- struct dsi_pll_input *pin = &pll->in;
- struct dsi_pll_output *pout = &pll->out;
- u64 vco_clk_rate = pll->vco_current_rate;
- u64 fref = pll->vco_ref_clk_rate;
+ u64 vco_clk_rate = pconf->vco_current_rate;
+ u64 fref = VCO_REF_CLK_RATE;
+ u32 vco_measure_time = 5;
+ u32 kvco_measure_time = 5;
u64 data;
u32 cnt;
- data = fref * pin->vco_measure_time;
+ data = fref * vco_measure_time;
do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */
data -= 2;
- pout->pll_vco_div_ref = data;
+ pconf->pll_vco_div_ref = data;
data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
- data *= pin->vco_measure_time;
+ data *= vco_measure_time;
do_div(data, 10);
- pout->pll_vco_count = data;
+ pconf->pll_vco_count = data;
- data = fref * pin->kvco_measure_time;
+ data = fref * kvco_measure_time;
do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */
data -= 1;
- pout->pll_kvco_div_ref = data;
+ pconf->pll_kvco_div_ref = data;
cnt = pll_14nm_kvco_slop(vco_clk_rate);
cnt *= 2;
cnt /= 100;
- cnt *= pin->kvco_measure_time;
- pout->pll_kvco_count = cnt;
-
- pout->pll_misc1 = 16;
- pout->pll_resetsm_cntrl = 48;
- pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
- pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
- pout->pll_kvco_code = 0;
+ cnt *= kvco_measure_time;
+ pconf->pll_kvco_count = cnt;
}
-static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
+static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
- struct dsi_pll_input *pin = &pll->in;
- struct dsi_pll_output *pout = &pll->out;
u8 data;
- data = pin->ssc_adj_period;
+ data = pconf->ssc_adj_period;
data &= 0x0ff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
- data = (pin->ssc_adj_period >> 8);
+ data = (pconf->ssc_adj_period >> 8);
data &= 0x03;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
- data = pout->ssc_period;
+ data = pconf->ssc_period;
data &= 0x0ff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
- data = (pout->ssc_period >> 8);
+ data = (pconf->ssc_period >> 8);
data &= 0x0ff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
- data = pout->ssc_step_size;
+ data = pconf->ssc_step_size;
data &= 0x0ff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
- data = (pout->ssc_step_size >> 8);
+ data = (pconf->ssc_step_size >> 8);
data &= 0x0ff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
- data = (pin->ssc_center & 0x01);
+ data = (pconf->ssc_center & 0x01);
data <<= 1;
data |= 0x01; /* enable */
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
@@ -409,8 +317,7 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
}
static void pll_db_commit_common(struct dsi_pll_14nm *pll,
- struct dsi_pll_input *pin,
- struct dsi_pll_output *pout)
+ struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
u8 data;
@@ -419,55 +326,41 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
data = 0;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
- data = pout->pll_txclk_en;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
- data = pout->pll_resetsm_cntrl;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
- data = pout->pll_resetsm_cntrl2;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
- data = pout->pll_resetsm_cntrl5;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */
- data = pout->pll_vco_div_ref & 0xff;
+ data = pconf->pll_vco_div_ref & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
- data = (pout->pll_vco_div_ref >> 8) & 0x3;
+ data = (pconf->pll_vco_div_ref >> 8) & 0x3;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
- data = pout->pll_kvco_div_ref & 0xff;
+ data = pconf->pll_kvco_div_ref & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
- data = (pout->pll_kvco_div_ref >> 8) & 0x3;
+ data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
- data = pout->pll_misc1;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
- data = pin->pll_ie_trim;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
- data = pin->pll_ip_trim;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
- data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
- data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
- data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
- data = pin->pll_icpmset << 3 | pin->pll_icpcset;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
- data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
- data = pin->pll_iptat_trim;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
- data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
}
static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
@@ -488,8 +381,7 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
}
static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
- struct dsi_pll_input *pin,
- struct dsi_pll_output *pout)
+ struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
void __iomem *cmn_base = pll->phy->base;
@@ -497,57 +389,64 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
DBG("DSI%d PLL", pll->phy->id);
- data = pout->cmn_ldo_cntrl;
- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
- pll_db_commit_common(pll, pin, pout);
+ pll_db_commit_common(pll, pconf);
pll_14nm_software_reset(pll);
- data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
+ /* Use the /2 path in Mux */
+ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
data = 0xff; /* data, clk, pll normal operation */
dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
/* configure the frequency dependent pll registers */
- data = pout->dec_start;
+ data = pconf->dec_start;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
- data = pout->div_frac_start & 0xff;
+ data = pconf->div_frac_start & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
- data = (pout->div_frac_start >> 8) & 0xff;
+ data = (pconf->div_frac_start >> 8) & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
- data = (pout->div_frac_start >> 16) & 0xf;
+ data = (pconf->div_frac_start >> 16) & 0xf;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
- data = pout->plllock_cmp & 0xff;
+ data = pconf->plllock_cmp & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
- data = (pout->plllock_cmp >> 8) & 0xff;
+ data = (pconf->plllock_cmp >> 8) & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
- data = (pout->plllock_cmp >> 16) & 0x3;
+ data = (pconf->plllock_cmp >> 16) & 0x3;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
- data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
+ data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
- data = pout->pll_vco_count & 0xff;
+ data = pconf->pll_vco_count & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
- data = (pout->pll_vco_count >> 8) & 0xff;
+ data = (pconf->pll_vco_count >> 8) & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
- data = pout->pll_kvco_count & 0xff;
+ data = pconf->pll_kvco_count & 0xff;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
- data = (pout->pll_kvco_count >> 8) & 0x3;
+ data = (pconf->pll_kvco_count >> 8) & 0x3;
dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
- data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
+ /*
+ * High nibble configures the post divider internal to the VCO. It's
+ * fixed to divide by 1 for now.
+ *
+ * 0: divided by 1
+ * 1: divided by 2
+ * 2: divided by 4
+ * 3: divided by 8
+ */
+ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3);
- if (pin->ssc_en)
- pll_db_commit_ssc(pll);
+ if (pconf->ssc_en)
+ pll_db_commit_ssc(pll, pconf);
wmb(); /* make sure register committed */
}
@@ -559,35 +458,20 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
- struct dsi_pll_input *pin = &pll_14nm->in;
- struct dsi_pll_output *pout = &pll_14nm->out;
+ struct dsi_pll_config conf;
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
parent_rate);
- pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
-
- dsi_pll_14nm_input_init(pll_14nm);
-
- /*
- * This configures the post divider internal to the VCO. It's
- * fixed to divide by 1 for now.
- *
- * tx_band = pll_postdiv.
- * 0: divided by 1
- * 1: divided by 2
- * 2: divided by 4
- * 3: divided by 8
- */
- pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
+ dsi_pll_14nm_config_init(&conf);
+ conf.vco_current_rate = rate;
- pll_14nm_dec_frac_calc(pll_14nm);
+ pll_14nm_dec_frac_calc(pll_14nm, &conf);
- if (pin->ssc_en)
- pll_14nm_ssc_calc(pll_14nm);
+ if (conf.ssc_en)
+ pll_14nm_ssc_calc(pll_14nm, &conf);
- pll_14nm_calc_vco_count(pll_14nm);
+ pll_14nm_calc_vco_count(pll_14nm, &conf);
/* commit the slave DSI PLL registers if we're master. Note that we
* don't lock the slave PLL. We just ensure that the PLL/PHY registers
@@ -596,10 +480,10 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
- pll_db_commit_14nm(pll_14nm_slave, pin, pout);
+ pll_db_commit_14nm(pll_14nm_slave, &conf);
}
- pll_db_commit_14nm(pll_14nm, pin, pout);
+ pll_db_commit_14nm(pll_14nm, &conf);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 4df237ad0eaf..ce6ae2fba993 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -36,43 +36,24 @@
*/
#define VCO_REF_CLK_RATE 19200000
-
-struct dsi_pll_regs {
- u32 pll_prop_gain_rate;
- u32 pll_lockdet_rate;
- u32 decimal_div_start;
- u32 frac_div_start_low;
- u32 frac_div_start_mid;
- u32 frac_div_start_high;
- u32 pll_clock_inverters;
- u32 ssc_stepsize_low;
- u32 ssc_stepsize_high;
- u32 ssc_div_per_low;
- u32 ssc_div_per_high;
- u32 ssc_adjper_low;
- u32 ssc_adjper_high;
- u32 ssc_control;
-};
+#define FRAC_BITS 18
/* Hardware is V4.1 */
#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
struct dsi_pll_config {
- u32 ref_freq;
- bool div_override;
- u32 output_div;
- bool ignore_frac;
- bool disable_prescaler;
bool enable_ssc;
bool ssc_center;
- u32 dec_bits;
- u32 frac_bits;
- u32 lock_timer;
u32 ssc_freq;
u32 ssc_offset;
u32 ssc_adj_per;
- u32 thresh_cycles;
- u32 refclk_cycles;
+
+ /* out */
+ u32 decimal_div_start;
+ u32 frac_div_start;
+ u32 pll_clock_inverters;
+ u32 ssc_stepsize;
+ u32 ssc_div_per;
};
struct pll_7nm_cached_state {
@@ -88,15 +69,11 @@ struct dsi_pll_7nm {
struct msm_dsi_phy *phy;
- u64 vco_ref_clk_rate;
u64 vco_current_rate;
/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
- struct dsi_pll_config pll_configuration;
- struct dsi_pll_regs reg_setup;
-
struct pll_7nm_cached_state cached_state;
struct dsi_pll_7nm *slave;
@@ -110,35 +87,20 @@ struct dsi_pll_7nm {
*/
static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
-static void dsi_pll_setup_config(struct dsi_pll_7nm *pll)
+static void dsi_pll_setup_config(struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
-
- config->ref_freq = pll->vco_ref_clk_rate;
- config->output_div = 1;
- config->dec_bits = 8;
- config->frac_bits = 18;
- config->lock_timer = 64;
config->ssc_freq = 31500;
config->ssc_offset = 4800;
config->ssc_adj_per = 2;
- config->thresh_cycles = 32;
- config->refclk_cycles = 256;
-
- config->div_override = false;
- config->ignore_frac = false;
- config->disable_prescaler = false;
/* TODO: ssc enable */
config->enable_ssc = false;
config->ssc_center = 0;
}
-static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
+static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
- struct dsi_pll_regs *regs = &pll->reg_setup;
- u64 fref = pll->vco_ref_clk_rate;
+ u64 fref = VCO_REF_CLK_RATE;
u64 pll_freq;
u64 divider;
u64 dec, dec_multiple;
@@ -147,42 +109,34 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
pll_freq = pll->vco_current_rate;
- if (config->disable_prescaler)
- divider = fref;
- else
- divider = fref * 2;
+ divider = fref * 2;
- multiplier = 1 << config->frac_bits;
+ multiplier = 1 << FRAC_BITS;
dec_multiple = div_u64(pll_freq * multiplier, divider);
div_u64_rem(dec_multiple, multiplier, &frac);
dec = div_u64(dec_multiple, multiplier);
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
- regs->pll_clock_inverters = 0x28;
+ config->pll_clock_inverters = 0x28;
else if (pll_freq <= 1000000000ULL)
- regs->pll_clock_inverters = 0xa0;
+ config->pll_clock_inverters = 0xa0;
else if (pll_freq <= 2500000000ULL)
- regs->pll_clock_inverters = 0x20;
+ config->pll_clock_inverters = 0x20;
else if (pll_freq <= 3020000000ULL)
- regs->pll_clock_inverters = 0x00;
+ config->pll_clock_inverters = 0x00;
else
- regs->pll_clock_inverters = 0x40;
+ config->pll_clock_inverters = 0x40;
- regs->pll_lockdet_rate = config->lock_timer;
- regs->decimal_div_start = dec;
- regs->frac_div_start_low = (frac & 0xff);
- regs->frac_div_start_mid = (frac & 0xff00) >> 8;
- regs->frac_div_start_high = (frac & 0x30000) >> 16;
+ config->decimal_div_start = dec;
+ config->frac_div_start = frac;
}
#define SSC_CENTER BIT(0)
#define SSC_EN BIT(1)
-static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
+static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
{
- struct dsi_pll_config *config = &pll->pll_configuration;
- struct dsi_pll_regs *regs = &pll->reg_setup;
u32 ssc_per;
u32 ssc_mod;
u64 ssc_step_size;
@@ -193,58 +147,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
return;
}
- ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
+ ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
ssc_per -= ssc_mod;
- frac = regs->frac_div_start_low |
- (regs->frac_div_start_mid << 8) |
- (regs->frac_div_start_high << 16);
- ssc_step_size = regs->decimal_div_start;
- ssc_step_size *= (1 << config->frac_bits);
+ frac = config->frac_div_start;
+ ssc_step_size = config->decimal_div_start;
+ ssc_step_size *= (1 << FRAC_BITS);
ssc_step_size += frac;
ssc_step_size *= config->ssc_offset;
ssc_step_size *= (config->ssc_adj_per + 1);
ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
- regs->ssc_div_per_low = ssc_per & 0xFF;
- regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
- regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
- regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
- regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
- regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
-
- regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
+ config->ssc_div_per = ssc_per;
+ config->ssc_stepsize = ssc_step_size;
pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
- regs->decimal_div_start, frac, config->frac_bits);
+ config->decimal_div_start, frac, FRAC_BITS);
pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
}
-static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
+static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
{
void __iomem *base = pll->phy->pll_base;
- struct dsi_pll_regs *regs = &pll->reg_setup;
- if (pll->pll_configuration.enable_ssc) {
+ if (config->enable_ssc) {
pr_debug("SSC is enabled\n");
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
- regs->ssc_stepsize_low);
+ config->ssc_stepsize & 0xff);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
- regs->ssc_stepsize_high);
+ config->ssc_stepsize >> 8);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
- regs->ssc_div_per_low);
+ config->ssc_div_per & 0xff);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
- regs->ssc_div_per_high);
+ config->ssc_div_per >> 8);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
- regs->ssc_adjper_low);
+ config->ssc_adj_per & 0xff);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
- regs->ssc_adjper_high);
+ config->ssc_adj_per >> 8);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
- SSC_EN | regs->ssc_control);
+ SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
}
}
@@ -296,44 +241,46 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
}
}
-static void dsi_pll_commit(struct dsi_pll_7nm *pll)
+static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
{
void __iomem *base = pll->phy->pll_base;
- struct dsi_pll_regs *reg = &pll->reg_setup;
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start);
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low);
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid);
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high);
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
+ config->frac_div_start & 0xff);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
+ (config->frac_div_start & 0xff00) >> 8);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
+ (config->frac_div_start & 0x30000) >> 16);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters);
}
static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
+ struct dsi_pll_config config;
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
parent_rate);
pll_7nm->vco_current_rate = rate;
- pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
- dsi_pll_setup_config(pll_7nm);
+ dsi_pll_setup_config(&config);
- dsi_pll_calc_dec_frac(pll_7nm);
+ dsi_pll_calc_dec_frac(pll_7nm, &config);
- dsi_pll_calc_ssc(pll_7nm);
+ dsi_pll_calc_ssc(pll_7nm, &config);
- dsi_pll_commit(pll_7nm);
+ dsi_pll_commit(pll_7nm, &config);
dsi_pll_config_hzindep_reg(pll_7nm);
- dsi_pll_ssc_commit(pll_7nm);
+ dsi_pll_ssc_commit(pll_7nm, &config);
/* flush, ensure all register writes are done*/
wmb();
@@ -486,9 +433,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
- struct dsi_pll_config *config = &pll_7nm->pll_configuration;
void __iomem *base = pll_7nm->phy->pll_base;
- u64 ref_clk = pll_7nm->vco_ref_clk_rate;
+ u64 ref_clk = VCO_REF_CLK_RATE;
u64 vco_rate = 0x0;
u64 multiplier;
u32 frac;
@@ -508,7 +454,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
* TODO:
* 1. Assumes prescaler is disabled
*/
- multiplier = 1 << config->frac_bits;
+ multiplier = 1 << FRAC_BITS;
pll_freq = dec * (ref_clk * 2);
tmp64 = (ref_clk * 2 * frac);
pll_freq += div_u64(tmp64, multiplier);
@@ -590,7 +536,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy)
val |= cached->pll_mux;
dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
- ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
+ ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, VCO_REF_CLK_RATE);
if (ret) {
DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure
2021-03-27 11:03 ` [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov
@ 2021-03-30 3:26 ` abhinavk
2021-03-30 15:23 ` Dmitry Baryshkov
0 siblings, 1 reply; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> The 7nm, 10nm and 14nm drivers would store interim data used during
> VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this
> data
> structures to the onstack storage. While we are at it, drop
> unused/static 'config' data, unused config fields, etc.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 167 ++++-------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 334 +++++++--------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 166 ++++------
> 3 files changed, 220 insertions(+), 447 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index b937e77b3c37..1fbb54f4df98 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -36,43 +36,25 @@
> */
>
> #define VCO_REF_CLK_RATE 19200000
> -
> -struct dsi_pll_regs {
> - u32 pll_prop_gain_rate;
> - u32 pll_lockdet_rate;
> - u32 decimal_div_start;
> - u32 frac_div_start_low;
> - u32 frac_div_start_mid;
> - u32 frac_div_start_high;
> - u32 pll_clock_inverters;
> - u32 ssc_stepsize_low;
> - u32 ssc_stepsize_high;
> - u32 ssc_div_per_low;
> - u32 ssc_div_per_high;
> - u32 ssc_adjper_low;
> - u32 ssc_adjper_high;
> - u32 ssc_control;
> -};
> +#define FRAC_BITS 18
>
> /* v3.0.0 10nm implementation that requires the old timings settings
> */
> #define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0)
>
> struct dsi_pll_config {
> - u32 ref_freq;
> - bool div_override;
> - u32 output_div;
> - bool ignore_frac;
> - bool disable_prescaler;
> bool enable_ssc;
> bool ssc_center;
> - u32 dec_bits;
> - u32 frac_bits;
> - u32 lock_timer;
> u32 ssc_freq;
> u32 ssc_offset;
> u32 ssc_adj_per;
> - u32 thresh_cycles;
> - u32 refclk_cycles;
> +
> + /* out */
> + u32 pll_prop_gain_rate;
> + u32 decimal_div_start;
> + u32 frac_div_start;
> + u32 pll_clock_inverters;
> + u32 ssc_stepsize;
> + u32 ssc_div_per;
> };
>
> struct pll_10nm_cached_state {
> @@ -88,15 +70,11 @@ struct dsi_pll_10nm {
>
> struct msm_dsi_phy *phy;
>
> - u64 vco_ref_clk_rate;
> u64 vco_current_rate;
>
> /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - struct dsi_pll_config pll_configuration;
> - struct dsi_pll_regs reg_setup;
> -
> struct pll_10nm_cached_state cached_state;
>
> struct dsi_pll_10nm *slave;
> @@ -110,34 +88,19 @@ struct dsi_pll_10nm {
> */
> static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
>
> -static void dsi_pll_setup_config(struct dsi_pll_10nm *pll)
> +static void dsi_pll_setup_config(struct dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> -
> - config->ref_freq = pll->vco_ref_clk_rate;
> - config->output_div = 1;
> - config->dec_bits = 8;
> - config->frac_bits = 18;
> - config->lock_timer = 64;
> config->ssc_freq = 31500;
> config->ssc_offset = 5000;
> config->ssc_adj_per = 2;
> - config->thresh_cycles = 32;
> - config->refclk_cycles = 256;
> -
> - config->div_override = false;
> - config->ignore_frac = false;
> - config->disable_prescaler = false;
>
> config->enable_ssc = false;
> - config->ssc_center = 0;
> + config->ssc_center = false;
> }
>
> -static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
> +static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct
> dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
> - u64 fref = pll->vco_ref_clk_rate;
> + u64 fref = VCO_REF_CLK_RATE;
> u64 pll_freq;
> u64 divider;
> u64 dec, dec_multiple;
> @@ -146,40 +109,32 @@ static void dsi_pll_calc_dec_frac(struct
> dsi_pll_10nm *pll)
>
> pll_freq = pll->vco_current_rate;
>
> - if (config->disable_prescaler)
> - divider = fref;
> - else
> - divider = fref * 2;
> + divider = fref * 2;
>
> - multiplier = 1 << config->frac_bits;
> + multiplier = 1 << FRAC_BITS;
> dec_multiple = div_u64(pll_freq * multiplier, divider);
> dec = div_u64_rem(dec_multiple, multiplier, &frac);
>
> if (pll_freq <= 1900000000UL)
> - regs->pll_prop_gain_rate = 8;
> + config->pll_prop_gain_rate = 8;
> else if (pll_freq <= 3000000000UL)
> - regs->pll_prop_gain_rate = 10;
> + config->pll_prop_gain_rate = 10;
> else
> - regs->pll_prop_gain_rate = 12;
> + config->pll_prop_gain_rate = 12;
> if (pll_freq < 1100000000UL)
> - regs->pll_clock_inverters = 8;
> + config->pll_clock_inverters = 8;
> else
> - regs->pll_clock_inverters = 0;
> + config->pll_clock_inverters = 0;
>
> - regs->pll_lockdet_rate = config->lock_timer;
> - regs->decimal_div_start = dec;
> - regs->frac_div_start_low = (frac & 0xff);
> - regs->frac_div_start_mid = (frac & 0xff00) >> 8;
> - regs->frac_div_start_high = (frac & 0x30000) >> 16;
> + config->decimal_div_start = dec;
> + config->frac_div_start = frac;
> }
>
> #define SSC_CENTER BIT(0)
> #define SSC_EN BIT(1)
>
> -static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
> +static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct
> dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
> u32 ssc_per;
> u32 ssc_mod;
> u64 ssc_step_size;
> @@ -190,58 +145,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm
> *pll)
> return;
> }
>
> - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 -
> 1;
> + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 -
> 1;
> ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
> ssc_per -= ssc_mod;
>
> - frac = regs->frac_div_start_low |
> - (regs->frac_div_start_mid << 8) |
> - (regs->frac_div_start_high << 16);
> - ssc_step_size = regs->decimal_div_start;
> - ssc_step_size *= (1 << config->frac_bits);
> + frac = config->frac_div_start;
> + ssc_step_size = config->decimal_div_start;
> + ssc_step_size *= (1 << FRAC_BITS);
> ssc_step_size += frac;
> ssc_step_size *= config->ssc_offset;
> ssc_step_size *= (config->ssc_adj_per + 1);
> ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
> ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
>
> - regs->ssc_div_per_low = ssc_per & 0xFF;
> - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
> - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
> - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
> - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
> - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
> -
> - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
> + config->ssc_div_per = ssc_per;
> + config->ssc_stepsize = ssc_step_size;
>
> pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
> - regs->decimal_div_start, frac, config->frac_bits);
> + config->decimal_div_start, frac, FRAC_BITS);
> pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
> ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
> }
>
> -static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
> +static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct
> dsi_pll_config *config)
> {
> void __iomem *base = pll->phy->pll_base;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
>
> - if (pll->pll_configuration.enable_ssc) {
> + if (config->enable_ssc) {
> pr_debug("SSC is enabled\n");
>
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> - regs->ssc_stepsize_low);
> + config->ssc_stepsize & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> - regs->ssc_stepsize_high);
> + config->ssc_stepsize >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> - regs->ssc_div_per_low);
> + config->ssc_div_per & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> - regs->ssc_div_per_high);
> + config->ssc_div_per >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
> - regs->ssc_adjper_low);
> + config->ssc_adj_per & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
> - regs->ssc_adjper_high);
> + config->ssc_adj_per >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
> - SSC_EN | regs->ssc_control);
> + SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
> }
> }
>
> @@ -271,50 +217,48 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_10nm *pll)
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
> }
>
> -static void dsi_pll_commit(struct dsi_pll_10nm *pll)
> +static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct
> dsi_pll_config *config)
> {
> void __iomem *base = pll->phy->pll_base;
> - struct dsi_pll_regs *reg = &pll->reg_setup;
>
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
> - reg->decimal_div_start);
> + config->decimal_div_start);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> - reg->frac_div_start_low);
> + config->frac_div_start & 0xff);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
> - reg->frac_div_start_mid);
> + (config->frac_div_start & 0xff00) >> 8);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> - reg->frac_div_start_high);
> - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> - reg->pll_lockdet_rate);
> + (config->frac_div_start & 0x30000) >> 16);
> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
> - reg->pll_clock_inverters);
> + config->pll_clock_inverters);
> }
>
> static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> + struct dsi_pll_config config;
>
> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
> parent_rate);
>
> pll_10nm->vco_current_rate = rate;
> - pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
>
> - dsi_pll_setup_config(pll_10nm);
> + dsi_pll_setup_config(&config);
>
> - dsi_pll_calc_dec_frac(pll_10nm);
> + dsi_pll_calc_dec_frac(pll_10nm, &config);
>
> - dsi_pll_calc_ssc(pll_10nm);
> + dsi_pll_calc_ssc(pll_10nm, &config);
>
> - dsi_pll_commit(pll_10nm);
> + dsi_pll_commit(pll_10nm, &config);
>
> dsi_pll_config_hzindep_reg(pll_10nm);
>
> - dsi_pll_ssc_commit(pll_10nm);
> + dsi_pll_ssc_commit(pll_10nm, &config);
>
> /* flush, ensure all register writes are done*/
> wmb();
> @@ -461,9 +405,8 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
> - struct dsi_pll_config *config = &pll_10nm->pll_configuration;
> void __iomem *base = pll_10nm->phy->pll_base;
> - u64 ref_clk = pll_10nm->vco_ref_clk_rate;
> + u64 ref_clk = VCO_REF_CLK_RATE;
> u64 vco_rate = 0x0;
> u64 multiplier;
> u32 frac;
> @@ -483,7 +426,7 @@ static unsigned long
> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> * TODO:
> * 1. Assumes prescaler is disabled
> */
> - multiplier = 1 << config->frac_bits;
> + multiplier = 1 << FRAC_BITS;
> pll_freq = dec * (ref_clk * 2);
> tmp64 = (ref_clk * 2 * frac);
> pll_freq += div_u64(tmp64, multiplier);
> @@ -565,7 +508,7 @@ static int dsi_10nm_restore_state(struct
> msm_dsi_phy *phy)
> val |= cached->pll_mux;
> dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
> + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
> pll_10nm->vco_current_rate, VCO_REF_CLK_RATE);
> if (ret) {
> DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 8b4865c5796d..d08ad0c632b4 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -37,51 +37,19 @@
> #define VCO_MIN_RATE 1300000000UL
> #define VCO_MAX_RATE 2600000000UL
>
> -#define DSI_PLL_DEFAULT_VCO_POSTDIV 1
> +struct dsi_pll_config {
> + u64 vco_current_rate;
>
> -struct dsi_pll_input {
> - u32 fref; /* reference clk */
> - u32 fdata; /* bit clock rate */
> - u32 dsiclk_sel; /* Mux configuration (see diagram) */
> u32 ssc_en; /* SSC enable/disable */
> - u32 ldo_en;
>
> /* fixed params */
> - u32 refclk_dbler_en;
> - u32 vco_measure_time;
> - u32 kvco_measure_time;
> - u32 bandgap_timer;
> - u32 pll_wakeup_timer;
> u32 plllock_cnt;
> - u32 plllock_rng;
> u32 ssc_center;
> u32 ssc_adj_period;
> u32 ssc_spread;
> u32 ssc_freq;
> - u32 pll_ie_trim;
> - u32 pll_ip_trim;
> - u32 pll_iptat_trim;
> - u32 pll_cpcset_cur;
> - u32 pll_cpmset_cur;
> -
> - u32 pll_icpmset;
> - u32 pll_icpcset;
> -
> - u32 pll_icpmset_p;
> - u32 pll_icpmset_m;
> -
> - u32 pll_icpcset_p;
> - u32 pll_icpcset_m;
> -
> - u32 pll_lpf_res1;
> - u32 pll_lpf_cap1;
> - u32 pll_lpf_cap2;
> - u32 pll_c3ctrl;
> - u32 pll_r3ctrl;
> -};
>
> -struct dsi_pll_output {
> - u32 pll_txclk_en;
> + /* calculated */
> u32 dec_start;
> u32 div_frac_start;
> u32 ssc_period;
> @@ -91,19 +59,6 @@ struct dsi_pll_output {
> u32 pll_vco_count;
> u32 pll_kvco_div_ref;
> u32 pll_kvco_count;
> - u32 pll_misc1;
> - u32 pll_lpf2_postdiv;
> - u32 pll_resetsm_cntrl;
> - u32 pll_resetsm_cntrl2;
> - u32 pll_resetsm_cntrl5;
> - u32 pll_kvco_code;
> -
> - u32 cmn_clk_cfg0;
> - u32 cmn_clk_cfg1;
> - u32 cmn_ldo_cntrl;
> -
> - u32 pll_postdiv;
> - u32 fcvo;
> };
>
> struct pll_14nm_cached_state {
> @@ -117,15 +72,9 @@ struct dsi_pll_14nm {
>
> struct msm_dsi_phy *phy;
>
> - struct dsi_pll_input in;
> - struct dsi_pll_output out;
> -
> /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - u64 vco_current_rate;
> - u64 vco_ref_clk_rate;
> -
> struct pll_14nm_cached_state cached_state;
>
> struct dsi_pll_14nm *slave;
> @@ -195,78 +144,50 @@ static bool pll_14nm_poll_for_ready(struct
> dsi_pll_14nm *pll_14nm,
> return pll_locked;
> }
>
> -static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
> +static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
> {
> - pll->in.fref = pll->vco_ref_clk_rate;
> - pll->in.fdata = 0;
> - pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
> - pll->in.ldo_en = 0; /* disabled for now */
> -
> /* fixed input */
> - pll->in.refclk_dbler_en = 0;
> - pll->in.vco_measure_time = 5;
> - pll->in.kvco_measure_time = 5;
> - pll->in.bandgap_timer = 4;
> - pll->in.pll_wakeup_timer = 5;
> - pll->in.plllock_cnt = 1;
> - pll->in.plllock_rng = 0;
> + pconf->plllock_cnt = 1;
>
> /*
> * SSC is enabled by default. We might need DT props for configuring
> * some SSC params like PPM and center/down spread etc.
> */
> - pll->in.ssc_en = 1;
> - pll->in.ssc_center = 0; /* down spread by default */
> - pll->in.ssc_spread = 5; /* PPM / 1000 */
> - pll->in.ssc_freq = 31500; /* default recommended */
> - pll->in.ssc_adj_period = 37;
> -
> - pll->in.pll_ie_trim = 4;
> - pll->in.pll_ip_trim = 4;
> - pll->in.pll_cpcset_cur = 1;
> - pll->in.pll_cpmset_cur = 1;
> - pll->in.pll_icpmset = 4;
> - pll->in.pll_icpcset = 4;
> - pll->in.pll_icpmset_p = 0;
> - pll->in.pll_icpmset_m = 0;
> - pll->in.pll_icpcset_p = 0;
> - pll->in.pll_icpcset_m = 0;
> - pll->in.pll_lpf_res1 = 3;
> - pll->in.pll_lpf_cap1 = 11;
> - pll->in.pll_lpf_cap2 = 1;
> - pll->in.pll_iptat_trim = 7;
> - pll->in.pll_c3ctrl = 2;
> - pll->in.pll_r3ctrl = 1;
> + pconf->ssc_en = 1;
> + pconf->ssc_center = 0; /* down spread by default */
> + pconf->ssc_spread = 5; /* PPM / 1000 */
> + pconf->ssc_freq = 31500; /* default recommended */
> + pconf->ssc_adj_period = 37;
> }
>
> #define CEIL(x, y) (((x) + ((y) - 1)) / (y))
>
> -static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
> +static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct
> dsi_pll_config *pconf)
> {
> u32 period, ssc_period;
> u32 ref, rem;
> u64 step_size;
>
> - DBG("vco=%lld ref=%lld", pll->vco_current_rate,
> pll->vco_ref_clk_rate);
> + DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
>
> - ssc_period = pll->in.ssc_freq / 500;
> - period = (u32)pll->vco_ref_clk_rate / 1000;
> + ssc_period = pconf->ssc_freq / 500;
> + period = (u32)VCO_REF_CLK_RATE / 1000;
> ssc_period = CEIL(period, ssc_period);
> ssc_period -= 1;
> - pll->out.ssc_period = ssc_period;
> + pconf->ssc_period = ssc_period;
>
> - DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
> - pll->in.ssc_spread, pll->out.ssc_period);
> + DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
> + pconf->ssc_spread, pconf->ssc_period);
>
> - step_size = (u32)pll->vco_current_rate;
> - ref = pll->vco_ref_clk_rate;
> + step_size = (u32)pconf->vco_current_rate;
> + ref = VCO_REF_CLK_RATE;
> ref /= 1000;
> step_size = div_u64(step_size, ref);
> step_size <<= 20;
> step_size = div_u64(step_size, 1000);
> - step_size *= pll->in.ssc_spread;
> + step_size *= pconf->ssc_spread;
> step_size = div_u64(step_size, 1000);
> - step_size *= (pll->in.ssc_adj_period + 1);
> + step_size *= (pconf->ssc_adj_period + 1);
>
> rem = 0;
> step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
> @@ -277,18 +198,16 @@ static void pll_14nm_ssc_calc(struct dsi_pll_14nm
> *pll)
>
> step_size &= 0x0ffff; /* take lower 16 bits */
>
> - pll->out.ssc_step_size = step_size;
> + pconf->ssc_step_size = step_size;
> }
>
> -static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
> +static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct
> dsi_pll_config *pconf)
> {
> - struct dsi_pll_input *pin = &pll->in;
> - struct dsi_pll_output *pout = &pll->out;
> u64 multiplier = BIT(20);
> u64 dec_start_multiple, dec_start, pll_comp_val;
> u32 duration, div_frac_start;
> - u64 vco_clk_rate = pll->vco_current_rate;
> - u64 fref = pll->vco_ref_clk_rate;
> + u64 vco_clk_rate = pconf->vco_current_rate;
> + u64 fref = VCO_REF_CLK_RATE;
>
> DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
>
> @@ -297,14 +216,14 @@ static void pll_14nm_dec_frac_calc(struct
> dsi_pll_14nm *pll)
>
> dec_start = div_u64(dec_start_multiple, multiplier);
>
> - pout->dec_start = (u32)dec_start;
> - pout->div_frac_start = div_frac_start;
> + pconf->dec_start = (u32)dec_start;
> + pconf->div_frac_start = div_frac_start;
>
> - if (pin->plllock_cnt == 0)
> + if (pconf->plllock_cnt == 0)
> duration = 1024;
> - else if (pin->plllock_cnt == 1)
> + else if (pconf->plllock_cnt == 1)
> duration = 256;
> - else if (pin->plllock_cnt == 2)
> + else if (pconf->plllock_cnt == 2)
> duration = 128;
> else
> duration = 32;
> @@ -313,10 +232,7 @@ static void pll_14nm_dec_frac_calc(struct
> dsi_pll_14nm *pll)
> pll_comp_val = div_u64(pll_comp_val, multiplier);
> do_div(pll_comp_val, 10);
>
> - pout->plllock_cmp = (u32)pll_comp_val;
> -
> - pout->pll_txclk_en = 1;
> - pout->cmn_ldo_cntrl = 0x3c;
> + pconf->plllock_cmp = (u32)pll_comp_val;
> }
>
> static u32 pll_14nm_kvco_slop(u32 vrate)
> @@ -333,74 +249,66 @@ static u32 pll_14nm_kvco_slop(u32 vrate)
> return slop;
> }
>
> -static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
> +static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct
> dsi_pll_config *pconf)
> {
> - struct dsi_pll_input *pin = &pll->in;
> - struct dsi_pll_output *pout = &pll->out;
> - u64 vco_clk_rate = pll->vco_current_rate;
> - u64 fref = pll->vco_ref_clk_rate;
> + u64 vco_clk_rate = pconf->vco_current_rate;
> + u64 fref = VCO_REF_CLK_RATE;
> + u32 vco_measure_time = 5;
> + u32 kvco_measure_time = 5;
> u64 data;
> u32 cnt;
>
> - data = fref * pin->vco_measure_time;
> + data = fref * vco_measure_time;
> do_div(data, 1000000);
> data &= 0x03ff; /* 10 bits */
> data -= 2;
> - pout->pll_vco_div_ref = data;
> + pconf->pll_vco_div_ref = data;
>
> data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
> - data *= pin->vco_measure_time;
> + data *= vco_measure_time;
> do_div(data, 10);
> - pout->pll_vco_count = data;
> + pconf->pll_vco_count = data;
>
> - data = fref * pin->kvco_measure_time;
> + data = fref * kvco_measure_time;
> do_div(data, 1000000);
> data &= 0x03ff; /* 10 bits */
> data -= 1;
> - pout->pll_kvco_div_ref = data;
> + pconf->pll_kvco_div_ref = data;
>
> cnt = pll_14nm_kvco_slop(vco_clk_rate);
> cnt *= 2;
> cnt /= 100;
> - cnt *= pin->kvco_measure_time;
> - pout->pll_kvco_count = cnt;
> -
> - pout->pll_misc1 = 16;
> - pout->pll_resetsm_cntrl = 48;
> - pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
> - pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
> - pout->pll_kvco_code = 0;
> + cnt *= kvco_measure_time;
> + pconf->pll_kvco_count = cnt;
> }
>
> -static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
> +static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct
> dsi_pll_config *pconf)
> {
> void __iomem *base = pll->phy->pll_base;
> - struct dsi_pll_input *pin = &pll->in;
> - struct dsi_pll_output *pout = &pll->out;
> u8 data;
>
> - data = pin->ssc_adj_period;
> + data = pconf->ssc_adj_period;
> data &= 0x0ff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
> - data = (pin->ssc_adj_period >> 8);
> + data = (pconf->ssc_adj_period >> 8);
> data &= 0x03;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
>
> - data = pout->ssc_period;
> + data = pconf->ssc_period;
> data &= 0x0ff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
> - data = (pout->ssc_period >> 8);
> + data = (pconf->ssc_period >> 8);
> data &= 0x0ff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
>
> - data = pout->ssc_step_size;
> + data = pconf->ssc_step_size;
> data &= 0x0ff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
> - data = (pout->ssc_step_size >> 8);
> + data = (pconf->ssc_step_size >> 8);
> data &= 0x0ff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
>
> - data = (pin->ssc_center & 0x01);
> + data = (pconf->ssc_center & 0x01);
> data <<= 1;
> data |= 0x01; /* enable */
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
> @@ -409,8 +317,7 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm
> *pll)
> }
>
> static void pll_db_commit_common(struct dsi_pll_14nm *pll,
> - struct dsi_pll_input *pin,
> - struct dsi_pll_output *pout)
> + struct dsi_pll_config *pconf)
> {
> void __iomem *base = pll->phy->pll_base;
> u8 data;
> @@ -419,55 +326,41 @@ static void pll_db_commit_common(struct
> dsi_pll_14nm *pll,
> data = 0;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
>
> - data = pout->pll_txclk_en;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
>
> - data = pout->pll_resetsm_cntrl;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
> - data = pout->pll_resetsm_cntrl2;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
> - data = pout->pll_resetsm_cntrl5;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3);
> /* bandgap_timer */
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /*
> pll_wakeup_timer */
>
> - data = pout->pll_vco_div_ref & 0xff;
> + data = pconf->pll_vco_div_ref & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
> - data = (pout->pll_vco_div_ref >> 8) & 0x3;
> + data = (pconf->pll_vco_div_ref >> 8) & 0x3;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
>
> - data = pout->pll_kvco_div_ref & 0xff;
> + data = pconf->pll_kvco_div_ref & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
> - data = (pout->pll_kvco_div_ref >> 8) & 0x3;
> + data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
>
> - data = pout->pll_misc1;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
>
> - data = pin->pll_ie_trim;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
>
> - data = pin->pll_ip_trim;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
>
> - data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
>
> - data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
>
> - data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
>
> - data = pin->pll_icpmset << 3 | pin->pll_icpcset;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
>
> - data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
>
> - data = pin->pll_iptat_trim;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
>
> - data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
> }
>
> static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
> @@ -488,8 +381,7 @@ static void pll_14nm_software_reset(struct
> dsi_pll_14nm *pll_14nm)
> }
>
> static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
> - struct dsi_pll_input *pin,
> - struct dsi_pll_output *pout)
> + struct dsi_pll_config *pconf)
> {
> void __iomem *base = pll->phy->pll_base;
> void __iomem *cmn_base = pll->phy->base;
> @@ -497,57 +389,64 @@ static void pll_db_commit_14nm(struct
> dsi_pll_14nm *pll,
>
> DBG("DSI%d PLL", pll->phy->id);
>
> - data = pout->cmn_ldo_cntrl;
> - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
>
> - pll_db_commit_common(pll, pin, pout);
> + pll_db_commit_common(pll, pconf);
>
> pll_14nm_software_reset(pll);
>
> - data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
> - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
> + /* Use the /2 path in Mux */
> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
>
> data = 0xff; /* data, clk, pll normal operation */
> dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
>
> /* configure the frequency dependent pll registers */
> - data = pout->dec_start;
> + data = pconf->dec_start;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
>
> - data = pout->div_frac_start & 0xff;
> + data = pconf->div_frac_start & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
> - data = (pout->div_frac_start >> 8) & 0xff;
> + data = (pconf->div_frac_start >> 8) & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
> - data = (pout->div_frac_start >> 16) & 0xf;
> + data = (pconf->div_frac_start >> 16) & 0xf;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
>
> - data = pout->plllock_cmp & 0xff;
> + data = pconf->plllock_cmp & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
>
> - data = (pout->plllock_cmp >> 8) & 0xff;
> + data = (pconf->plllock_cmp >> 8) & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
>
> - data = (pout->plllock_cmp >> 16) & 0x3;
> + data = (pconf->plllock_cmp >> 16) & 0x3;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
>
> - data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
> + data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
>
> - data = pout->pll_vco_count & 0xff;
> + data = pconf->pll_vco_count & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
> - data = (pout->pll_vco_count >> 8) & 0xff;
> + data = (pconf->pll_vco_count >> 8) & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
>
> - data = pout->pll_kvco_count & 0xff;
> + data = pconf->pll_kvco_count & 0xff;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
> - data = (pout->pll_kvco_count >> 8) & 0x3;
> + data = (pconf->pll_kvco_count >> 8) & 0x3;
> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
>
> - data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
> + /*
> + * High nibble configures the post divider internal to the VCO. It's
> + * fixed to divide by 1 for now.
> + *
> + * 0: divided by 1
> + * 1: divided by 2
> + * 2: divided by 4
> + * 3: divided by 8
> + */
> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 |
> 3);
>
> - if (pin->ssc_en)
> - pll_db_commit_ssc(pll);
> + if (pconf->ssc_en)
> + pll_db_commit_ssc(pll, pconf);
>
> wmb(); /* make sure register committed */
> }
> @@ -559,35 +458,20 @@ static int dsi_pll_14nm_vco_set_rate(struct
> clk_hw *hw, unsigned long rate,
> unsigned long parent_rate)
> {
> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
> - struct dsi_pll_input *pin = &pll_14nm->in;
> - struct dsi_pll_output *pout = &pll_14nm->out;
> + struct dsi_pll_config conf;
>
> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
> parent_rate);
>
> - pll_14nm->vco_current_rate = rate;
> - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
> -
> - dsi_pll_14nm_input_init(pll_14nm);
> -
> - /*
> - * This configures the post divider internal to the VCO. It's
> - * fixed to divide by 1 for now.
> - *
> - * tx_band = pll_postdiv.
> - * 0: divided by 1
> - * 1: divided by 2
> - * 2: divided by 4
> - * 3: divided by 8
> - */
> - pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
> + dsi_pll_14nm_config_init(&conf);
> + conf.vco_current_rate = rate;
>
> - pll_14nm_dec_frac_calc(pll_14nm);
> + pll_14nm_dec_frac_calc(pll_14nm, &conf);
>
> - if (pin->ssc_en)
> - pll_14nm_ssc_calc(pll_14nm);
> + if (conf.ssc_en)
> + pll_14nm_ssc_calc(pll_14nm, &conf);
>
> - pll_14nm_calc_vco_count(pll_14nm);
> + pll_14nm_calc_vco_count(pll_14nm, &conf);
>
> /* commit the slave DSI PLL registers if we're master. Note that we
> * don't lock the slave PLL. We just ensure that the PLL/PHY
> registers
> @@ -596,10 +480,10 @@ static int dsi_pll_14nm_vco_set_rate(struct
> clk_hw *hw, unsigned long rate,
> if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>
> - pll_db_commit_14nm(pll_14nm_slave, pin, pout);
> + pll_db_commit_14nm(pll_14nm_slave, &conf);
> }
>
> - pll_db_commit_14nm(pll_14nm, pin, pout);
> + pll_db_commit_14nm(pll_14nm, &conf);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 4df237ad0eaf..ce6ae2fba993 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -36,43 +36,24 @@
> */
>
> #define VCO_REF_CLK_RATE 19200000
> -
> -struct dsi_pll_regs {
> - u32 pll_prop_gain_rate;
> - u32 pll_lockdet_rate;
> - u32 decimal_div_start;
> - u32 frac_div_start_low;
> - u32 frac_div_start_mid;
> - u32 frac_div_start_high;
> - u32 pll_clock_inverters;
> - u32 ssc_stepsize_low;
> - u32 ssc_stepsize_high;
> - u32 ssc_div_per_low;
> - u32 ssc_div_per_high;
> - u32 ssc_adjper_low;
> - u32 ssc_adjper_high;
> - u32 ssc_control;
> -};
> +#define FRAC_BITS 18
>
> /* Hardware is V4.1 */
> #define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
>
> struct dsi_pll_config {
> - u32 ref_freq;
> - bool div_override;
> - u32 output_div;
> - bool ignore_frac;
> - bool disable_prescaler;
> bool enable_ssc;
> bool ssc_center;
> - u32 dec_bits;
> - u32 frac_bits;
> - u32 lock_timer;
> u32 ssc_freq;
> u32 ssc_offset;
> u32 ssc_adj_per;
> - u32 thresh_cycles;
> - u32 refclk_cycles;
> +
> + /* out */
> + u32 decimal_div_start;
> + u32 frac_div_start;
> + u32 pll_clock_inverters;
> + u32 ssc_stepsize;
> + u32 ssc_div_per;
> };
>
> struct pll_7nm_cached_state {
> @@ -88,15 +69,11 @@ struct dsi_pll_7nm {
>
> struct msm_dsi_phy *phy;
>
> - u64 vco_ref_clk_rate;
> u64 vco_current_rate;
>
> /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - struct dsi_pll_config pll_configuration;
> - struct dsi_pll_regs reg_setup;
> -
> struct pll_7nm_cached_state cached_state;
>
> struct dsi_pll_7nm *slave;
> @@ -110,35 +87,20 @@ struct dsi_pll_7nm {
> */
> static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
>
> -static void dsi_pll_setup_config(struct dsi_pll_7nm *pll)
> +static void dsi_pll_setup_config(struct dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> -
> - config->ref_freq = pll->vco_ref_clk_rate;
> - config->output_div = 1;
> - config->dec_bits = 8;
> - config->frac_bits = 18;
> - config->lock_timer = 64;
> config->ssc_freq = 31500;
> config->ssc_offset = 4800;
> config->ssc_adj_per = 2;
> - config->thresh_cycles = 32;
> - config->refclk_cycles = 256;
> -
> - config->div_override = false;
> - config->ignore_frac = false;
> - config->disable_prescaler = false;
>
> /* TODO: ssc enable */
> config->enable_ssc = false;
> config->ssc_center = 0;
> }
>
> -static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
> +static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct
> dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
> - u64 fref = pll->vco_ref_clk_rate;
> + u64 fref = VCO_REF_CLK_RATE;
> u64 pll_freq;
> u64 divider;
> u64 dec, dec_multiple;
> @@ -147,42 +109,34 @@ static void dsi_pll_calc_dec_frac(struct
> dsi_pll_7nm *pll)
>
> pll_freq = pll->vco_current_rate;
>
> - if (config->disable_prescaler)
> - divider = fref;
> - else
> - divider = fref * 2;
> + divider = fref * 2;
>
> - multiplier = 1 << config->frac_bits;
> + multiplier = 1 << FRAC_BITS;
> dec_multiple = div_u64(pll_freq * multiplier, divider);
> div_u64_rem(dec_multiple, multiplier, &frac);
>
> dec = div_u64(dec_multiple, multiplier);
>
> if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
> - regs->pll_clock_inverters = 0x28;
> + config->pll_clock_inverters = 0x28;
> else if (pll_freq <= 1000000000ULL)
> - regs->pll_clock_inverters = 0xa0;
> + config->pll_clock_inverters = 0xa0;
> else if (pll_freq <= 2500000000ULL)
> - regs->pll_clock_inverters = 0x20;
> + config->pll_clock_inverters = 0x20;
> else if (pll_freq <= 3020000000ULL)
> - regs->pll_clock_inverters = 0x00;
> + config->pll_clock_inverters = 0x00;
> else
> - regs->pll_clock_inverters = 0x40;
> + config->pll_clock_inverters = 0x40;
>
> - regs->pll_lockdet_rate = config->lock_timer;
> - regs->decimal_div_start = dec;
> - regs->frac_div_start_low = (frac & 0xff);
> - regs->frac_div_start_mid = (frac & 0xff00) >> 8;
> - regs->frac_div_start_high = (frac & 0x30000) >> 16;
> + config->decimal_div_start = dec;
> + config->frac_div_start = frac;
> }
>
> #define SSC_CENTER BIT(0)
> #define SSC_EN BIT(1)
>
> -static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
> +static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct
> dsi_pll_config *config)
> {
> - struct dsi_pll_config *config = &pll->pll_configuration;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
> u32 ssc_per;
> u32 ssc_mod;
> u64 ssc_step_size;
> @@ -193,58 +147,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm
> *pll)
> return;
> }
>
> - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 -
> 1;
> + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 -
> 1;
> ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
> ssc_per -= ssc_mod;
>
> - frac = regs->frac_div_start_low |
> - (regs->frac_div_start_mid << 8) |
> - (regs->frac_div_start_high << 16);
> - ssc_step_size = regs->decimal_div_start;
> - ssc_step_size *= (1 << config->frac_bits);
> + frac = config->frac_div_start;
> + ssc_step_size = config->decimal_div_start;
> + ssc_step_size *= (1 << FRAC_BITS);
> ssc_step_size += frac;
> ssc_step_size *= config->ssc_offset;
> ssc_step_size *= (config->ssc_adj_per + 1);
> ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
> ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
>
> - regs->ssc_div_per_low = ssc_per & 0xFF;
> - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
> - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
> - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
> - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
> - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
> -
> - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
> + config->ssc_div_per = ssc_per;
> + config->ssc_stepsize = ssc_step_size;
>
> pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
> - regs->decimal_div_start, frac, config->frac_bits);
> + config->decimal_div_start, frac, FRAC_BITS);
> pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
> ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
> }
>
> -static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
> +static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct
> dsi_pll_config *config)
> {
> void __iomem *base = pll->phy->pll_base;
> - struct dsi_pll_regs *regs = &pll->reg_setup;
>
> - if (pll->pll_configuration.enable_ssc) {
> + if (config->enable_ssc) {
> pr_debug("SSC is enabled\n");
>
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
> - regs->ssc_stepsize_low);
> + config->ssc_stepsize & 0xff);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
> - regs->ssc_stepsize_high);
> + config->ssc_stepsize >> 8);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
> - regs->ssc_div_per_low);
> + config->ssc_div_per & 0xff);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
> - regs->ssc_div_per_high);
> + config->ssc_div_per >> 8);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
> - regs->ssc_adjper_low);
> + config->ssc_adj_per & 0xff);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
> - regs->ssc_adjper_high);
> + config->ssc_adj_per >> 8);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
> - SSC_EN | regs->ssc_control);
> + SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
> }
> }
>
> @@ -296,44 +241,46 @@ static void dsi_pll_config_hzindep_reg(struct
> dsi_pll_7nm *pll)
> }
> }
>
> -static void dsi_pll_commit(struct dsi_pll_7nm *pll)
> +static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct
> dsi_pll_config *config)
> {
> void __iomem *base = pll->phy->pll_base;
> - struct dsi_pll_regs *reg = &pll->reg_setup;
>
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
> reg->decimal_div_start);
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> reg->frac_div_start_low);
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
> reg->frac_div_start_mid);
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> reg->frac_div_start_high);
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1,
> reg->pll_lockdet_rate);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
> config->decimal_div_start);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
> + config->frac_div_start & 0xff);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
> + (config->frac_div_start & 0xff00) >> 8);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
> + (config->frac_div_start & 0x30000) >> 16);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO:
> 0x00 for CPHY */
> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
> reg->pll_clock_inverters);
> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
> config->pll_clock_inverters);
> }
>
> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long
> rate,
> unsigned long parent_rate)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> + struct dsi_pll_config config;
>
> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
> parent_rate);
>
> pll_7nm->vco_current_rate = rate;
> - pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
>
> - dsi_pll_setup_config(pll_7nm);
> + dsi_pll_setup_config(&config);
>
> - dsi_pll_calc_dec_frac(pll_7nm);
> + dsi_pll_calc_dec_frac(pll_7nm, &config);
>
> - dsi_pll_calc_ssc(pll_7nm);
> + dsi_pll_calc_ssc(pll_7nm, &config);
>
> - dsi_pll_commit(pll_7nm);
> + dsi_pll_commit(pll_7nm, &config);
>
> dsi_pll_config_hzindep_reg(pll_7nm);
>
> - dsi_pll_ssc_commit(pll_7nm);
> + dsi_pll_ssc_commit(pll_7nm, &config);
>
> /* flush, ensure all register writes are done*/
> wmb();
> @@ -486,9 +433,8 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> - struct dsi_pll_config *config = &pll_7nm->pll_configuration;
> void __iomem *base = pll_7nm->phy->pll_base;
> - u64 ref_clk = pll_7nm->vco_ref_clk_rate;
> + u64 ref_clk = VCO_REF_CLK_RATE;
> u64 vco_rate = 0x0;
> u64 multiplier;
> u32 frac;
> @@ -508,7 +454,7 @@ static unsigned long
> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> * TODO:
> * 1. Assumes prescaler is disabled
> */
> - multiplier = 1 << config->frac_bits;
> + multiplier = 1 << FRAC_BITS;
> pll_freq = dec * (ref_clk * 2);
> tmp64 = (ref_clk * 2 * frac);
> pll_freq += div_u64(tmp64, multiplier);
> @@ -590,7 +536,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy
> *phy)
> val |= cached->pll_mux;
> dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>
> - ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
> + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
> pll_7nm->vco_current_rate, VCO_REF_CLK_RATE);
> if (ret) {
> DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
> "restore vco rate failed. ret=%d\n", ret);
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure
2021-03-30 3:26 ` [Freedreno] " abhinavk
@ 2021-03-30 15:23 ` Dmitry Baryshkov
0 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-30 15:23 UTC (permalink / raw)
To: abhinavk
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 30/03/2021 06:26, abhinavk@codeaurora.org wrote:
> On 2021-03-27 04:03, Dmitry Baryshkov wrote:
>> The 7nm, 10nm and 14nm drivers would store interim data used during
>> VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data
>> structures to the onstack storage. While we are at it, drop
>> unused/static 'config' data, unused config fields, etc.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Thank you for the thorough review. I'll post v4 as soon as we agree on
the patch 24.
>> ---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 167 ++++-------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 334 +++++++--------------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 166 ++++------
>> 3 files changed, 220 insertions(+), 447 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> index b937e77b3c37..1fbb54f4df98 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> @@ -36,43 +36,25 @@
>> */
>>
>> #define VCO_REF_CLK_RATE 19200000
>> -
>> -struct dsi_pll_regs {
>> - u32 pll_prop_gain_rate;
>> - u32 pll_lockdet_rate;
>> - u32 decimal_div_start;
>> - u32 frac_div_start_low;
>> - u32 frac_div_start_mid;
>> - u32 frac_div_start_high;
>> - u32 pll_clock_inverters;
>> - u32 ssc_stepsize_low;
>> - u32 ssc_stepsize_high;
>> - u32 ssc_div_per_low;
>> - u32 ssc_div_per_high;
>> - u32 ssc_adjper_low;
>> - u32 ssc_adjper_high;
>> - u32 ssc_control;
>> -};
>> +#define FRAC_BITS 18
>>
>> /* v3.0.0 10nm implementation that requires the old timings settings */
>> #define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0)
>>
>> struct dsi_pll_config {
>> - u32 ref_freq;
>> - bool div_override;
>> - u32 output_div;
>> - bool ignore_frac;
>> - bool disable_prescaler;
>> bool enable_ssc;
>> bool ssc_center;
>> - u32 dec_bits;
>> - u32 frac_bits;
>> - u32 lock_timer;
>> u32 ssc_freq;
>> u32 ssc_offset;
>> u32 ssc_adj_per;
>> - u32 thresh_cycles;
>> - u32 refclk_cycles;
>> +
>> + /* out */
>> + u32 pll_prop_gain_rate;
>> + u32 decimal_div_start;
>> + u32 frac_div_start;
>> + u32 pll_clock_inverters;
>> + u32 ssc_stepsize;
>> + u32 ssc_div_per;
>> };
>>
>> struct pll_10nm_cached_state {
>> @@ -88,15 +70,11 @@ struct dsi_pll_10nm {
>>
>> struct msm_dsi_phy *phy;
>>
>> - u64 vco_ref_clk_rate;
>> u64 vco_current_rate;
>>
>> /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
>> spinlock_t postdiv_lock;
>>
>> - struct dsi_pll_config pll_configuration;
>> - struct dsi_pll_regs reg_setup;
>> -
>> struct pll_10nm_cached_state cached_state;
>>
>> struct dsi_pll_10nm *slave;
>> @@ -110,34 +88,19 @@ struct dsi_pll_10nm {
>> */
>> static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
>>
>> -static void dsi_pll_setup_config(struct dsi_pll_10nm *pll)
>> +static void dsi_pll_setup_config(struct dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> -
>> - config->ref_freq = pll->vco_ref_clk_rate;
>> - config->output_div = 1;
>> - config->dec_bits = 8;
>> - config->frac_bits = 18;
>> - config->lock_timer = 64;
>> config->ssc_freq = 31500;
>> config->ssc_offset = 5000;
>> config->ssc_adj_per = 2;
>> - config->thresh_cycles = 32;
>> - config->refclk_cycles = 256;
>> -
>> - config->div_override = false;
>> - config->ignore_frac = false;
>> - config->disable_prescaler = false;
>>
>> config->enable_ssc = false;
>> - config->ssc_center = 0;
>> + config->ssc_center = false;
>> }
>>
>> -static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
>> +static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct
>> dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>> - u64 fref = pll->vco_ref_clk_rate;
>> + u64 fref = VCO_REF_CLK_RATE;
>> u64 pll_freq;
>> u64 divider;
>> u64 dec, dec_multiple;
>> @@ -146,40 +109,32 @@ static void dsi_pll_calc_dec_frac(struct
>> dsi_pll_10nm *pll)
>>
>> pll_freq = pll->vco_current_rate;
>>
>> - if (config->disable_prescaler)
>> - divider = fref;
>> - else
>> - divider = fref * 2;
>> + divider = fref * 2;
>>
>> - multiplier = 1 << config->frac_bits;
>> + multiplier = 1 << FRAC_BITS;
>> dec_multiple = div_u64(pll_freq * multiplier, divider);
>> dec = div_u64_rem(dec_multiple, multiplier, &frac);
>>
>> if (pll_freq <= 1900000000UL)
>> - regs->pll_prop_gain_rate = 8;
>> + config->pll_prop_gain_rate = 8;
>> else if (pll_freq <= 3000000000UL)
>> - regs->pll_prop_gain_rate = 10;
>> + config->pll_prop_gain_rate = 10;
>> else
>> - regs->pll_prop_gain_rate = 12;
>> + config->pll_prop_gain_rate = 12;
>> if (pll_freq < 1100000000UL)
>> - regs->pll_clock_inverters = 8;
>> + config->pll_clock_inverters = 8;
>> else
>> - regs->pll_clock_inverters = 0;
>> + config->pll_clock_inverters = 0;
>>
>> - regs->pll_lockdet_rate = config->lock_timer;
>> - regs->decimal_div_start = dec;
>> - regs->frac_div_start_low = (frac & 0xff);
>> - regs->frac_div_start_mid = (frac & 0xff00) >> 8;
>> - regs->frac_div_start_high = (frac & 0x30000) >> 16;
>> + config->decimal_div_start = dec;
>> + config->frac_div_start = frac;
>> }
>>
>> #define SSC_CENTER BIT(0)
>> #define SSC_EN BIT(1)
>>
>> -static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
>> +static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct
>> dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>> u32 ssc_per;
>> u32 ssc_mod;
>> u64 ssc_step_size;
>> @@ -190,58 +145,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm
>> *pll)
>> return;
>> }
>>
>> - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) /
>> 2 - 1;
>> + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) /
>> 2 - 1;
>> ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
>> ssc_per -= ssc_mod;
>>
>> - frac = regs->frac_div_start_low |
>> - (regs->frac_div_start_mid << 8) |
>> - (regs->frac_div_start_high << 16);
>> - ssc_step_size = regs->decimal_div_start;
>> - ssc_step_size *= (1 << config->frac_bits);
>> + frac = config->frac_div_start;
>> + ssc_step_size = config->decimal_div_start;
>> + ssc_step_size *= (1 << FRAC_BITS);
>> ssc_step_size += frac;
>> ssc_step_size *= config->ssc_offset;
>> ssc_step_size *= (config->ssc_adj_per + 1);
>> ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
>> ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
>>
>> - regs->ssc_div_per_low = ssc_per & 0xFF;
>> - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
>> - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
>> - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
>> - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
>> - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
>> -
>> - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
>> + config->ssc_div_per = ssc_per;
>> + config->ssc_stepsize = ssc_step_size;
>>
>> pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
>> - regs->decimal_div_start, frac, config->frac_bits);
>> + config->decimal_div_start, frac, FRAC_BITS);
>> pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
>> ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
>> }
>>
>> -static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
>> +static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct
>> dsi_pll_config *config)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>>
>> - if (pll->pll_configuration.enable_ssc) {
>> + if (config->enable_ssc) {
>> pr_debug("SSC is enabled\n");
>>
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
>> - regs->ssc_stepsize_low);
>> + config->ssc_stepsize & 0xff);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
>> - regs->ssc_stepsize_high);
>> + config->ssc_stepsize >> 8);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
>> - regs->ssc_div_per_low);
>> + config->ssc_div_per & 0xff);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
>> - regs->ssc_div_per_high);
>> + config->ssc_div_per >> 8);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
>> - regs->ssc_adjper_low);
>> + config->ssc_adj_per & 0xff);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
>> - regs->ssc_adjper_high);
>> + config->ssc_adj_per >> 8);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
>> - SSC_EN | regs->ssc_control);
>> + SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
>> }
>> }
>>
>> @@ -271,50 +217,48 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_10nm *pll)
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
>> }
>>
>> -static void dsi_pll_commit(struct dsi_pll_10nm *pll)
>> +static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct
>> dsi_pll_config *config)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> - struct dsi_pll_regs *reg = &pll->reg_setup;
>>
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE,
>> 0x12);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
>> - reg->decimal_div_start);
>> + config->decimal_div_start);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
>> - reg->frac_div_start_low);
>> + config->frac_div_start & 0xff);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
>> - reg->frac_div_start_mid);
>> + (config->frac_div_start & 0xff00) >> 8);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
>> - reg->frac_div_start_high);
>> - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
>> - reg->pll_lockdet_rate);
>> + (config->frac_div_start & 0x30000) >> 16);
>> + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
>> dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
>> - reg->pll_clock_inverters);
>> + config->pll_clock_inverters);
>> }
>>
>> static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>> + struct dsi_pll_config config;
>>
>> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
>> parent_rate);
>>
>> pll_10nm->vco_current_rate = rate;
>> - pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
>>
>> - dsi_pll_setup_config(pll_10nm);
>> + dsi_pll_setup_config(&config);
>>
>> - dsi_pll_calc_dec_frac(pll_10nm);
>> + dsi_pll_calc_dec_frac(pll_10nm, &config);
>>
>> - dsi_pll_calc_ssc(pll_10nm);
>> + dsi_pll_calc_ssc(pll_10nm, &config);
>>
>> - dsi_pll_commit(pll_10nm);
>> + dsi_pll_commit(pll_10nm, &config);
>>
>> dsi_pll_config_hzindep_reg(pll_10nm);
>>
>> - dsi_pll_ssc_commit(pll_10nm);
>> + dsi_pll_ssc_commit(pll_10nm, &config);
>>
>> /* flush, ensure all register writes are done*/
>> wmb();
>> @@ -461,9 +405,8 @@ static unsigned long
>> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>> - struct dsi_pll_config *config = &pll_10nm->pll_configuration;
>> void __iomem *base = pll_10nm->phy->pll_base;
>> - u64 ref_clk = pll_10nm->vco_ref_clk_rate;
>> + u64 ref_clk = VCO_REF_CLK_RATE;
>> u64 vco_rate = 0x0;
>> u64 multiplier;
>> u32 frac;
>> @@ -483,7 +426,7 @@ static unsigned long
>> dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
>> * TODO:
>> * 1. Assumes prescaler is disabled
>> */
>> - multiplier = 1 << config->frac_bits;
>> + multiplier = 1 << FRAC_BITS;
>> pll_freq = dec * (ref_clk * 2);
>> tmp64 = (ref_clk * 2 * frac);
>> pll_freq += div_u64(tmp64, multiplier);
>> @@ -565,7 +508,7 @@ static int dsi_10nm_restore_state(struct
>> msm_dsi_phy *phy)
>> val |= cached->pll_mux;
>> dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
>>
>> - ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
>> pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
>> + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
>> pll_10nm->vco_current_rate, VCO_REF_CLK_RATE);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
>> "restore vco rate failed. ret=%d\n", ret);
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> index 8b4865c5796d..d08ad0c632b4 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> @@ -37,51 +37,19 @@
>> #define VCO_MIN_RATE 1300000000UL
>> #define VCO_MAX_RATE 2600000000UL
>>
>> -#define DSI_PLL_DEFAULT_VCO_POSTDIV 1
>> +struct dsi_pll_config {
>> + u64 vco_current_rate;
>>
>> -struct dsi_pll_input {
>> - u32 fref; /* reference clk */
>> - u32 fdata; /* bit clock rate */
>> - u32 dsiclk_sel; /* Mux configuration (see diagram) */
>> u32 ssc_en; /* SSC enable/disable */
>> - u32 ldo_en;
>>
>> /* fixed params */
>> - u32 refclk_dbler_en;
>> - u32 vco_measure_time;
>> - u32 kvco_measure_time;
>> - u32 bandgap_timer;
>> - u32 pll_wakeup_timer;
>> u32 plllock_cnt;
>> - u32 plllock_rng;
>> u32 ssc_center;
>> u32 ssc_adj_period;
>> u32 ssc_spread;
>> u32 ssc_freq;
>> - u32 pll_ie_trim;
>> - u32 pll_ip_trim;
>> - u32 pll_iptat_trim;
>> - u32 pll_cpcset_cur;
>> - u32 pll_cpmset_cur;
>> -
>> - u32 pll_icpmset;
>> - u32 pll_icpcset;
>> -
>> - u32 pll_icpmset_p;
>> - u32 pll_icpmset_m;
>> -
>> - u32 pll_icpcset_p;
>> - u32 pll_icpcset_m;
>> -
>> - u32 pll_lpf_res1;
>> - u32 pll_lpf_cap1;
>> - u32 pll_lpf_cap2;
>> - u32 pll_c3ctrl;
>> - u32 pll_r3ctrl;
>> -};
>>
>> -struct dsi_pll_output {
>> - u32 pll_txclk_en;
>> + /* calculated */
>> u32 dec_start;
>> u32 div_frac_start;
>> u32 ssc_period;
>> @@ -91,19 +59,6 @@ struct dsi_pll_output {
>> u32 pll_vco_count;
>> u32 pll_kvco_div_ref;
>> u32 pll_kvco_count;
>> - u32 pll_misc1;
>> - u32 pll_lpf2_postdiv;
>> - u32 pll_resetsm_cntrl;
>> - u32 pll_resetsm_cntrl2;
>> - u32 pll_resetsm_cntrl5;
>> - u32 pll_kvco_code;
>> -
>> - u32 cmn_clk_cfg0;
>> - u32 cmn_clk_cfg1;
>> - u32 cmn_ldo_cntrl;
>> -
>> - u32 pll_postdiv;
>> - u32 fcvo;
>> };
>>
>> struct pll_14nm_cached_state {
>> @@ -117,15 +72,9 @@ struct dsi_pll_14nm {
>>
>> struct msm_dsi_phy *phy;
>>
>> - struct dsi_pll_input in;
>> - struct dsi_pll_output out;
>> -
>> /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
>> spinlock_t postdiv_lock;
>>
>> - u64 vco_current_rate;
>> - u64 vco_ref_clk_rate;
>> -
>> struct pll_14nm_cached_state cached_state;
>>
>> struct dsi_pll_14nm *slave;
>> @@ -195,78 +144,50 @@ static bool pll_14nm_poll_for_ready(struct
>> dsi_pll_14nm *pll_14nm,
>> return pll_locked;
>> }
>>
>> -static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
>> +static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
>> {
>> - pll->in.fref = pll->vco_ref_clk_rate;
>> - pll->in.fdata = 0;
>> - pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
>> - pll->in.ldo_en = 0; /* disabled for now */
>> -
>> /* fixed input */
>> - pll->in.refclk_dbler_en = 0;
>> - pll->in.vco_measure_time = 5;
>> - pll->in.kvco_measure_time = 5;
>> - pll->in.bandgap_timer = 4;
>> - pll->in.pll_wakeup_timer = 5;
>> - pll->in.plllock_cnt = 1;
>> - pll->in.plllock_rng = 0;
>> + pconf->plllock_cnt = 1;
>>
>> /*
>> * SSC is enabled by default. We might need DT props for configuring
>> * some SSC params like PPM and center/down spread etc.
>> */
>> - pll->in.ssc_en = 1;
>> - pll->in.ssc_center = 0; /* down spread by default */
>> - pll->in.ssc_spread = 5; /* PPM / 1000 */
>> - pll->in.ssc_freq = 31500; /* default recommended */
>> - pll->in.ssc_adj_period = 37;
>> -
>> - pll->in.pll_ie_trim = 4;
>> - pll->in.pll_ip_trim = 4;
>> - pll->in.pll_cpcset_cur = 1;
>> - pll->in.pll_cpmset_cur = 1;
>> - pll->in.pll_icpmset = 4;
>> - pll->in.pll_icpcset = 4;
>> - pll->in.pll_icpmset_p = 0;
>> - pll->in.pll_icpmset_m = 0;
>> - pll->in.pll_icpcset_p = 0;
>> - pll->in.pll_icpcset_m = 0;
>> - pll->in.pll_lpf_res1 = 3;
>> - pll->in.pll_lpf_cap1 = 11;
>> - pll->in.pll_lpf_cap2 = 1;
>> - pll->in.pll_iptat_trim = 7;
>> - pll->in.pll_c3ctrl = 2;
>> - pll->in.pll_r3ctrl = 1;
>> + pconf->ssc_en = 1;
>> + pconf->ssc_center = 0; /* down spread by default */
>> + pconf->ssc_spread = 5; /* PPM / 1000 */
>> + pconf->ssc_freq = 31500; /* default recommended */
>> + pconf->ssc_adj_period = 37;
>> }
>>
>> #define CEIL(x, y) (((x) + ((y) - 1)) / (y))
>>
>> -static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
>> +static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct
>> dsi_pll_config *pconf)
>> {
>> u32 period, ssc_period;
>> u32 ref, rem;
>> u64 step_size;
>>
>> - DBG("vco=%lld ref=%lld", pll->vco_current_rate,
>> pll->vco_ref_clk_rate);
>> + DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
>>
>> - ssc_period = pll->in.ssc_freq / 500;
>> - period = (u32)pll->vco_ref_clk_rate / 1000;
>> + ssc_period = pconf->ssc_freq / 500;
>> + period = (u32)VCO_REF_CLK_RATE / 1000;
>> ssc_period = CEIL(period, ssc_period);
>> ssc_period -= 1;
>> - pll->out.ssc_period = ssc_period;
>> + pconf->ssc_period = ssc_period;
>>
>> - DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
>> - pll->in.ssc_spread, pll->out.ssc_period);
>> + DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
>> + pconf->ssc_spread, pconf->ssc_period);
>>
>> - step_size = (u32)pll->vco_current_rate;
>> - ref = pll->vco_ref_clk_rate;
>> + step_size = (u32)pconf->vco_current_rate;
>> + ref = VCO_REF_CLK_RATE;
>> ref /= 1000;
>> step_size = div_u64(step_size, ref);
>> step_size <<= 20;
>> step_size = div_u64(step_size, 1000);
>> - step_size *= pll->in.ssc_spread;
>> + step_size *= pconf->ssc_spread;
>> step_size = div_u64(step_size, 1000);
>> - step_size *= (pll->in.ssc_adj_period + 1);
>> + step_size *= (pconf->ssc_adj_period + 1);
>>
>> rem = 0;
>> step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
>> @@ -277,18 +198,16 @@ static void pll_14nm_ssc_calc(struct
>> dsi_pll_14nm *pll)
>>
>> step_size &= 0x0ffff; /* take lower 16 bits */
>>
>> - pll->out.ssc_step_size = step_size;
>> + pconf->ssc_step_size = step_size;
>> }
>>
>> -static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
>> +static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct
>> dsi_pll_config *pconf)
>> {
>> - struct dsi_pll_input *pin = &pll->in;
>> - struct dsi_pll_output *pout = &pll->out;
>> u64 multiplier = BIT(20);
>> u64 dec_start_multiple, dec_start, pll_comp_val;
>> u32 duration, div_frac_start;
>> - u64 vco_clk_rate = pll->vco_current_rate;
>> - u64 fref = pll->vco_ref_clk_rate;
>> + u64 vco_clk_rate = pconf->vco_current_rate;
>> + u64 fref = VCO_REF_CLK_RATE;
>>
>> DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
>>
>> @@ -297,14 +216,14 @@ static void pll_14nm_dec_frac_calc(struct
>> dsi_pll_14nm *pll)
>>
>> dec_start = div_u64(dec_start_multiple, multiplier);
>>
>> - pout->dec_start = (u32)dec_start;
>> - pout->div_frac_start = div_frac_start;
>> + pconf->dec_start = (u32)dec_start;
>> + pconf->div_frac_start = div_frac_start;
>>
>> - if (pin->plllock_cnt == 0)
>> + if (pconf->plllock_cnt == 0)
>> duration = 1024;
>> - else if (pin->plllock_cnt == 1)
>> + else if (pconf->plllock_cnt == 1)
>> duration = 256;
>> - else if (pin->plllock_cnt == 2)
>> + else if (pconf->plllock_cnt == 2)
>> duration = 128;
>> else
>> duration = 32;
>> @@ -313,10 +232,7 @@ static void pll_14nm_dec_frac_calc(struct
>> dsi_pll_14nm *pll)
>> pll_comp_val = div_u64(pll_comp_val, multiplier);
>> do_div(pll_comp_val, 10);
>>
>> - pout->plllock_cmp = (u32)pll_comp_val;
>> -
>> - pout->pll_txclk_en = 1;
>> - pout->cmn_ldo_cntrl = 0x3c;
>> + pconf->plllock_cmp = (u32)pll_comp_val;
>> }
>>
>> static u32 pll_14nm_kvco_slop(u32 vrate)
>> @@ -333,74 +249,66 @@ static u32 pll_14nm_kvco_slop(u32 vrate)
>> return slop;
>> }
>>
>> -static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
>> +static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct
>> dsi_pll_config *pconf)
>> {
>> - struct dsi_pll_input *pin = &pll->in;
>> - struct dsi_pll_output *pout = &pll->out;
>> - u64 vco_clk_rate = pll->vco_current_rate;
>> - u64 fref = pll->vco_ref_clk_rate;
>> + u64 vco_clk_rate = pconf->vco_current_rate;
>> + u64 fref = VCO_REF_CLK_RATE;
>> + u32 vco_measure_time = 5;
>> + u32 kvco_measure_time = 5;
>> u64 data;
>> u32 cnt;
>>
>> - data = fref * pin->vco_measure_time;
>> + data = fref * vco_measure_time;
>> do_div(data, 1000000);
>> data &= 0x03ff; /* 10 bits */
>> data -= 2;
>> - pout->pll_vco_div_ref = data;
>> + pconf->pll_vco_div_ref = data;
>>
>> data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
>> - data *= pin->vco_measure_time;
>> + data *= vco_measure_time;
>> do_div(data, 10);
>> - pout->pll_vco_count = data;
>> + pconf->pll_vco_count = data;
>>
>> - data = fref * pin->kvco_measure_time;
>> + data = fref * kvco_measure_time;
>> do_div(data, 1000000);
>> data &= 0x03ff; /* 10 bits */
>> data -= 1;
>> - pout->pll_kvco_div_ref = data;
>> + pconf->pll_kvco_div_ref = data;
>>
>> cnt = pll_14nm_kvco_slop(vco_clk_rate);
>> cnt *= 2;
>> cnt /= 100;
>> - cnt *= pin->kvco_measure_time;
>> - pout->pll_kvco_count = cnt;
>> -
>> - pout->pll_misc1 = 16;
>> - pout->pll_resetsm_cntrl = 48;
>> - pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
>> - pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
>> - pout->pll_kvco_code = 0;
>> + cnt *= kvco_measure_time;
>> + pconf->pll_kvco_count = cnt;
>> }
>>
>> -static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
>> +static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct
>> dsi_pll_config *pconf)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> - struct dsi_pll_input *pin = &pll->in;
>> - struct dsi_pll_output *pout = &pll->out;
>> u8 data;
>>
>> - data = pin->ssc_adj_period;
>> + data = pconf->ssc_adj_period;
>> data &= 0x0ff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
>> - data = (pin->ssc_adj_period >> 8);
>> + data = (pconf->ssc_adj_period >> 8);
>> data &= 0x03;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
>>
>> - data = pout->ssc_period;
>> + data = pconf->ssc_period;
>> data &= 0x0ff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
>> - data = (pout->ssc_period >> 8);
>> + data = (pconf->ssc_period >> 8);
>> data &= 0x0ff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
>>
>> - data = pout->ssc_step_size;
>> + data = pconf->ssc_step_size;
>> data &= 0x0ff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
>> - data = (pout->ssc_step_size >> 8);
>> + data = (pconf->ssc_step_size >> 8);
>> data &= 0x0ff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
>>
>> - data = (pin->ssc_center & 0x01);
>> + data = (pconf->ssc_center & 0x01);
>> data <<= 1;
>> data |= 0x01; /* enable */
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
>> @@ -409,8 +317,7 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm
>> *pll)
>> }
>>
>> static void pll_db_commit_common(struct dsi_pll_14nm *pll,
>> - struct dsi_pll_input *pin,
>> - struct dsi_pll_output *pout)
>> + struct dsi_pll_config *pconf)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> u8 data;
>> @@ -419,55 +326,41 @@ static void pll_db_commit_common(struct
>> dsi_pll_14nm *pll,
>> data = 0;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
>>
>> - data = pout->pll_txclk_en;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
>>
>> - data = pout->pll_resetsm_cntrl;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
>> - data = pout->pll_resetsm_cntrl2;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
>> - data = pout->pll_resetsm_cntrl5;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3);
>> /* bandgap_timer */
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /*
>> pll_wakeup_timer */
>>
>> - data = pout->pll_vco_div_ref & 0xff;
>> + data = pconf->pll_vco_div_ref & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
>> - data = (pout->pll_vco_div_ref >> 8) & 0x3;
>> + data = (pconf->pll_vco_div_ref >> 8) & 0x3;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
>>
>> - data = pout->pll_kvco_div_ref & 0xff;
>> + data = pconf->pll_kvco_div_ref & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
>> - data = (pout->pll_kvco_div_ref >> 8) & 0x3;
>> + data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
>>
>> - data = pout->pll_misc1;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
>>
>> - data = pin->pll_ie_trim;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
>>
>> - data = pin->pll_ip_trim;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
>>
>> - data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
>>
>> - data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
>>
>> - data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
>>
>> - data = pin->pll_icpmset << 3 | pin->pll_icpcset;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
>>
>> - data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
>>
>> - data = pin->pll_iptat_trim;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
>>
>> - data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
>> }
>>
>> static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
>> @@ -488,8 +381,7 @@ static void pll_14nm_software_reset(struct
>> dsi_pll_14nm *pll_14nm)
>> }
>>
>> static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
>> - struct dsi_pll_input *pin,
>> - struct dsi_pll_output *pout)
>> + struct dsi_pll_config *pconf)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> void __iomem *cmn_base = pll->phy->base;
>> @@ -497,57 +389,64 @@ static void pll_db_commit_14nm(struct
>> dsi_pll_14nm *pll,
>>
>> DBG("DSI%d PLL", pll->phy->id);
>>
>> - data = pout->cmn_ldo_cntrl;
>> - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
>> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
>>
>> - pll_db_commit_common(pll, pin, pout);
>> + pll_db_commit_common(pll, pconf);
>>
>> pll_14nm_software_reset(pll);
>>
>> - data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
>> - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
>> + /* Use the /2 path in Mux */
>> + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
>>
>> data = 0xff; /* data, clk, pll normal operation */
>> dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
>>
>> /* configure the frequency dependent pll registers */
>> - data = pout->dec_start;
>> + data = pconf->dec_start;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
>>
>> - data = pout->div_frac_start & 0xff;
>> + data = pconf->div_frac_start & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
>> - data = (pout->div_frac_start >> 8) & 0xff;
>> + data = (pconf->div_frac_start >> 8) & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
>> - data = (pout->div_frac_start >> 16) & 0xf;
>> + data = (pconf->div_frac_start >> 16) & 0xf;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
>>
>> - data = pout->plllock_cmp & 0xff;
>> + data = pconf->plllock_cmp & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
>>
>> - data = (pout->plllock_cmp >> 8) & 0xff;
>> + data = (pconf->plllock_cmp >> 8) & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
>>
>> - data = (pout->plllock_cmp >> 16) & 0x3;
>> + data = (pconf->plllock_cmp >> 16) & 0x3;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
>>
>> - data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
>> + data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
>>
>> - data = pout->pll_vco_count & 0xff;
>> + data = pconf->pll_vco_count & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
>> - data = (pout->pll_vco_count >> 8) & 0xff;
>> + data = (pconf->pll_vco_count >> 8) & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
>>
>> - data = pout->pll_kvco_count & 0xff;
>> + data = pconf->pll_kvco_count & 0xff;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
>> - data = (pout->pll_kvco_count >> 8) & 0x3;
>> + data = (pconf->pll_kvco_count >> 8) & 0x3;
>> dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
>>
>> - data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
>> - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
>> + /*
>> + * High nibble configures the post divider internal to the VCO. It's
>> + * fixed to divide by 1 for now.
>> + *
>> + * 0: divided by 1
>> + * 1: divided by 2
>> + * 2: divided by 4
>> + * 3: divided by 8
>> + */
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 <<
>> 4 | 3);
>>
>> - if (pin->ssc_en)
>> - pll_db_commit_ssc(pll);
>> + if (pconf->ssc_en)
>> + pll_db_commit_ssc(pll, pconf);
>>
>> wmb(); /* make sure register committed */
>> }
>> @@ -559,35 +458,20 @@ static int dsi_pll_14nm_vco_set_rate(struct
>> clk_hw *hw, unsigned long rate,
>> unsigned long parent_rate)
>> {
>> struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
>> - struct dsi_pll_input *pin = &pll_14nm->in;
>> - struct dsi_pll_output *pout = &pll_14nm->out;
>> + struct dsi_pll_config conf;
>>
>> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
>> parent_rate);
>>
>> - pll_14nm->vco_current_rate = rate;
>> - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
>> -
>> - dsi_pll_14nm_input_init(pll_14nm);
>> -
>> - /*
>> - * This configures the post divider internal to the VCO. It's
>> - * fixed to divide by 1 for now.
>> - *
>> - * tx_band = pll_postdiv.
>> - * 0: divided by 1
>> - * 1: divided by 2
>> - * 2: divided by 4
>> - * 3: divided by 8
>> - */
>> - pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
>> + dsi_pll_14nm_config_init(&conf);
>> + conf.vco_current_rate = rate;
>>
>> - pll_14nm_dec_frac_calc(pll_14nm);
>> + pll_14nm_dec_frac_calc(pll_14nm, &conf);
>>
>> - if (pin->ssc_en)
>> - pll_14nm_ssc_calc(pll_14nm);
>> + if (conf.ssc_en)
>> + pll_14nm_ssc_calc(pll_14nm, &conf);
>>
>> - pll_14nm_calc_vco_count(pll_14nm);
>> + pll_14nm_calc_vco_count(pll_14nm, &conf);
>>
>> /* commit the slave DSI PLL registers if we're master. Note that we
>> * don't lock the slave PLL. We just ensure that the PLL/PHY
>> registers
>> @@ -596,10 +480,10 @@ static int dsi_pll_14nm_vco_set_rate(struct
>> clk_hw *hw, unsigned long rate,
>> if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
>> struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
>>
>> - pll_db_commit_14nm(pll_14nm_slave, pin, pout);
>> + pll_db_commit_14nm(pll_14nm_slave, &conf);
>> }
>>
>> - pll_db_commit_14nm(pll_14nm, pin, pout);
>> + pll_db_commit_14nm(pll_14nm, &conf);
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 4df237ad0eaf..ce6ae2fba993 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -36,43 +36,24 @@
>> */
>>
>> #define VCO_REF_CLK_RATE 19200000
>> -
>> -struct dsi_pll_regs {
>> - u32 pll_prop_gain_rate;
>> - u32 pll_lockdet_rate;
>> - u32 decimal_div_start;
>> - u32 frac_div_start_low;
>> - u32 frac_div_start_mid;
>> - u32 frac_div_start_high;
>> - u32 pll_clock_inverters;
>> - u32 ssc_stepsize_low;
>> - u32 ssc_stepsize_high;
>> - u32 ssc_div_per_low;
>> - u32 ssc_div_per_high;
>> - u32 ssc_adjper_low;
>> - u32 ssc_adjper_high;
>> - u32 ssc_control;
>> -};
>> +#define FRAC_BITS 18
>>
>> /* Hardware is V4.1 */
>> #define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
>>
>> struct dsi_pll_config {
>> - u32 ref_freq;
>> - bool div_override;
>> - u32 output_div;
>> - bool ignore_frac;
>> - bool disable_prescaler;
>> bool enable_ssc;
>> bool ssc_center;
>> - u32 dec_bits;
>> - u32 frac_bits;
>> - u32 lock_timer;
>> u32 ssc_freq;
>> u32 ssc_offset;
>> u32 ssc_adj_per;
>> - u32 thresh_cycles;
>> - u32 refclk_cycles;
>> +
>> + /* out */
>> + u32 decimal_div_start;
>> + u32 frac_div_start;
>> + u32 pll_clock_inverters;
>> + u32 ssc_stepsize;
>> + u32 ssc_div_per;
>> };
>>
>> struct pll_7nm_cached_state {
>> @@ -88,15 +69,11 @@ struct dsi_pll_7nm {
>>
>> struct msm_dsi_phy *phy;
>>
>> - u64 vco_ref_clk_rate;
>> u64 vco_current_rate;
>>
>> /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
>> spinlock_t postdiv_lock;
>>
>> - struct dsi_pll_config pll_configuration;
>> - struct dsi_pll_regs reg_setup;
>> -
>> struct pll_7nm_cached_state cached_state;
>>
>> struct dsi_pll_7nm *slave;
>> @@ -110,35 +87,20 @@ struct dsi_pll_7nm {
>> */
>> static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
>>
>> -static void dsi_pll_setup_config(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_setup_config(struct dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> -
>> - config->ref_freq = pll->vco_ref_clk_rate;
>> - config->output_div = 1;
>> - config->dec_bits = 8;
>> - config->frac_bits = 18;
>> - config->lock_timer = 64;
>> config->ssc_freq = 31500;
>> config->ssc_offset = 4800;
>> config->ssc_adj_per = 2;
>> - config->thresh_cycles = 32;
>> - config->refclk_cycles = 256;
>> -
>> - config->div_override = false;
>> - config->ignore_frac = false;
>> - config->disable_prescaler = false;
>>
>> /* TODO: ssc enable */
>> config->enable_ssc = false;
>> config->ssc_center = 0;
>> }
>>
>> -static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct
>> dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>> - u64 fref = pll->vco_ref_clk_rate;
>> + u64 fref = VCO_REF_CLK_RATE;
>> u64 pll_freq;
>> u64 divider;
>> u64 dec, dec_multiple;
>> @@ -147,42 +109,34 @@ static void dsi_pll_calc_dec_frac(struct
>> dsi_pll_7nm *pll)
>>
>> pll_freq = pll->vco_current_rate;
>>
>> - if (config->disable_prescaler)
>> - divider = fref;
>> - else
>> - divider = fref * 2;
>> + divider = fref * 2;
>>
>> - multiplier = 1 << config->frac_bits;
>> + multiplier = 1 << FRAC_BITS;
>> dec_multiple = div_u64(pll_freq * multiplier, divider);
>> div_u64_rem(dec_multiple, multiplier, &frac);
>>
>> dec = div_u64(dec_multiple, multiplier);
>>
>> if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
>> - regs->pll_clock_inverters = 0x28;
>> + config->pll_clock_inverters = 0x28;
>> else if (pll_freq <= 1000000000ULL)
>> - regs->pll_clock_inverters = 0xa0;
>> + config->pll_clock_inverters = 0xa0;
>> else if (pll_freq <= 2500000000ULL)
>> - regs->pll_clock_inverters = 0x20;
>> + config->pll_clock_inverters = 0x20;
>> else if (pll_freq <= 3020000000ULL)
>> - regs->pll_clock_inverters = 0x00;
>> + config->pll_clock_inverters = 0x00;
>> else
>> - regs->pll_clock_inverters = 0x40;
>> + config->pll_clock_inverters = 0x40;
>>
>> - regs->pll_lockdet_rate = config->lock_timer;
>> - regs->decimal_div_start = dec;
>> - regs->frac_div_start_low = (frac & 0xff);
>> - regs->frac_div_start_mid = (frac & 0xff00) >> 8;
>> - regs->frac_div_start_high = (frac & 0x30000) >> 16;
>> + config->decimal_div_start = dec;
>> + config->frac_div_start = frac;
>> }
>>
>> #define SSC_CENTER BIT(0)
>> #define SSC_EN BIT(1)
>>
>> -static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct
>> dsi_pll_config *config)
>> {
>> - struct dsi_pll_config *config = &pll->pll_configuration;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>> u32 ssc_per;
>> u32 ssc_mod;
>> u64 ssc_step_size;
>> @@ -193,58 +147,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm
>> *pll)
>> return;
>> }
>>
>> - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) /
>> 2 - 1;
>> + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) /
>> 2 - 1;
>> ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
>> ssc_per -= ssc_mod;
>>
>> - frac = regs->frac_div_start_low |
>> - (regs->frac_div_start_mid << 8) |
>> - (regs->frac_div_start_high << 16);
>> - ssc_step_size = regs->decimal_div_start;
>> - ssc_step_size *= (1 << config->frac_bits);
>> + frac = config->frac_div_start;
>> + ssc_step_size = config->decimal_div_start;
>> + ssc_step_size *= (1 << FRAC_BITS);
>> ssc_step_size += frac;
>> ssc_step_size *= config->ssc_offset;
>> ssc_step_size *= (config->ssc_adj_per + 1);
>> ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
>> ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
>>
>> - regs->ssc_div_per_low = ssc_per & 0xFF;
>> - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
>> - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
>> - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
>> - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
>> - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
>> -
>> - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
>> + config->ssc_div_per = ssc_per;
>> + config->ssc_stepsize = ssc_step_size;
>>
>> pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
>> - regs->decimal_div_start, frac, config->frac_bits);
>> + config->decimal_div_start, frac, FRAC_BITS);
>> pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
>> ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
>> }
>>
>> -static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct
>> dsi_pll_config *config)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> - struct dsi_pll_regs *regs = &pll->reg_setup;
>>
>> - if (pll->pll_configuration.enable_ssc) {
>> + if (config->enable_ssc) {
>> pr_debug("SSC is enabled\n");
>>
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
>> - regs->ssc_stepsize_low);
>> + config->ssc_stepsize & 0xff);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
>> - regs->ssc_stepsize_high);
>> + config->ssc_stepsize >> 8);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
>> - regs->ssc_div_per_low);
>> + config->ssc_div_per & 0xff);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
>> - regs->ssc_div_per_high);
>> + config->ssc_div_per >> 8);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
>> - regs->ssc_adjper_low);
>> + config->ssc_adj_per & 0xff);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
>> - regs->ssc_adjper_high);
>> + config->ssc_adj_per >> 8);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
>> - SSC_EN | regs->ssc_control);
>> + SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
>> }
>> }
>>
>> @@ -296,44 +241,46 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_7nm *pll)
>> }
>> }
>>
>> -static void dsi_pll_commit(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct
>> dsi_pll_config *config)
>> {
>> void __iomem *base = pll->phy->pll_base;
>> - struct dsi_pll_regs *reg = &pll->reg_setup;
>>
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
>> reg->decimal_div_start);
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
>> reg->frac_div_start_low);
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
>> reg->frac_div_start_mid);
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
>> reg->frac_div_start_high);
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1,
>> reg->pll_lockdet_rate);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
>> config->decimal_div_start);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
>> + config->frac_div_start & 0xff);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
>> + (config->frac_div_start & 0xff00) >> 8);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
>> + (config->frac_div_start & 0x30000) >> 16);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO:
>> 0x00 for CPHY */
>> - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
>> reg->pll_clock_inverters);
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
>> config->pll_clock_inverters);
>> }
>>
>> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long
>> rate,
>> unsigned long parent_rate)
>> {
>> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>> + struct dsi_pll_config config;
>>
>> DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
>> parent_rate);
>>
>> pll_7nm->vco_current_rate = rate;
>> - pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
>>
>> - dsi_pll_setup_config(pll_7nm);
>> + dsi_pll_setup_config(&config);
>>
>> - dsi_pll_calc_dec_frac(pll_7nm);
>> + dsi_pll_calc_dec_frac(pll_7nm, &config);
>>
>> - dsi_pll_calc_ssc(pll_7nm);
>> + dsi_pll_calc_ssc(pll_7nm, &config);
>>
>> - dsi_pll_commit(pll_7nm);
>> + dsi_pll_commit(pll_7nm, &config);
>>
>> dsi_pll_config_hzindep_reg(pll_7nm);
>>
>> - dsi_pll_ssc_commit(pll_7nm);
>> + dsi_pll_ssc_commit(pll_7nm, &config);
>>
>> /* flush, ensure all register writes are done*/
>> wmb();
>> @@ -486,9 +433,8 @@ static unsigned long
>> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
>> - struct dsi_pll_config *config = &pll_7nm->pll_configuration;
>> void __iomem *base = pll_7nm->phy->pll_base;
>> - u64 ref_clk = pll_7nm->vco_ref_clk_rate;
>> + u64 ref_clk = VCO_REF_CLK_RATE;
>> u64 vco_rate = 0x0;
>> u64 multiplier;
>> u32 frac;
>> @@ -508,7 +454,7 @@ static unsigned long
>> dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
>> * TODO:
>> * 1. Assumes prescaler is disabled
>> */
>> - multiplier = 1 << config->frac_bits;
>> + multiplier = 1 << FRAC_BITS;
>> pll_freq = dec * (ref_clk * 2);
>> tmp64 = (ref_clk * 2 * frac);
>> pll_freq += div_u64(tmp64, multiplier);
>> @@ -590,7 +536,7 @@ static int dsi_7nm_restore_state(struct
>> msm_dsi_phy *phy)
>> val |= cached->pll_mux;
>> dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
>>
>> - ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
>> pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
>> + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
>> pll_7nm->vco_current_rate, VCO_REF_CLK_RATE);
>> if (ret) {
>> DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
>> "restore vco rate failed. ret=%d\n", ret);
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (21 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 3:34 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov
2021-03-30 1:31 ` [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Stephen Boyd
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17 -----------------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 --------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 13 +++++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 +++++++----
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 13 +++++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 --
8 files changed, 21 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 74cc11c84d71..56f5134e3933 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
return 0;
}
-void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
- u32 bit_mask)
-{
- int phy_id = phy->id;
- u32 val;
-
- if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
- return;
-
- val = dsi_phy_read(phy->base + reg);
-
- if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
- dsi_phy_write(phy->base + reg, val | bit_mask);
- else
- dsi_phy_write(phy->base + reg, val & (~bit_mask));
-}
-
static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
{
struct regulator_bulk_data *s = phy->supplies;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 8e828c5ca8f4..3b207cf9f6b4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg {
unsigned long min_pll_rate;
unsigned long max_pll_rate;
- /*
- * Each cell {phy_id, pll_id} of the truth table indicates
- * if the source PLL selection bit should be set for each PHY.
- * Fill default H/W values in illegal cells, eg. cell {0, 1}.
- */
- bool src_pll_truthtable[DSI_MAX][DSI_MAX];
const resource_size_t io_start[DSI_MAX];
const int num_dsi_phy;
const int quirks;
@@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
-void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
- u32 bit_mask);
#endif /* __DSI_PHY_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 1fbb54f4df98..04535ccd11ef 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -919,7 +919,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
@@ -941,7 +940,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index d08ad0c632b4..7a87bed71e36 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
int ret;
void __iomem *base = phy->base;
void __iomem *lane_base = phy->lane_base;
+ u32 glbl_test_ctrl;
if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
DRM_DEV_ERROR(&phy->pdev->dev,
@@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
udelay(100);
dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
- msm_dsi_phy_set_src_pll(phy, src_pll_id,
- REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
- DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
-
+ glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+ if (phy->id == DSI_1 && src_pll_id == DSI_0)
+ glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
ret = dsi_14nm_set_usecase(phy);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
@@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
@@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index 5e73f811d645..f5b88c85a8fc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
int i;
void __iomem *base = phy->base;
u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
+ u32 val;
DBG("");
@@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
- msm_dsi_phy_set_src_pll(phy, src_pll_id,
- REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
- DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
+ val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
+ if (src_pll_id == DSI_1)
+ val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
for (i = 0; i < 4; i++) {
dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
@@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
- .src_pll_truthtable = { {false, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
.num = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 0bcea3f3eca3..9f83ab90d093 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_dphy_timing *timing = &phy->timing;
int i;
void __iomem *base = phy->base;
+ u32 val;
DBG("");
@@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
- msm_dsi_phy_set_src_pll(phy, src_pll_id,
- REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
- DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
+ val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
+ if (phy->id == DSI_1 && src_pll_id == DSI_0)
+ val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
return 0;
}
@@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
- .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
.num = 1,
@@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
- .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
.num = 1,
@@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
- .src_pll_truthtable = { {true, true}, {true, true} },
.has_phy_regulator = true,
.reg_cfg = {
.num = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 9ddd0adccce3..d2bfe43c9ef1 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
- .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = {
.num = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index ce6ae2fba993..619998506b78 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -955,7 +955,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
}
const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
@@ -978,7 +977,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
};
const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
- .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = {
.num = 1,
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll
2021-03-27 11:03 ` [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov
@ 2021-03-30 3:34 ` abhinavk
2021-03-30 13:42 ` Dmitry Baryshkov
0 siblings, 1 reply; 50+ messages in thread
From: abhinavk @ 2021-03-30 3:34 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> The src_truthtable config is not used for some of phys, which use other
> means of configuring the master/slave usecases. Inline this function
> with the goal of removing src_pll_id argument in the next commit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17 -----------------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 --------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 --
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 13 +++++++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 +++++++----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 13 +++++++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 --
> 8 files changed, 21 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 74cc11c84d71..56f5134e3933 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct
> msm_dsi_dphy_timing *timing,
> return 0;
> }
>
> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
> reg,
> - u32 bit_mask)
> -{
> - int phy_id = phy->id;
> - u32 val;
> -
> - if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
> - return;
> -
> - val = dsi_phy_read(phy->base + reg);
> -
> - if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
> - dsi_phy_write(phy->base + reg, val | bit_mask);
> - else
> - dsi_phy_write(phy->base + reg, val & (~bit_mask));
> -}
> -
> static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
> {
> struct regulator_bulk_data *s = phy->supplies;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 8e828c5ca8f4..3b207cf9f6b4 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg {
> unsigned long min_pll_rate;
> unsigned long max_pll_rate;
>
> - /*
> - * Each cell {phy_id, pll_id} of the truth table indicates
> - * if the source PLL selection bit should be set for each PHY.
> - * Fill default H/W values in illegal cells, eg. cell {0, 1}.
> - */
> - bool src_pll_truthtable[DSI_MAX][DSI_MAX];
> const resource_size_t io_start[DSI_MAX];
> const int num_dsi_phy;
> const int quirks;
> @@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct
> msm_dsi_dphy_timing *timing,
> struct msm_dsi_phy_clk_request *clk_req);
> int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
> struct msm_dsi_phy_clk_request *clk_req);
> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
> reg,
> - u32 bit_mask);
>
> #endif /* __DSI_PHY_H__ */
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 1fbb54f4df98..04535ccd11ef 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -919,7 +919,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy
> *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
> @@ -941,7 +940,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index d08ad0c632b4..7a87bed71e36 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> int ret;
> void __iomem *base = phy->base;
> void __iomem *lane_base = phy->lane_base;
> + u32 glbl_test_ctrl;
>
> if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
> DRM_DEV_ERROR(&phy->pdev->dev,
> @@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct
> msm_dsi_phy *phy, int src_pll_id,
> udelay(100);
> dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
>
> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
> - REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
> - DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
> -
> + glbl_test_ctrl = dsi_phy_read(base +
> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
> + glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + else
> + glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
> glbl_test_ctrl);
> ret = dsi_14nm_set_usecase(phy);
> if (ret) {
> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
> @@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct
> msm_dsi_phy *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
> @@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =
> {
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> index 5e73f811d645..f5b88c85a8fc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> @@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> int i;
> void __iomem *base = phy->base;
> u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
> + u32 val;
>
> DBG("");
>
> @@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
>
> dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
>
> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
> - REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
> - DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
> + val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
> + if (src_pll_id == DSI_1)
> + val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + else
> + val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
>
> for (i = 0; i < 4; i++) {
> dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
> @@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy
> *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
> - .src_pll_truthtable = { {false, true}, {false, true} },
> .has_phy_regulator = true,
> .reg_cfg = {
> .num = 2,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 0bcea3f3eca3..9f83ab90d093 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> struct msm_dsi_dphy_timing *timing = &phy->timing;
> int i;
> void __iomem *base = phy->base;
> + u32 val;
>
> DBG("");
>
> @@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
>
> dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
>
> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
> - REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
> - DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
> + val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + else
> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
>
> return 0;
> }
> @@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy
> *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
> - .src_pll_truthtable = { {true, true}, {false, true} },
> .has_phy_regulator = true,
> .reg_cfg = {
> .num = 1,
> @@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
> = {
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
> - .src_pll_truthtable = { {true, true}, {false, true} },
> .has_phy_regulator = true,
> .reg_cfg = {
> .num = 1,
> @@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg
> dsi_phy_28nm_hpm_famb_cfgs = {
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
> - .src_pll_truthtable = { {true, true}, {true, true} },
> .has_phy_regulator = true,
> .reg_cfg = {
> .num = 1,
The src_pll_truthtable for dsi_phy_28nm_lp_cfgs has all entries as true,
while the other
28nm_***_cfgs dont. So wouldnt this below logic end up breaking
dsi_phy_28nm_lp_cfgs?
> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + else
> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
If so, I think we can leave it in cfg itself since the 28nm phy driver
is common and is managed
using different config to differentiate the hpm, lp and hpn_famb
variants.
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 9ddd0adccce3..d2bfe43c9ef1 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy
> *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
> - .src_pll_truthtable = { {true, true}, {false, true} },
> .has_phy_regulator = true,
> .reg_cfg = {
> .num = 1,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index ce6ae2fba993..619998506b78 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -955,7 +955,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy
> *phy)
> }
>
> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
> @@ -978,7 +977,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
> - .src_pll_truthtable = { {false, false}, {true, false} },
> .has_phy_lane = true,
> .reg_cfg = {
> .num = 1,
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll
2021-03-30 3:34 ` [Freedreno] " abhinavk
@ 2021-03-30 13:42 ` Dmitry Baryshkov
2021-03-30 17:44 ` abhinavk
0 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-30 13:42 UTC (permalink / raw)
To: abhinavk
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 30/03/2021 06:34, abhinavk@codeaurora.org wrote:
> On 2021-03-27 04:03, Dmitry Baryshkov wrote:
>> The src_truthtable config is not used for some of phys, which use other
>> means of configuring the master/slave usecases. Inline this function
>> with the goal of removing src_pll_id argument in the next commit.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17 -----------------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 --------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 --
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 13 +++++++------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 +++++++----
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 13 +++++++------
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 -
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 --
>> 8 files changed, 21 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> index 74cc11c84d71..56f5134e3933 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> @@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct
>> msm_dsi_dphy_timing *timing,
>> return 0;
>> }
>>
>> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
>> reg,
>> - u32 bit_mask)
>> -{
>> - int phy_id = phy->id;
>> - u32 val;
>> -
>> - if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
>> - return;
>> -
>> - val = dsi_phy_read(phy->base + reg);
>> -
>> - if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
>> - dsi_phy_write(phy->base + reg, val | bit_mask);
>> - else
>> - dsi_phy_write(phy->base + reg, val & (~bit_mask));
>> -}
>> -
>> static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
>> {
>> struct regulator_bulk_data *s = phy->supplies;
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index 8e828c5ca8f4..3b207cf9f6b4 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg {
>> unsigned long min_pll_rate;
>> unsigned long max_pll_rate;
>>
>> - /*
>> - * Each cell {phy_id, pll_id} of the truth table indicates
>> - * if the source PLL selection bit should be set for each PHY.
>> - * Fill default H/W values in illegal cells, eg. cell {0, 1}.
>> - */
>> - bool src_pll_truthtable[DSI_MAX][DSI_MAX];
>> const resource_size_t io_start[DSI_MAX];
>> const int num_dsi_phy;
>> const int quirks;
>> @@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct
>> msm_dsi_dphy_timing *timing,
>> struct msm_dsi_phy_clk_request *clk_req);
>> int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
>> struct msm_dsi_phy_clk_request *clk_req);
>> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32
>> reg,
>> - u32 bit_mask);
>>
>> #endif /* __DSI_PHY_H__ */
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> index 1fbb54f4df98..04535ccd11ef 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>> @@ -919,7 +919,6 @@ static void dsi_10nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
>> @@ -941,7 +940,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
>> };
>>
>> const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> index d08ad0c632b4..7a87bed71e36 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> @@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>> int ret;
>> void __iomem *base = phy->base;
>> void __iomem *lane_base = phy->lane_base;
>> + u32 glbl_test_ctrl;
>>
>> if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
>> DRM_DEV_ERROR(&phy->pdev->dev,
>> @@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct
>> msm_dsi_phy *phy, int src_pll_id,
>> udelay(100);
>> dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
>>
>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>> - REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
>> - DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>> -
>> + glbl_test_ctrl = dsi_phy_read(base +
>> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>> + glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + else
>> + glbl_test_ctrl &=
>> ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
>> glbl_test_ctrl);
>> ret = dsi_14nm_set_usecase(phy);
>> if (ret) {
>> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed,
>> %d\n",
>> @@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
>> @@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
>> };
>>
>> const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>> index 5e73f811d645..f5b88c85a8fc 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>> @@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>> int i;
>> void __iomem *base = phy->base;
>> u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
>> + u32 val;
>>
>> DBG("");
>>
>> @@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>>
>> dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
>>
>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>> - REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
>> - DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>> + val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
>> + if (src_pll_id == DSI_1)
>> + val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + else
>> + val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
>>
>> for (i = 0; i < 4; i++) {
>> dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
>> @@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
>> - .src_pll_truthtable = { {false, true}, {false, true} },
>> .has_phy_regulator = true,
>> .reg_cfg = {
>> .num = 2,
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> index 0bcea3f3eca3..9f83ab90d093 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>> @@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>> struct msm_dsi_dphy_timing *timing = &phy->timing;
>> int i;
>> void __iomem *base = phy->base;
>> + u32 val;
>>
>> DBG("");
>>
>> @@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
>> *phy, int src_pll_id,
>>
>> dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
>>
>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>> - REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
>> - DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>> + val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + else
>> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
>>
>> return 0;
>> }
>> @@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
>> - .src_pll_truthtable = { {true, true}, {false, true} },
>> .has_phy_regulator = true,
>> .reg_cfg = {
>> .num = 1,
>> @@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs
>> = {
>> };
>>
>> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
>> - .src_pll_truthtable = { {true, true}, {false, true} },
>> .has_phy_regulator = true,
>> .reg_cfg = {
>> .num = 1,
>> @@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg
>> dsi_phy_28nm_hpm_famb_cfgs = {
>> };
>>
>> const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
>> - .src_pll_truthtable = { {true, true}, {true, true} },
>> .has_phy_regulator = true,
>> .reg_cfg = {
>> .num = 1,
>
> The src_pll_truthtable for dsi_phy_28nm_lp_cfgs has all entries as true,
> while the other
> 28nm_***_cfgs dont. So wouldnt this below logic end up breaking
> dsi_phy_28nm_lp_cfgs?
28nm_lp has just one PHY, so second half of the table does not make
sense at all.
And it is exactly one of the reasons to get rid of it: it might be
misleading.
Also consider the [0][1] table entry, which is also declared, but it is
not usable.
>
>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + else
>> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
>
> If so, I think we can leave it in cfg itself since the 28nm phy driver
> is common and is managed
> using different config to differentiate the hpm, lp and hpn_famb variants.
I'd prefer to drop it from all the drivers, to have fewer 'declared but
unused' cases/data.
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> index 9ddd0adccce3..d2bfe43c9ef1 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>> @@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
>> - .src_pll_truthtable = { {true, true}, {false, true} },
>> .has_phy_regulator = true,
>> .reg_cfg = {
>> .num = 1,
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index ce6ae2fba993..619998506b78 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -955,7 +955,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy
>> *phy)
>> }
>>
>> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
>> @@ -978,7 +977,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>> };
>>
>> const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
>> - .src_pll_truthtable = { {false, false}, {true, false} },
>> .has_phy_lane = true,
>> .reg_cfg = {
>> .num = 1,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll
2021-03-30 13:42 ` Dmitry Baryshkov
@ 2021-03-30 17:44 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 17:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-30 06:42, Dmitry Baryshkov wrote:
> On 30/03/2021 06:34, abhinavk@codeaurora.org wrote:
>> On 2021-03-27 04:03, Dmitry Baryshkov wrote:
>>> The src_truthtable config is not used for some of phys, which use
>>> other
>>> means of configuring the master/slave usecases. Inline this function
>>> with the goal of removing src_pll_id argument in the next commit.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17
>>> -----------------
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 --------
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 --
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 13 +++++++------
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 +++++++----
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 13 +++++++------
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 -
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 --
>>> 8 files changed, 21 insertions(+), 46 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> index 74cc11c84d71..56f5134e3933 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> @@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct
>>> msm_dsi_dphy_timing *timing,
>>> return 0;
>>> }
>>>
>>> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id,
>>> u32 reg,
>>> - u32 bit_mask)
>>> -{
>>> - int phy_id = phy->id;
>>> - u32 val;
>>> -
>>> - if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
>>> - return;
>>> -
>>> - val = dsi_phy_read(phy->base + reg);
>>> -
>>> - if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
>>> - dsi_phy_write(phy->base + reg, val | bit_mask);
>>> - else
>>> - dsi_phy_write(phy->base + reg, val & (~bit_mask));
>>> -}
>>> -
>>> static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
>>> {
>>> struct regulator_bulk_data *s = phy->supplies;
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> index 8e828c5ca8f4..3b207cf9f6b4 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> @@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg {
>>> unsigned long min_pll_rate;
>>> unsigned long max_pll_rate;
>>>
>>> - /*
>>> - * Each cell {phy_id, pll_id} of the truth table indicates
>>> - * if the source PLL selection bit should be set for each PHY.
>>> - * Fill default H/W values in illegal cells, eg. cell {0, 1}.
>>> - */
>>> - bool src_pll_truthtable[DSI_MAX][DSI_MAX];
>>> const resource_size_t io_start[DSI_MAX];
>>> const int num_dsi_phy;
>>> const int quirks;
>>> @@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct
>>> msm_dsi_dphy_timing *timing,
>>> struct msm_dsi_phy_clk_request *clk_req);
>>> int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
>>> struct msm_dsi_phy_clk_request *clk_req);
>>> -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id,
>>> u32 reg,
>>> - u32 bit_mask);
>>>
>>> #endif /* __DSI_PHY_H__ */
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>>> index 1fbb54f4df98..04535ccd11ef 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
>>> @@ -919,7 +919,6 @@ static void dsi_10nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> @@ -941,7 +940,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =
>>> {
>>> };
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>>> index d08ad0c632b4..7a87bed71e36 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>>> @@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy
>>> *phy, int src_pll_id,
>>> int ret;
>>> void __iomem *base = phy->base;
>>> void __iomem *lane_base = phy->lane_base;
>>> + u32 glbl_test_ctrl;
>>>
>>> if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
>>> DRM_DEV_ERROR(&phy->pdev->dev,
>>> @@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct
>>> msm_dsi_phy *phy, int src_pll_id,
>>> udelay(100);
>>> dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
>>>
>>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>>> - REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
>>> - DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>>> -
>>> + glbl_test_ctrl = dsi_phy_read(base +
>>> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
>>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>>> + glbl_test_ctrl |=
>>> DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + else
>>> + glbl_test_ctrl &=
>>> ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
>>> glbl_test_ctrl);
>>> ret = dsi_14nm_set_usecase(phy);
>>> if (ret) {
>>> DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed,
>>> %d\n",
>>> @@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> @@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs
>>> = {
>>> };
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>>> index 5e73f811d645..f5b88c85a8fc 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
>>> @@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
>>> *phy, int src_pll_id,
>>> int i;
>>> void __iomem *base = phy->base;
>>> u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
>>> + u32 val;
>>>
>>> DBG("");
>>>
>>> @@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
>>> *phy, int src_pll_id,
>>>
>>> dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
>>>
>>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>>> - REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
>>> - DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>>> + val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
>>> + if (src_pll_id == DSI_1)
>>> + val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + else
>>> + val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
>>>
>>> for (i = 0; i < 4; i++) {
>>> dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
>>> @@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
>>> - .src_pll_truthtable = { {false, true}, {false, true} },
>>> .has_phy_regulator = true,
>>> .reg_cfg = {
>>> .num = 2,
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>>> index 0bcea3f3eca3..9f83ab90d093 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
>>> @@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
>>> *phy, int src_pll_id,
>>> struct msm_dsi_dphy_timing *timing = &phy->timing;
>>> int i;
>>> void __iomem *base = phy->base;
>>> + u32 val;
>>>
>>> DBG("");
>>>
>>> @@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct
>>> msm_dsi_phy
>>> *phy, int src_pll_id,
>>>
>>> dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
>>>
>>> - msm_dsi_phy_set_src_pll(phy, src_pll_id,
>>> - REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
>>> - DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
>>> + val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
>>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>>> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + else
>>> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
>>>
>>> return 0;
>>> }
>>> @@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
>>> - .src_pll_truthtable = { {true, true}, {false, true} },
>>> .has_phy_regulator = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> @@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg
>>> dsi_phy_28nm_hpm_cfgs = {
>>> };
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
>>> - .src_pll_truthtable = { {true, true}, {false, true} },
>>> .has_phy_regulator = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> @@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg
>>> dsi_phy_28nm_hpm_famb_cfgs = {
>>> };
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
>>> - .src_pll_truthtable = { {true, true}, {true, true} },
>>> .has_phy_regulator = true,
>>> .reg_cfg = {
>>> .num = 1,
>>
>> The src_pll_truthtable for dsi_phy_28nm_lp_cfgs has all entries as
>> true, while the other
>> 28nm_***_cfgs dont. So wouldnt this below logic end up breaking
>> dsi_phy_28nm_lp_cfgs?
>
> 28nm_lp has just one PHY, so second half of the table does not make
> sense at all.
>
> And it is exactly one of the reasons to get rid of it: it might be
> misleading.
>
> Also consider the [0][1] table entry, which is also declared, but it
> is not usable.
Thanks for the clarification. You are right. There is only one PHY for
28nm so the
second row and the second column seem unnecessary. Hence,
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>
>>
>>> + if (phy->id == DSI_1 && src_pll_id == DSI_0)
>>> + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + else
>>> + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
>>> + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
>>
>> If so, I think we can leave it in cfg itself since the 28nm phy driver
>> is common and is managed
>> using different config to differentiate the hpm, lp and hpn_famb
>> variants.
>
> I'd prefer to drop it from all the drivers, to have fewer 'declared
> but unused' cases/data.
>
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>>> index 9ddd0adccce3..d2bfe43c9ef1 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
>>> @@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
>>> - .src_pll_truthtable = { {true, true}, {false, true} },
>>> .has_phy_regulator = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> index ce6ae2fba993..619998506b78 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> @@ -955,7 +955,6 @@ static void dsi_7nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> }
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
>>> @@ -978,7 +977,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>>> };
>>>
>>> const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
>>> - .src_pll_truthtable = { {false, false}, {true, false} },
>>> .has_phy_lane = true,
>>> .reg_cfg = {
>>> .num = 1,
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (22 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov
@ 2021-03-27 11:03 ` Dmitry Baryshkov
2021-03-30 19:29 ` [Freedreno] " abhinavk
2021-03-30 1:31 ` [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Stephen Boyd
24 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2021-03-27 11:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Jonathan Marek, Michael Turquette
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
dri-devel, freedreno, linux-clk
Phy driver already knows the source PLL id basing on the set usecase and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a slave
mode, so PLL 0 is always a clocksource for DSI 0 and it is always a
clocksource for DSI 1 too unless DSI 1 is used in the standalone mode.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 11 +++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 4 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 4 ++--
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
10 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 53feea9d30c0..c8ef63bdc042 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -162,7 +162,7 @@ struct msm_dsi_phy_clk_request {
void msm_dsi_phy_driver_register(void);
void msm_dsi_phy_driver_unregister(void);
-int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 0c47c5fb1ab3..76735cde57c6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -114,7 +114,7 @@ static int dsi_mgr_setup_components(int id)
return ret;
}
-static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
+static int enable_phy(struct msm_dsi *msm_dsi,
struct msm_dsi_phy_shared_timings *shared_timings)
{
struct msm_dsi_phy_clk_request clk_req;
@@ -123,7 +123,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);
- ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
+ ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req);
msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
return ret;
@@ -136,7 +136,6 @@ dsi_mgr_phy_enable(int id,
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
- int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
int ret;
/* In case of dual DSI, some registers in PHY1 have been programmed
@@ -149,11 +148,11 @@ dsi_mgr_phy_enable(int id,
msm_dsi_host_reset_phy(mdsi->host);
msm_dsi_host_reset_phy(sdsi->host);
- ret = enable_phy(mdsi, src_pll_id,
+ ret = enable_phy(mdsi,
&shared_timings[DSI_CLOCK_MASTER]);
if (ret)
return ret;
- ret = enable_phy(sdsi, src_pll_id,
+ ret = enable_phy(sdsi,
&shared_timings[DSI_CLOCK_SLAVE]);
if (ret) {
msm_dsi_phy_disable(mdsi->phy);
@@ -162,7 +161,7 @@ dsi_mgr_phy_enable(int id,
}
} else {
msm_dsi_host_reset_phy(msm_dsi->host);
- ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]);
+ ret = enable_phy(msm_dsi, &shared_timings[id]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 56f5134e3933..2a421fd77f2f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -753,7 +753,7 @@ void __exit msm_dsi_phy_driver_unregister(void)
platform_driver_unregister(&dsi_phy_platform_driver);
}
-int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct device *dev = &phy->pdev->dev;
@@ -776,7 +776,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
goto reg_en_fail;
}
- ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
+ ret = phy->cfg->ops.enable(phy, clk_req);
if (ret) {
DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
goto phy_en_fail;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 3b207cf9f6b4..74fffcae0f10 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -19,7 +19,7 @@
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
- int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
+ int (*enable)(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req);
void (*disable)(struct msm_dsi_phy *phy);
void (*save_state)(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 04535ccd11ef..bea68154ef87 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -786,7 +786,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
}
}
-static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
int ret;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 7a87bed71e36..c9afa6c461ee 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -938,7 +938,7 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
}
-static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_dphy_timing *timing = &phy->timing;
@@ -996,7 +996,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
- if (phy->id == DSI_1 && src_pll_id == DSI_0)
+ if (phy->usecase == MSM_DSI_PHY_SLAVE)
glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
else
glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index f5b88c85a8fc..e96d789aea18 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -63,7 +63,7 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
}
-static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_dphy_timing *timing = &phy->timing;
@@ -85,7 +85,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
- if (src_pll_id == DSI_1)
+ if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)
val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
else
val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 9f83ab90d093..0e8f74ebb895 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -698,7 +698,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
dsi_28nm_phy_regulator_enable_dcdc(phy);
}
-static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_dphy_timing *timing = &phy->timing;
@@ -745,7 +745,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
- if (phy->id == DSI_1 && src_pll_id == DSI_0)
+ if (phy->usecase == MSM_DSI_PHY_SLAVE)
val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
else
val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index d2bfe43c9ef1..104446450f7c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -585,7 +585,7 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy)
dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88);
}
-static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_dphy_timing *timing = &phy->timing;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 619998506b78..badc76a8d425 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -799,7 +799,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
}
}
-static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
+static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
int ret;
--
2.30.2
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [Freedreno] [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call
2021-03-27 11:03 ` [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov
@ 2021-03-30 19:29 ` abhinavk
0 siblings, 0 replies; 50+ messages in thread
From: abhinavk @ 2021-03-30 19:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Jonathan Marek, Michael Turquette,
Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
Daniel Vetter, freedreno, linux-clk
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
> Phy driver already knows the source PLL id basing on the set usecase
> and
> the current PLL id. Stop passing it to the phy_enable call. As a
> reminder, dsi manager will always use DSI 0 as a clock master in a
> slave
> mode, so PLL 0 is always a clocksource for DSI 0 and it is always a
> clocksource for DSI 1 too unless DSI 1 is used in the standalone mode.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 11 +++++------
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 4 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 4 ++--
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
> 10 files changed, 18 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
> b/drivers/gpu/drm/msm/dsi/dsi.h
> index 53feea9d30c0..c8ef63bdc042 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -162,7 +162,7 @@ struct msm_dsi_phy_clk_request {
>
> void msm_dsi_phy_driver_register(void);
> void msm_dsi_phy_driver_unregister(void);
> -int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
> +int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req);
> void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
> void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 0c47c5fb1ab3..76735cde57c6 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -114,7 +114,7 @@ static int dsi_mgr_setup_components(int id)
> return ret;
> }
>
> -static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
> +static int enable_phy(struct msm_dsi *msm_dsi,
> struct msm_dsi_phy_shared_timings *shared_timings)
> {
> struct msm_dsi_phy_clk_request clk_req;
> @@ -123,7 +123,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, int
> src_pll_id,
>
> msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);
>
> - ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
> + ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req);
> msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
>
> return ret;
> @@ -136,7 +136,6 @@ dsi_mgr_phy_enable(int id,
> struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
> struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
> struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
> - int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
> int ret;
>
> /* In case of dual DSI, some registers in PHY1 have been programmed
> @@ -149,11 +148,11 @@ dsi_mgr_phy_enable(int id,
> msm_dsi_host_reset_phy(mdsi->host);
> msm_dsi_host_reset_phy(sdsi->host);
>
> - ret = enable_phy(mdsi, src_pll_id,
> + ret = enable_phy(mdsi,
> &shared_timings[DSI_CLOCK_MASTER]);
> if (ret)
> return ret;
> - ret = enable_phy(sdsi, src_pll_id,
> + ret = enable_phy(sdsi,
> &shared_timings[DSI_CLOCK_SLAVE]);
> if (ret) {
> msm_dsi_phy_disable(mdsi->phy);
> @@ -162,7 +161,7 @@ dsi_mgr_phy_enable(int id,
> }
> } else {
> msm_dsi_host_reset_phy(msm_dsi->host);
> - ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]);
> + ret = enable_phy(msm_dsi, &shared_timings[id]);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 56f5134e3933..2a421fd77f2f 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -753,7 +753,7 @@ void __exit msm_dsi_phy_driver_unregister(void)
> platform_driver_unregister(&dsi_phy_platform_driver);
> }
>
> -int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
> +int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> struct device *dev = &phy->pdev->dev;
> @@ -776,7 +776,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
> int src_pll_id,
> goto reg_en_fail;
> }
>
> - ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
> + ret = phy->cfg->ops.enable(phy, clk_req);
> if (ret) {
> DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
> goto phy_en_fail;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 3b207cf9f6b4..74fffcae0f10 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -19,7 +19,7 @@
>
> struct msm_dsi_phy_ops {
> int (*pll_init)(struct msm_dsi_phy *phy);
> - int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
> + int (*enable)(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req);
> void (*disable)(struct msm_dsi_phy *phy);
> void (*save_state)(struct msm_dsi_phy *phy);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index 04535ccd11ef..bea68154ef87 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -786,7 +786,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct
> msm_dsi_phy *phy)
> }
> }
>
> -static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int
> src_pll_id,
> +static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> int ret;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 7a87bed71e36..c9afa6c461ee 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -938,7 +938,7 @@ static void dsi_14nm_dphy_set_timing(struct
> msm_dsi_phy *phy,
> DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
> }
>
> -static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int
> src_pll_id,
> +static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> struct msm_dsi_dphy_timing *timing = &phy->timing;
> @@ -996,7 +996,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
>
> glbl_test_ctrl = dsi_phy_read(base +
> REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
> - if (phy->id == DSI_1 && src_pll_id == DSI_0)
> + if (phy->usecase == MSM_DSI_PHY_SLAVE)
I think it should not make a difference but can we keep the check for
DSI_1? So lets modify this to be:
if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
> glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> else
> glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> index f5b88c85a8fc..e96d789aea18 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
> @@ -63,7 +63,7 @@ static void dsi_20nm_phy_regulator_ctrl(struct
> msm_dsi_phy *phy, bool enable)
> dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
> }
>
> -static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int
> src_pll_id,
> +static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> struct msm_dsi_dphy_timing *timing = &phy->timing;
> @@ -85,7 +85,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
>
> val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
> - if (src_pll_id == DSI_1)
> + if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)
> val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> else
> val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 9f83ab90d093..0e8f74ebb895 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -698,7 +698,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct
> msm_dsi_phy *phy, bool enable)
> dsi_28nm_phy_regulator_enable_dcdc(phy);
> }
>
> -static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int
> src_pll_id,
> +static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> struct msm_dsi_dphy_timing *timing = &phy->timing;
> @@ -745,7 +745,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy
> *phy, int src_pll_id,
> dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
>
> val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
> - if (phy->id == DSI_1 && src_pll_id == DSI_0)
> + if (phy->usecase == MSM_DSI_PHY_SLAVE)
same here
> val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> else
> val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index d2bfe43c9ef1..104446450f7c 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -585,7 +585,7 @@ static void dsi_28nm_phy_lane_config(struct
> msm_dsi_phy *phy)
> dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88);
> }
>
> -static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int
> src_pll_id,
> +static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> struct msm_dsi_dphy_timing *timing = &phy->timing;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 619998506b78..badc76a8d425 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -799,7 +799,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct
> msm_dsi_phy *phy)
> }
> }
>
> -static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
> +static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_clk_request *clk_req)
> {
> int ret;
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
` (23 preceding siblings ...)
2021-03-27 11:03 ` [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov
@ 2021-03-30 1:31 ` Stephen Boyd
24 siblings, 0 replies; 50+ messages in thread
From: Stephen Boyd @ 2021-03-30 1:31 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Jonathan Marek,
Michael Turquette, Rob Clark, Sean Paul
Cc: David Airlie, Daniel Vetter, linux-arm-msm, dri-devel, freedreno,
linux-clk
Quoting Dmitry Baryshkov (2021-03-27 04:02:40)
> Restructure MSM DSI PHY drivers. What started as an attempt to grok the
> overcomplicated PHY drivers, has lead up to the idea of merging PHY and
> PLL code, reducing abstractions, code duplication, dropping dead code,
> etc.
>
> The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016,
> 28nm-lp) and lightly tested on RB3 (sdm845, 10nm).
>
> The patch 'clk: fixed: add devm helper for clk_hw_register_fixed_factor()'
> is already a part of mainline as of 5.12-rc1, but is included here for
> completeness to fix compilation issues (as msm-next is based on 5.11-rc5).
>
> Changes since v2:
> - Drop the 'stop setting clock parents manually' patch for now together
> with the dtsi changes. Unlike the rest of patchset it provides
> functional changes and might require additional discussion.
> The patchset will be resubmitted later.
>
> Changes since v1:
> - Rebase on top of msm/msm-next
> - Reorder patches to follow logical sequence
> - Add sc7180 clocks assignment
> - Drop sm8250 clocks assignment, as respective file is not updated in
> msm/msm-next
>
> Changes since RFC:
> - Reorder patches to move global clock patches in the beginning and
> dtsi patches where they are required.
> - remove msm_dsi_phy_set_src_pll() and guess src_pll_id using PHY usecase.
>
> The following changes since commit 627dc55c273dab308303a5217bd3e767d7083ddb:
>
> drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume (2021-03-22 18:52:34 -0700)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/dmitry.baryshkov/kernel.git dsi-phy-3
I tested this on sc7180 lazor and the display comes up
Tested-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 50+ messages in thread