* [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init
@ 2021-10-14 18:58 Prasad Malisetty
2021-10-15 13:57 ` Bjorn Helgaas
2021-10-21 7:36 ` Manivannan Sadhasivam
0 siblings, 2 replies; 4+ messages in thread
From: Prasad Malisetty @ 2021-10-14 18:58 UTC (permalink / raw)
To: svarbanov, agross, bjorn.andersson, lorenzo.pieralisi,
linux-arm-msm, linux-pci, linux-kernel, vbadigan, kw, bhelgaas,
manivannan.sadhasivam
Cc: Prasad Malisetty
In pcie_init_2_7_0 one of the register writes using incorrect offset
as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
offset value should be 0x1A8 instead 0x178).
Update the correct offset value for SDM845 platform.
fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..5bce152 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+ val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
val |= BIT(31);
- writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+ writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
}
return 0;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init
2021-10-14 18:58 [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init Prasad Malisetty
@ 2021-10-15 13:57 ` Bjorn Helgaas
2021-10-21 7:36 ` Manivannan Sadhasivam
1 sibling, 0 replies; 4+ messages in thread
From: Bjorn Helgaas @ 2021-10-15 13:57 UTC (permalink / raw)
To: Prasad Malisetty
Cc: svarbanov, agross, bjorn.andersson, lorenzo.pieralisi,
linux-arm-msm, linux-pci, linux-kernel, vbadigan, kw, bhelgaas,
manivannan.sadhasivam
This looks specific to SDM845, so the subject line should mention
SDM845, e.g.,
PCI: qcom: Fix SDM845 incorrect register offset
On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote:
> In pcie_init_2_7_0 one of the register writes using incorrect offset
> as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
> offset value should be 0x1A8 instead 0x178).
> Update the correct offset value for SDM845 platform.
Add "()" after function name. Add blank line between paragraphs.
It'd be nice to have a clue about what fails because of the incorrect
register offset. ed8cc3b1fc84 is almost two years old, so I guess
it's not an obvious issue.
> fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")
Capitalize "Fixes:", use 12-char SHA1, remove blank line after. Look
at previous git history and copy the style there.
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
It looks like ed8cc3b1fc84 appeared in v5.6, so this should probably
have a "Cc: stable@vger.kernel.org" tag as well.
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8a7a300..5bce152 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
> val |= BIT(31);
> - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
> }
>
> return 0;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init
2021-10-14 18:58 [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init Prasad Malisetty
2021-10-15 13:57 ` Bjorn Helgaas
@ 2021-10-21 7:36 ` Manivannan Sadhasivam
2021-10-21 15:21 ` Prasad Malisetty
1 sibling, 1 reply; 4+ messages in thread
From: Manivannan Sadhasivam @ 2021-10-21 7:36 UTC (permalink / raw)
To: Prasad Malisetty
Cc: svarbanov, agross, bjorn.andersson, lorenzo.pieralisi,
linux-arm-msm, linux-pci, linux-kernel, vbadigan, kw, bhelgaas
On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote:
> In pcie_init_2_7_0 one of the register writes using incorrect offset
> as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
> offset value should be 0x1A8 instead 0x178).
> Update the correct offset value for SDM845 platform.
>
> fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
After incorporating the reviews from Bjorn H,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8a7a300..5bce152 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
> val |= BIT(31);
> - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
> }
>
> return 0;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init
2021-10-21 7:36 ` Manivannan Sadhasivam
@ 2021-10-21 15:21 ` Prasad Malisetty
0 siblings, 0 replies; 4+ messages in thread
From: Prasad Malisetty @ 2021-10-21 15:21 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: svarbanov, agross, bjorn.andersson, lorenzo.pieralisi,
linux-arm-msm, linux-pci, linux-kernel, vbadigan, kw, bhelgaas
On 2021-10-21 13:06, Manivannan Sadhasivam wrote:
> On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote:
>> In pcie_init_2_7_0 one of the register writes using incorrect offset
>> as per the platform register definitions
>> (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
>> offset value should be 0x1A8 instead 0x178).
>> Update the correct offset value for SDM845 platform.
>>
>> fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")
>>
>> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
>
> After incorporating the reviews from Bjorn H,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Thanks,
> Mani
>
Thanks Mani for the review. I will incorporate the changes as suggested
by Bjorn H in next patch version.
-Prasad
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>> b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 8a7a300..5bce152 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie
>> *pcie)
>> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
>> + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
>> val |= BIT(31);
>> - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
>> + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
>> }
>>
>> return 0;
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-10-21 15:22 UTC | newest]
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2021-10-14 18:58 [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init Prasad Malisetty
2021-10-15 13:57 ` Bjorn Helgaas
2021-10-21 7:36 ` Manivannan Sadhasivam
2021-10-21 15:21 ` Prasad Malisetty
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