* [RFC PATCH 1/4] arm64: dts: qcom: sm8150: add dispcc node
2021-11-10 17:03 [RFC PATCH 0/4] arm64: dts: sm8150: display support for Microsoft Surface Duo Katherine Perez
@ 2021-11-10 17:03 ` Katherine Perez
2021-11-11 21:56 ` Konrad Dybcio
2021-11-10 17:03 ` [RFC PATCH 2/4] arm64: dts: qcom: sm8150: add display nodes Katherine Perez
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Katherine Perez @ 2021-11-10 17:03 UTC (permalink / raw)
To: Bjorn Andersson, Vinod Koul; +Cc: linux-arm-msm
Add the display clock controller node to sm8150.
Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 81b4ff2cc4cd..ee40af469fab 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -3260,6 +3261,30 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8150-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [RFC PATCH 2/4] arm64: dts: qcom: sm8150: add display nodes
2021-11-10 17:03 [RFC PATCH 0/4] arm64: dts: sm8150: display support for Microsoft Surface Duo Katherine Perez
2021-11-10 17:03 ` [RFC PATCH 1/4] arm64: dts: qcom: sm8150: add dispcc node Katherine Perez
@ 2021-11-10 17:03 ` Katherine Perez
2021-11-11 22:00 ` Konrad Dybcio
2021-11-10 17:03 ` [RFC PATCH 3/4] arm64: dts: qcom: sm8150: add DSI " Katherine Perez
2021-11-10 17:03 ` [RFC PATCH 4/4] arm64: dts: qcom: sm8150: display support for Microsoft Surface Duo Katherine Perez
3 siblings, 1 reply; 7+ messages in thread
From: Katherine Perez @ 2021-11-10 17:03 UTC (permalink / raw)
To: Bjorn Andersson, Vinod Koul; +Cc: linux-arm-msm
Add MDSS and MDP nodes to sm8150.
Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 ++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ee40af469fab..38dbc39103ba 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3261,6 +3261,98 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sm8150-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ iommus = <&apps_smmu 0x800 0x420>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: mdp@ae010000 {
+ compatible = "qcom,sm8150-dpu";
+ reg = <0x0ae01000 0x84208>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <460000000>,
+ <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8150-dispcc";
reg = <0 0x0af00000 0 0x10000>;
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [RFC PATCH 2/4] arm64: dts: qcom: sm8150: add display nodes
2021-11-10 17:03 ` [RFC PATCH 2/4] arm64: dts: qcom: sm8150: add display nodes Katherine Perez
@ 2021-11-11 22:00 ` Konrad Dybcio
0 siblings, 0 replies; 7+ messages in thread
From: Konrad Dybcio @ 2021-11-11 22:00 UTC (permalink / raw)
To: Katherine Perez, Bjorn Andersson, Vinod Koul; +Cc: linux-arm-msm
On 10.11.2021 18:03, Katherine Perez wrote:
> Add MDSS and MDP nodes to sm8150.
>
> Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 ++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index ee40af469fab..38dbc39103ba 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3261,6 +3261,98 @@ camnoc_virt: interconnect@ac00000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
>
[...]
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <460000000>,
> + <19200000>;
> +
I'm not sure if assigning F_MAX is a good idea, but it proobably won't hurt, given we have an OPP table?
Besides that,
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread
* [RFC PATCH 3/4] arm64: dts: qcom: sm8150: add DSI display nodes
2021-11-10 17:03 [RFC PATCH 0/4] arm64: dts: sm8150: display support for Microsoft Surface Duo Katherine Perez
2021-11-10 17:03 ` [RFC PATCH 1/4] arm64: dts: qcom: sm8150: add dispcc node Katherine Perez
2021-11-10 17:03 ` [RFC PATCH 2/4] arm64: dts: qcom: sm8150: add display nodes Katherine Perez
@ 2021-11-10 17:03 ` Katherine Perez
2021-11-10 17:03 ` [RFC PATCH 4/4] arm64: dts: qcom: sm8150: display support for Microsoft Surface Duo Katherine Perez
3 siblings, 0 replies; 7+ messages in thread
From: Katherine Perez @ 2021-11-10 17:03 UTC (permalink / raw)
To: Bjorn Andersson, Vinod Koul; +Cc: linux-arm-msm
Add DSI controller and PHY nodes to sm8150.
Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 183 ++++++++++++++++++++++++++-
1 file changed, 179 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 38dbc39103ba..afa612daefa1 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3261,6 +3261,35 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-328580000 {
+ opp-hz = /bits/ 64 <328580000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
mdss: mdss@ae00000 {
compatible = "qcom,sm8150-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@@ -3351,6 +3380,152 @@ opp-460000000 {
};
};
};
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-7nm-8150";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ dsi1: dsi@ae96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8150_CX>;
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: dsi-phy@ae96400 {
+ compatible = "qcom,dsi-phy-7nm-8150";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
};
dispcc: clock-controller@af00000 {
@@ -3359,10 +3534,10 @@ dispcc: clock-controller@af00000 {
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
<0>,
<0>;
clock-names = "bi_tcxo",
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [RFC PATCH 4/4] arm64: dts: qcom: sm8150: display support for Microsoft Surface Duo
2021-11-10 17:03 [RFC PATCH 0/4] arm64: dts: sm8150: display support for Microsoft Surface Duo Katherine Perez
` (2 preceding siblings ...)
2021-11-10 17:03 ` [RFC PATCH 3/4] arm64: dts: qcom: sm8150: add DSI " Katherine Perez
@ 2021-11-10 17:03 ` Katherine Perez
3 siblings, 0 replies; 7+ messages in thread
From: Katherine Perez @ 2021-11-10 17:03 UTC (permalink / raw)
To: Bjorn Andersson, Vinod Koul; +Cc: linux-arm-msm
Add support for display to Microsoft Surface Duo.
Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
---
.../dts/qcom/sm8150-microsoft-surface-duo.dts | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
index 5901c28e6696..721f76b1b30c 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
@@ -270,6 +270,8 @@ vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_hv_refgen0:
+ vdda_mipi_dsi0_1p2:
+ vdda_mipi_dsi1_1p2:
vdda_qlink_hv_ck:
vreg_l3c_1p2: ldo3 {
regulator-min-microvolt = <1200000>;
@@ -359,6 +361,26 @@ vreg_l6f_2p85: ldo6 {
};
};
+&dsi0 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+};
+
+&dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vdda_dsi_0_pll_0p9>;
+};
+
+&dsi1 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi1_1p2>;
+};
+
+&dsi1_phy {
+ status = "okay";
+ vdds-supply = <&vdda_dsi_1_pll_0p9>;
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -430,6 +452,10 @@ &i2c19 {
/* MAX34417 @ 0x1e */
};
+&mdss {
+ status = "okay";
+};
+
&pon {
pwrkey {
status = "okay";
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread