Re: [PATCH V3,4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

Re: [PATCH V3,4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

[CK Hu]

On Fri, 2019-01-25 at 12:02 +0800, Wangyan Wang wrote:
> From: chunhui dai <chunhui.dai@mediatek.com>
> 
> Due to a clerical error,there is one zero less for 12800000.
> Fix it for 128000000.
> 

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> index 43bc058d5528..88dd9e812ca0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>  
>  	if (rate <= 64000000)
>  		pos_div = 3;
> -	else if (rate <= 12800000)
> -		pos_div = 1;
> +	else if (rate <= 128000000)
> +		pos_div = 2;
>  	else
>  		pos_div = 1;
>  

Re: [PATCH V3,0/8] make mt7623 clock of HDMI stable

[CK Hu]

Hi, Wangyan:

How do you prove that this series would make mt7623 HDMI clock more
stable? By experience result? I would like to prove it by the source
code.

Does 'stable' means that hardware could generate the frequency most
close to the target frequency? If it does, I think you could compare the
frequency generated by original code and applying this series for all
the usually-used frequency. I also need you to show the clock tree and
all setting of each divider so we could review that is this series good
enough. Also, describe these in cover latter.

You have mail to dri-devel [1] and linux-mediatek [2], but these patches
does not show in web site. Maybe your mail is not plain text, please fix
this and resend patches.

[1] https://lists.freedesktop.org/archives/dri-devel/
[2] http://lists.infradead.org/pipermail/linux-mediatek/

Regards,
CK

On Fri, 2019-01-25 at 12:01 +0800, Wangyan Wang wrote:
> V3 adopt maintainer's suggestion.
> Here is the change list between V2 & V3:
> 1. add "Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>"
> in commit message
> 
> 2. add modify description in patch 
> "drm/mediatek: fix the rate and divder ..."
>  
> chunhui dai (8):
>   drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
>     hardware
>   drm/mediatek: move the setting of fixed divider
>   drm/mediatek: using different flags of clk for HDMI phy
>   drm/mediatek: fix the rate and divder of hdmi phy for MT2701
>   clk: mediatek: add MUX_GATE_FLAGS_2
>   clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
>   drm/mediatek: using new factor for tvdpll in MT2701
>   drm/mediatek: fix the rate of parent for hdmi phy in MT2701
> 
>  drivers/clk/mediatek/clk-mt2701.c             |  4 +-
>  drivers/clk/mediatek/clk-mtk.c                |  2 +-
>  drivers/clk/mediatek/clk-mtk.h                | 20 +++++--
>  drivers/gpu/drm/mediatek/mtk_dpi.c            |  8 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c       | 34 +++--------
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.h       |  7 +--
>  .../gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c    | 56 +++++++++++++++++--
>  .../gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c    | 23 ++++++++
>  8 files changed, 102 insertions(+), 52 deletions(-)
>