[PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value

[PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value

[Eugen.Hristev]

From: Eugen Hristev <eugen.hristev@microchip.com>

Product datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---

datasheet link http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
chapter 57.7.10 optimal setting of the PLLA and PLLUTMI

 drivers/clk/at91/clk-sam9x60-pll.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 34b8178..dfb354a 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -25,7 +25,8 @@
 #define		PMC_PLL_CTRL1_MUL_MSK		GENMASK(30, 24)
 
 #define PMC_PLL_ACR	0x18
-#define		PMC_PLL_ACR_DEFAULT		0x1b040010UL
+#define		PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL
+#define		PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL
 #define		PMC_PLL_ACR_UTMIVR		BIT(12)
 #define		PMC_PLL_ACR_UTMIBG		BIT(13)
 #define		PMC_PLL_ACR_LOOP_FILTER_MSK	GENMASK(31, 24)
@@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
 	}
 
 	/* Recommended value for PMC_PLL_ACR */
-	val = PMC_PLL_ACR_DEFAULT;
+	if (pll->characteristics->upll)
+		val = PMC_PLL_ACR_DEFAULT_UPLL;
+	else
+		val = PMC_PLL_ACR_DEFAULT_PLLA;
 	regmap_write(regmap, PMC_PLL_ACR, val);
 
 	regmap_write(regmap, PMC_PLL_CTRL1,
-- 
2.7.4

Re: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value

[Nicolas.Ferre]

On 11/11/2019 at 14:28, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
> 
> Product datasheet recommends different values for UPLL and PLLA analog control
> register.
> Adapt accordingly.
> 
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Best regards,
   Nicolas

> ---
> 
> datasheet link http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
> chapter 57.7.10 optimal setting of the PLLA and PLLUTMI
> 
>   drivers/clk/at91/clk-sam9x60-pll.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 34b8178..dfb354a 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -25,7 +25,8 @@
>   #define		PMC_PLL_CTRL1_MUL_MSK		GENMASK(30, 24)
>   
>   #define PMC_PLL_ACR	0x18
> -#define		PMC_PLL_ACR_DEFAULT		0x1b040010UL
> +#define		PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL
> +#define		PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL
>   #define		PMC_PLL_ACR_UTMIVR		BIT(12)
>   #define		PMC_PLL_ACR_UTMIBG		BIT(13)
>   #define		PMC_PLL_ACR_LOOP_FILTER_MSK	GENMASK(31, 24)
> @@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>   	}
>   
>   	/* Recommended value for PMC_PLL_ACR */
> -	val = PMC_PLL_ACR_DEFAULT;
> +	if (pll->characteristics->upll)
> +		val = PMC_PLL_ACR_DEFAULT_UPLL;
> +	else
> +		val = PMC_PLL_ACR_DEFAULT_PLLA;
>   	regmap_write(regmap, PMC_PLL_ACR, val);
>   
>   	regmap_write(regmap, PMC_PLL_CTRL1,
> 


-- 
Nicolas Ferre

Re: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value

[Stephen Boyd]

Quoting Eugen.Hristev@microchip.com (2019-11-11 05:28:57)
> From: Eugen Hristev <eugen.hristev@microchip.com>
> 
> Product datasheet recommends different values for UPLL and PLLA analog control
> register.
> Adapt accordingly.
> 
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---

Applied to clk-next