* [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
@ 2019-11-11 13:28 Eugen.Hristev
2019-11-12 10:38 ` Nicolas.Ferre
2020-01-06 3:06 ` Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Eugen.Hristev @ 2019-11-11 13:28 UTC (permalink / raw)
To: mturquette, sboyd, alexandre.belloni, linux-clk,
linux-arm-kernel, linux-kernel
Cc: Nicolas.Ferre, Ludovic.Desroches, Eugen.Hristev
From: Eugen Hristev <eugen.hristev@microchip.com>
Product datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
datasheet link http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
chapter 57.7.10 optimal setting of the PLLA and PLLUTMI
drivers/clk/at91/clk-sam9x60-pll.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 34b8178..dfb354a 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -25,7 +25,8 @@
#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
#define PMC_PLL_ACR 0x18
-#define PMC_PLL_ACR_DEFAULT 0x1b040010UL
+#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL
+#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL
#define PMC_PLL_ACR_UTMIVR BIT(12)
#define PMC_PLL_ACR_UTMIBG BIT(13)
#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
@@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
}
/* Recommended value for PMC_PLL_ACR */
- val = PMC_PLL_ACR_DEFAULT;
+ if (pll->characteristics->upll)
+ val = PMC_PLL_ACR_DEFAULT_UPLL;
+ else
+ val = PMC_PLL_ACR_DEFAULT_PLLA;
regmap_write(regmap, PMC_PLL_ACR, val);
regmap_write(regmap, PMC_PLL_CTRL1,
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
2019-11-11 13:28 [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value Eugen.Hristev
@ 2019-11-12 10:38 ` Nicolas.Ferre
2020-01-06 3:06 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Nicolas.Ferre @ 2019-11-12 10:38 UTC (permalink / raw)
To: Eugen.Hristev, mturquette, sboyd, alexandre.belloni, linux-clk,
linux-arm-kernel, linux-kernel
Cc: Ludovic.Desroches
On 11/11/2019 at 14:28, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
>
> Product datasheet recommends different values for UPLL and PLLA analog control
> register.
> Adapt accordingly.
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Best regards,
Nicolas
> ---
>
> datasheet link http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
> chapter 57.7.10 optimal setting of the PLLA and PLLUTMI
>
> drivers/clk/at91/clk-sam9x60-pll.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 34b8178..dfb354a 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -25,7 +25,8 @@
> #define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
>
> #define PMC_PLL_ACR 0x18
> -#define PMC_PLL_ACR_DEFAULT 0x1b040010UL
> +#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL
> +#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL
> #define PMC_PLL_ACR_UTMIVR BIT(12)
> #define PMC_PLL_ACR_UTMIBG BIT(13)
> #define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
> @@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
> }
>
> /* Recommended value for PMC_PLL_ACR */
> - val = PMC_PLL_ACR_DEFAULT;
> + if (pll->characteristics->upll)
> + val = PMC_PLL_ACR_DEFAULT_UPLL;
> + else
> + val = PMC_PLL_ACR_DEFAULT_PLLA;
> regmap_write(regmap, PMC_PLL_ACR, val);
>
> regmap_write(regmap, PMC_PLL_CTRL1,
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
2019-11-11 13:28 [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value Eugen.Hristev
2019-11-12 10:38 ` Nicolas.Ferre
@ 2020-01-06 3:06 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2020-01-06 3:06 UTC (permalink / raw)
To: Eugen.Hristev, alexandre.belloni, linux-arm-kernel, linux-clk,
linux-kernel, mturquette
Cc: Nicolas.Ferre, Ludovic.Desroches, Eugen.Hristev
Quoting Eugen.Hristev@microchip.com (2019-11-11 05:28:57)
> From: Eugen Hristev <eugen.hristev@microchip.com>
>
> Product datasheet recommends different values for UPLL and PLLA analog control
> register.
> Adapt accordingly.
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-01-06 3:06 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-11 13:28 [PATCH] clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value Eugen.Hristev
2019-11-12 10:38 ` Nicolas.Ferre
2020-01-06 3:06 ` Stephen Boyd
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).