From: Rahul Tanwar <rtanwar@maxlinear.com>
To: <sboyd@kernel.org>, <mturquette@baylibre.com>,
<linux-clk@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-lgm-soc@maxlinear.com>,
"Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes
Date: Thu, 22 Sep 2022 14:24:27 +0800 [thread overview]
Message-ID: <3bcdfdf0f66dd2fdcffbdeabb5e3ab0bfb2e3489.1663827071.git.rtanwar@maxlinear.com> (raw)
In-Reply-To: <cover.1663827071.git.rtanwar@maxlinear.com>
Some clocks support parent clock dividers but they do not
support clock gating (clk enable/disable). Such types of
clocks might call API's for get/set_reg_val routines with
width as 0 during clk_prepare_enable() call. Handle such
cases by first validating width during clk_prepare_enable()
while still supporting clk_set_rate() correctly.
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 73ce84345f81..46daf9ebd6c9 100644
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -299,29 +299,51 @@ struct lgm_clk_branch {
static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
u8 shift, u8 width, u32 set_val)
{
- u32 mask = (GENMASK(width - 1, 0) << shift);
+ u32 mask;
+ /*
+ * Some clocks support parent clock dividers but they do not
+ * support clock gating (clk enable/disable). Such types of
+ * clocks might call this function with width as 0 during
+ * clk_prepare_enable() call. Handle such cases by not doing
+ * anything during clk_prepare_enable() but handle clk_set_rate()
+ * correctly
+ */
+ if (!width)
+ return;
+
+ mask = (GENMASK(width - 1, 0) << shift);
regmap_update_bits(membase, reg, mask, set_val << shift);
}
static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
u8 shift, u8 width)
{
- u32 mask = (GENMASK(width - 1, 0) << shift);
+ u32 mask;
u32 val;
+ /*
+ * Some clocks support parent clock dividers but they do not
+ * support clock gating (clk enable/disable). Such types of
+ * clocks might call this function with width as 0 during
+ * clk_prepare_enable() call. Handle such cases by not doing
+ * anything during clk_prepare_enable() but handle clk_set_rate()
+ * correctly
+ */
+ if (!width)
+ return 0;
+
if (regmap_read(membase, reg, &val)) {
WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
return 0;
}
+ mask = (GENMASK(width - 1, 0) << shift);
val = (val & mask) >> shift;
return val;
}
-
-
int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
const struct lgm_clk_branch *list,
unsigned int nr_clk);
--
2.17.1
next prev parent reply other threads:[~2022-09-22 6:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:24 [PATCH RESEND v2 0/5] Modify MxL's CGU clk driver to make it secure boot compatible Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Rahul Tanwar
2022-09-29 0:14 ` Stephen Boyd
2022-09-29 5:29 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 2/5] clk: mxl: Remove unnecessary spinlocks Rahul Tanwar
2022-09-29 0:16 ` Stephen Boyd
2022-09-29 5:37 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Rahul Tanwar
2022-09-29 0:17 ` Stephen Boyd
2022-09-29 5:45 ` Rahul Tanwar
[not found] ` <20220930010123.38984C4347C@smtp.kernel.org>
2022-10-05 9:36 ` Rahul Tanwar
[not found] ` <20221005202037.E7B43C433C1@smtp.kernel.org>
2022-10-11 7:28 ` Rahul Tanwar
[not found] ` <20221011174345.906BAC433D7@smtp.kernel.org>
2022-10-12 9:34 ` Rahul Tanwar
2022-10-11 7:33 ` Rahul Tanwar
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` Rahul Tanwar [this message]
2022-09-29 0:20 ` [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes Stephen Boyd
2022-09-29 6:10 ` Rahul Tanwar
[not found] ` <20220930010212.7860DC433C1@smtp.kernel.org>
2022-10-05 9:36 ` Rahul Tanwar
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change Rahul Tanwar
2022-09-29 0:18 ` Stephen Boyd
2022-09-29 5:46 ` Rahul Tanwar
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