From: Rahul Tanwar <rtanwar@maxlinear.com>
To: <sboyd@kernel.org>, <mturquette@baylibre.com>,
<linux-clk@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-lgm-soc@maxlinear.com>,
"Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver
Date: Thu, 22 Sep 2022 14:24:26 +0800 [thread overview]
Message-ID: <5a88bd5a9e93cc6e794080e5cac821ae0c27ec56.1663827071.git.rtanwar@maxlinear.com> (raw)
In-Reply-To: <cover.1663827071.git.rtanwar@maxlinear.com>
In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled
from EPU (power management IP) in certain power saving modes. If gate
clocks are allowed to be enabled/disabled from CGU clk driver, then
there arises a conflict where in case clk driver disables a gate clk,
and then EPU tries to disable the same gate clk, then it will hang
polling for the clk gated successful status.
To avoid such a conflict, disable gate clocks enabling/disabling from
CGU clk driver. But add a GATE_CLK_HW flag to control this in order to
be backward compatible with other SoCs which share the same CGU IP but
not the same EPU IP.
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
drivers/clk/x86/clk-cgu.c | 32 ++++++++++++++++++++++++--------
drivers/clk/x86/clk-cgu.h | 1 +
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 1f7e93de67bc..d24173cfe0b0 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -258,8 +258,12 @@ static int lgm_clk_gate_enable(struct clk_hw *hw)
struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
unsigned int reg;
- reg = GATE_HW_REG_EN(gate->reg);
- lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
+ if (gate->flags & GATE_CLK_HW) {
+ reg = GATE_HW_REG_EN(gate->reg);
+ lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
+ } else {
+ gate->reg = 1;
+ }
return 0;
}
@@ -269,8 +273,12 @@ static void lgm_clk_gate_disable(struct clk_hw *hw)
struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
unsigned int reg;
- reg = GATE_HW_REG_DIS(gate->reg);
- lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
+ if (gate->flags & GATE_CLK_HW) {
+ reg = GATE_HW_REG_DIS(gate->reg);
+ lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1);
+ } else {
+ gate->reg = 0;
+ }
}
static int lgm_clk_gate_is_enabled(struct clk_hw *hw)
@@ -278,8 +286,12 @@ static int lgm_clk_gate_is_enabled(struct clk_hw *hw)
struct lgm_clk_gate *gate = to_lgm_clk_gate(hw);
unsigned int reg, ret;
- reg = GATE_HW_REG_STAT(gate->reg);
- ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1);
+ if (gate->flags & GATE_CLK_HW) {
+ reg = GATE_HW_REG_STAT(gate->reg);
+ ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1);
+ } else {
+ ret = gate->reg;
+ }
return ret;
}
@@ -315,7 +327,8 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx,
init.num_parents = pname ? 1 : 0;
gate->membase = ctx->membase;
- gate->reg = reg;
+ if (cflags & GATE_CLK_HW)
+ gate->reg = reg;
gate->shift = shift;
gate->flags = cflags;
gate->hw.init = &init;
@@ -326,7 +339,10 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx,
return ERR_PTR(ret);
if (cflags & CLOCK_FLAG_VAL_INIT) {
- lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val);
+ if (cflags & GATE_CLK_HW)
+ lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val);
+ else
+ gate->reg = 1;
}
return hw;
diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 0aa0f35d63a0..73ce84345f81 100644
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -197,6 +197,7 @@ struct lgm_clk_branch {
/* clock flags definition */
#define CLOCK_FLAG_VAL_INIT BIT(16)
#define MUX_CLK_SW BIT(17)
+#define GATE_CLK_HW BIT(18)
#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
_shift, _width, _cf, _v) \
--
2.17.1
next prev parent reply other threads:[~2022-09-22 6:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:24 [PATCH RESEND v2 0/5] Modify MxL's CGU clk driver to make it secure boot compatible Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Rahul Tanwar
2022-09-29 0:14 ` Stephen Boyd
2022-09-29 5:29 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 2/5] clk: mxl: Remove unnecessary spinlocks Rahul Tanwar
2022-09-29 0:16 ` Stephen Boyd
2022-09-29 5:37 ` Rahul Tanwar
2022-09-22 6:24 ` Rahul Tanwar [this message]
2022-09-29 0:17 ` [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Stephen Boyd
2022-09-29 5:45 ` Rahul Tanwar
[not found] ` <20220930010123.38984C4347C@smtp.kernel.org>
2022-10-05 9:36 ` Rahul Tanwar
[not found] ` <20221005202037.E7B43C433C1@smtp.kernel.org>
2022-10-11 7:28 ` Rahul Tanwar
[not found] ` <20221011174345.906BAC433D7@smtp.kernel.org>
2022-10-12 9:34 ` Rahul Tanwar
2022-10-11 7:33 ` Rahul Tanwar
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes Rahul Tanwar
2022-09-29 0:20 ` Stephen Boyd
2022-09-29 6:10 ` Rahul Tanwar
[not found] ` <20220930010212.7860DC433C1@smtp.kernel.org>
2022-10-05 9:36 ` Rahul Tanwar
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change Rahul Tanwar
2022-09-29 0:18 ` Stephen Boyd
2022-09-29 5:46 ` Rahul Tanwar
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