From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Joseph Lo <josephl@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>, <pgaikwad@nvidia.com>,
<linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
<jckuo@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks
Date: Thu, 18 Jul 2019 12:11:03 -0700 [thread overview]
Message-ID: <7717c538-106e-743a-82be-feb627dfa12f@nvidia.com> (raw)
In-Reply-To: <8bca130c-c95c-591e-2f6e-f02538f8f8b8@nvidia.com>
On 7/18/19 11:29 AM, Sowjanya Komatineni wrote:
>
> On 7/18/19 10:41 AM, Sowjanya Komatineni wrote:
>>
>> On 7/18/19 10:22 AM, Sowjanya Komatineni wrote:
>>>
>>> On 7/18/19 9:34 AM, Dmitry Osipenko wrote:
>>>> 18.07.2019 4:15, Sowjanya Komatineni пишет:
>>>>
>>>> [snip]
>>>>
>>>>>>> Please try to fix all missing dependencies and orderings.
>>>>>> Peter,
>>>>>>
>>>>>> dfllCPU_OUT is the first one to go thru restore when
>>>>>> clk_restore_context traverses thru the list.
>>>>>>
>>>>>> dfllCPU_OUT has dependency on DFLL_ref and DFLL_SOC but this
>>>>>> dependency is unknown to clock-tree.
>>>>>>
>>>>>> We can add DFLL_REF and DFLL_SOC as parents to dfllCPU_OUT during
>>>>>> register so dfllCPU_OUT save/restore happens after their parents are
>>>>>> restored.
>>>>>>
>>>>>> But DFLL needs both of these to be restored before DFLLCPU_Out
>>>>>> and as
>>>>>> DFLL_SOC restore always happens after the REF, thinking to add
>>>>>> DFLL_SOC as parent to dfllCPU_OUT so save/restore follows after
>>>>>> their
>>>>>> dependencies.
>>>>>>
>>>>>> Please comment.
>>>>>>
>>>>> Did quick try and I see by adding dfll-soc as parent to
>>>>> dfllCPU_OUT, its
>>>>> in proper order after all its dependencies.
>>>>>
>>>>> Can now add dfll save/restore to do dfll reinit during restore..
>>>>>
>>>> If dfllCPU_OUT can work properly with dfll-soc being disabled, then
>>>> this
>>>> kind of dependency isn't very correct and just papers over the real
>>>> problem, which is that there should be a way for CCF to specify
>>>> multiple
>>>> dependencies for the clock or the reverse ordering should be used for
>>>> the restoring.
>>>
>>> dfll will not work without dfll-soc enabled.
>>>
>>> CLDVFS control logic is split into 2 clock domains. dvfs_ref_clk and
>>> dvfs_soc_clk.
>>>
>>> Majority of the control logic is clocked from dvfs_soc_clk for
>>> interfacing control registers.
>>>
>> Note on reverse ordering for restore. Currently restore order goes
>> thru clock list and for each root goes thru parent -> child restore.
>>
>> this order is correct and also all clocks are parented properly so
>> they follow proper order.
>>
>> dfllCPU is the only one where current driver doesn't take care of
>> dependency in dfll_soc which gets enabled only after dfll_ref.
>>
>>
>> Based on dfllCPU control logic module design, dfll_ref and dfll_soc
>> should be enabled prior to dfll init/enable.
>>
>> So parenting dfll_soc to dfllCPU keeps proper order.
>>
>
> 1. With dfllCPU parenting to dfll_soc, its keeps it in expected order
> and we don't define any parent clk_ops anyway for this, so should be OK?
>
> OR
>
> 2. Any suggestion on how to define/specify dependencies for clock
> other than parenting to follow proper order in clock tree as
> clk_save_context and clk_restore_context strictly goes thru clock tree
> order and all other clocks are parented properly except for dfllCPU
> where there is no parent. Techinically dfll_ref & dfll_soc are not
> parents but they need to be configured prior to dfll reinit.
>
> OR
>
> 3. I don't see way to override clk_save_context/clk_restore_context
> APIs to change the way of traversal so I can modify to traverse in
> expected order without dfllCPU parenting.
instead of using core API of save/restore context, probably can change
traversing to skip the 1st root in clock tree during initial traversing
and at the end invoke restore for 1st node.
>
> OR
>
> 4. dfll re-init can be done in dfll-fcpu driver pm_ops which actually
> registers dfll or at the end of tegra210_clock resume
>
Please suggest if you agree with either 1/3/4.
next prev parent reply other threads:[~2019-07-18 19:11 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 2:12 [PATCH V5 00/18] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 01/18] irqchip: tegra: Do not disable COP IRQ during suspend Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-06-28 11:56 ` Dmitry Osipenko
2019-06-28 12:05 ` Dmitry Osipenko
2019-06-28 23:00 ` Sowjanya Komatineni
2019-06-29 12:38 ` Dmitry Osipenko
2019-06-29 15:40 ` Dmitry Osipenko
2019-06-29 15:46 ` Dmitry Osipenko
2019-06-29 15:58 ` Dmitry Osipenko
2019-06-29 16:28 ` Dmitry Osipenko
2019-07-04 7:31 ` Linus Walleij
2019-07-04 10:40 ` Dmitry Osipenko
2019-07-13 5:31 ` Sowjanya Komatineni
2019-07-14 21:41 ` Dmitry Osipenko
2019-07-13 5:48 ` Sowjanya Komatineni
2019-07-04 7:26 ` Linus Walleij
2019-06-28 2:12 ` [PATCH V5 03/18] clk: tegra: Save and restore divider rate Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 04/18] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 05/18] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 06/18] clk: tegra: Save and restore CPU and System clocks context Sowjanya Komatineni
2019-06-29 13:33 ` Dmitry Osipenko
2019-06-29 15:26 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 07/18] clk: tegra: Support for saving and restoring OSC context Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 08/18] clk: tegra: Add suspend resume support for DFLL Sowjanya Komatineni
2019-06-29 13:28 ` Dmitry Osipenko
2019-06-29 21:45 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 09/18] clk: tegra: Add save and restore context support for peripheral clocks Sowjanya Komatineni
2019-06-29 13:17 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 10/18] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks Sowjanya Komatineni
2019-06-29 13:14 ` Dmitry Osipenko
2019-06-29 15:10 ` Dmitry Osipenko
2019-07-13 5:54 ` Sowjanya Komatineni
2019-07-14 21:41 ` Dmitry Osipenko
2019-07-16 0:35 ` Sowjanya Komatineni
2019-07-16 3:00 ` Sowjanya Komatineni
2019-07-16 3:41 ` Sowjanya Komatineni
2019-07-16 3:50 ` Dmitry Osipenko
2019-07-16 4:37 ` Sowjanya Komatineni
2019-07-16 5:37 ` Dmitry Osipenko
2019-07-16 6:20 ` Dmitry Osipenko
2019-07-16 6:35 ` Sowjanya Komatineni
2019-07-16 7:24 ` Joseph Lo
2019-07-16 8:06 ` Peter De Schrijver
2019-07-16 15:00 ` Dmitry Osipenko
2019-07-16 16:50 ` Sowjanya Komatineni
2019-07-16 18:19 ` Sowjanya Komatineni
2019-07-16 18:25 ` Dmitry Osipenko
2019-07-16 18:30 ` Sowjanya Komatineni
2019-07-16 18:43 ` Dmitry Osipenko
2019-07-16 19:26 ` Sowjanya Komatineni
2019-07-16 20:47 ` Dmitry Osipenko
2019-07-16 21:12 ` Sowjanya Komatineni
2019-07-16 21:21 ` Dmitry Osipenko
2019-07-16 21:35 ` Sowjanya Komatineni
2019-07-16 22:00 ` Dmitry Osipenko
2019-07-16 22:06 ` Sowjanya Komatineni
2019-07-17 2:18 ` Sowjanya Komatineni
2019-07-17 2:35 ` Sowjanya Komatineni
2019-07-17 4:11 ` Dmitry Osipenko
[not found] ` <77df234f-aa40-0319-a593-f1f19f0f1c2a@nvidia.com>
2019-07-17 5:42 ` Dmitry Osipenko
2019-07-17 5:55 ` Sowjanya Komatineni
2019-07-17 6:33 ` Dmitry Osipenko
2019-07-17 6:36 ` Sowjanya Komatineni
2019-07-17 15:17 ` Dmitry Osipenko
2019-07-17 17:29 ` Sowjanya Komatineni
2019-07-17 18:32 ` Dmitry Osipenko
2019-07-17 18:51 ` Sowjanya Komatineni
2019-07-17 18:54 ` Sowjanya Komatineni
2019-07-17 19:43 ` Dmitry Osipenko
2019-07-17 20:01 ` Sowjanya Komatineni
2019-07-17 20:11 ` Sowjanya Komatineni
2019-07-17 21:29 ` Sowjanya Komatineni
2019-07-17 21:30 ` Dmitry Osipenko
2019-07-17 21:51 ` Sowjanya Komatineni
2019-07-17 21:57 ` Sowjanya Komatineni
2019-07-17 22:48 ` Dmitry Osipenko
2019-07-17 23:36 ` Sowjanya Komatineni
2019-07-17 23:44 ` Dmitry Osipenko
2019-07-18 0:25 ` Sowjanya Komatineni
2019-07-18 1:15 ` Sowjanya Komatineni
2019-07-18 16:34 ` Dmitry Osipenko
2019-07-18 17:22 ` Sowjanya Komatineni
2019-07-18 17:41 ` Sowjanya Komatineni
2019-07-18 18:29 ` Sowjanya Komatineni
2019-07-18 19:11 ` Sowjanya Komatineni [this message]
2019-07-18 19:42 ` Peter De Schrijver
2019-07-18 20:26 ` Dmitry Osipenko
2019-07-18 20:36 ` Sowjanya Komatineni
2019-07-18 22:52 ` Dmitry Osipenko
2019-07-18 23:08 ` Sowjanya Komatineni
2019-07-18 23:52 ` Dmitry Osipenko
2019-07-17 3:54 ` Dmitry Osipenko
2019-07-17 4:01 ` Sowjanya Komatineni
2019-07-18 19:18 ` Peter De Schrijver
2019-07-18 19:24 ` Sowjanya Komatineni
2019-07-18 20:11 ` Dmitry Osipenko
2019-07-18 20:32 ` Dmitry Osipenko
2019-07-18 19:15 ` Peter De Schrijver
2019-06-29 15:13 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 12/18] soc/tegra: pmc: Allow support for more tegra wake Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 13/18] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-06-29 13:11 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 14/18] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 15/18] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 16/18] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-06-29 13:00 ` Dmitry Osipenko
2019-06-29 13:02 ` Dmitry Osipenko
2019-06-28 2:12 ` [PATCH V5 17/18] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-06-28 2:12 ` [PATCH V5 18/18] arm64: dts: tegra210-p3450: Jetson nano " Sowjanya Komatineni
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