From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, Chet Douglas <chet.r.douglas@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [RFC PATCH v2 10/28] cxl/core: Store global list of root ports
Date: Fri, 22 Oct 2021 11:36:51 -0700 [thread overview]
Message-ID: <20211022183709.1199701-11-ben.widawsky@intel.com> (raw)
In-Reply-To: <20211022183709.1199701-1-ben.widawsky@intel.com>
CXL root ports (the downstream port to a host bridge) are to be
enumerated by a platform specific driver. In the case of ACPI compliant
systems, this is like the cxl_acpi driver. Root ports are the first
CXL spec defined component that can be "found" by that platform specific
driver.
By storing a list of these root ports components in lower levels of the
topology (switches and endpoints), have a mechanism to walk up their
device hierarchy to find an enumerated root port. This will be necessary
for region programming.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/acpi.c | 4 ++--
drivers/cxl/core/bus.c | 34 +++++++++++++++++++++++++++++++++-
drivers/cxl/cxl.h | 5 ++++-
tools/testing/cxl/mock_acpi.c | 4 ++--
4 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 8cca0814dfb8..625c5d95b83f 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -231,7 +231,7 @@ __mock int match_add_root_ports(struct pci_dev *pdev, void *data)
creg = cxl_reg_block(pdev, &map);
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
- rc = cxl_add_dport(port, &pdev->dev, port_num, creg);
+ rc = cxl_add_dport(port, &pdev->dev, port_num, creg, true);
if (rc) {
ctx->error = rc;
return rc;
@@ -406,7 +406,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
dev_dbg(host, "No CHBS found for Host Bridge: %s\n",
dev_name(match));
- rc = cxl_add_dport(root_port, match, uid, get_chbcr(chbs));
+ rc = cxl_add_dport(root_port, match, uid, get_chbcr(chbs), false);
if (rc) {
dev_err(host, "failed to add downstream port: %s\n",
dev_name(match));
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index dffbd0ac64af..03394a3ae75f 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -25,6 +25,8 @@
*/
static DEFINE_IDA(cxl_port_ida);
+static LIST_HEAD(cxl_root_ports);
+static DECLARE_RWSEM(root_port_sem);
static ssize_t devtype_show(struct device *dev, struct device_attribute *attr,
char *buf)
@@ -268,12 +270,31 @@ struct cxl_port *to_cxl_port(struct device *dev)
}
EXPORT_SYMBOL_GPL(to_cxl_port);
+struct cxl_dport *cxl_get_root_dport(struct device *dev)
+{
+ struct cxl_dport *ret = NULL;
+ struct cxl_dport *dport;
+
+ down_read(&root_port_sem);
+ list_for_each_entry(dport, &cxl_root_ports, root_port_link) {
+ if (dport->dport == dev) {
+ ret = dport;
+ break;
+ }
+ }
+
+ up_read(&root_port_sem);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(cxl_get_root_dport);
+
static void unregister_port(void *_port)
{
struct cxl_port *port = _port;
struct cxl_dport *dport;
device_lock(&port->dev);
+ down_read(&root_port_sem);
list_for_each_entry(dport, &port->dports, list) {
char link_name[CXL_TARGET_STRLEN];
@@ -281,7 +302,10 @@ static void unregister_port(void *_port)
dport->port_id) >= CXL_TARGET_STRLEN)
continue;
sysfs_remove_link(&port->dev.kobj, link_name);
+
+ list_del_init(&dport->root_port_link);
}
+ up_read(&root_port_sem);
device_unlock(&port->dev);
device_unregister(&port->dev);
}
@@ -431,12 +455,13 @@ static int add_dport(struct cxl_port *port, struct cxl_dport *new)
* @dport_dev: firmware or PCI device representing the dport
* @port_id: identifier for this dport in a decoder's target list
* @component_reg_phys: optional location of CXL component registers
+ * @root_port: is this a root port (hostbridge downstream)
*
* Note that all allocations and links are undone by cxl_port deletion
* and release.
*/
int cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id,
- resource_size_t component_reg_phys)
+ resource_size_t component_reg_phys, bool root_port)
{
char link_name[CXL_TARGET_STRLEN];
struct cxl_dport *dport;
@@ -451,6 +476,7 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id,
return -ENOMEM;
INIT_LIST_HEAD(&dport->list);
+ INIT_LIST_HEAD(&dport->root_port_link);
dport->dport = get_device(dport_dev);
dport->port_id = port_id;
dport->component_reg_phys = component_reg_phys;
@@ -464,6 +490,12 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id,
if (rc)
goto err;
+ if (root_port) {
+ down_write(&root_port_sem);
+ list_add_tail(&dport->root_port_link, &cxl_root_ports);
+ up_write(&root_port_sem);
+ }
+
return 0;
err:
cxl_dport_release(dport);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index ad22caf9135c..d26d97e1098d 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -291,6 +291,7 @@ struct cxl_port {
* @component_reg_phys: downstream port component registers
* @port: reference to cxl_port that contains this downstream port
* @list: node for a cxl_port's list of cxl_dport instances
+ * @root_port_link: node for global list of root ports
*/
struct cxl_dport {
struct device *dport;
@@ -298,6 +299,7 @@ struct cxl_dport {
resource_size_t component_reg_phys;
struct cxl_port *port;
struct list_head list;
+ struct list_head root_port_link;
};
struct cxl_port *to_cxl_port(struct device *dev);
@@ -306,7 +308,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
struct cxl_port *parent_port);
int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
- resource_size_t component_reg_phys);
+ resource_size_t component_reg_phys, bool root_port);
+struct cxl_dport *cxl_get_root_dport(struct device *dev);
struct cxl_decoder *to_cxl_decoder(struct device *dev);
bool is_root_decoder(struct device *dev);
diff --git a/tools/testing/cxl/mock_acpi.c b/tools/testing/cxl/mock_acpi.c
index 4c8a493ace56..ddefc4345f36 100644
--- a/tools/testing/cxl/mock_acpi.c
+++ b/tools/testing/cxl/mock_acpi.c
@@ -57,7 +57,7 @@ static int match_add_root_port(struct pci_dev *pdev, void *data)
/* TODO walk DVSEC to find component register base */
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
- rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
+ rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE, true);
if (rc) {
dev_err(dev, "failed to add dport: %s (%d)\n",
dev_name(&pdev->dev), rc);
@@ -78,7 +78,7 @@ static int mock_add_root_port(struct platform_device *pdev, void *data)
struct device *dev = ctx->dev;
int rc;
- rc = cxl_add_dport(port, &pdev->dev, pdev->id, CXL_RESOURCE_NONE);
+ rc = cxl_add_dport(port, &pdev->dev, pdev->id, CXL_RESOURCE_NONE, true);
if (rc) {
dev_err(dev, "failed to add dport: %s (%d)\n",
dev_name(&pdev->dev), rc);
--
2.33.1
next prev parent reply other threads:[~2021-10-22 18:37 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 18:36 [RFC PATCH v2 00/28] CXL Region Creation / HDM decoder programming Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-10-29 20:15 ` Dan Williams
2021-10-29 21:20 ` Ben Widawsky
2021-10-29 21:39 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 02/28] cxl: Move register block enumeration to core Ben Widawsky
2021-10-29 20:23 ` Dan Williams
2021-10-29 21:23 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 03/28] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-10-29 20:28 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 04/28] cxl: Add helper for new drivers Ben Widawsky
2021-10-29 20:30 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource Ben Widawsky
2021-10-29 20:50 ` Dan Williams
2021-10-29 21:26 ` Ben Widawsky
2021-10-29 22:22 ` Dan Williams
2021-10-29 22:37 ` Ben Widawsky
2021-11-01 14:33 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 06/28] cxl: Introduce endpoint decoders Ben Widawsky
2021-10-29 21:00 ` Dan Williams
2021-10-29 22:02 ` Ben Widawsky
2021-10-29 22:25 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 07/28] cxl/core: Move target population locking to caller Ben Widawsky
2021-10-29 23:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 08/28] cxl/port: Introduce a port driver Ben Widawsky
2021-10-30 1:37 ` Dan Williams
2021-10-31 17:53 ` Dan Williams
2021-10-31 18:10 ` Dan Williams
2021-11-01 17:36 ` Ben Widawsky
2021-11-01 17:53 ` Ben Widawsky
2021-11-01 17:54 ` Ben Widawsky
2021-11-02 3:31 ` Dan Williams
2021-11-02 16:27 ` Ben Widawsky
2021-11-02 17:21 ` Dan Williams
2021-11-02 16:58 ` Ben Widawsky
2021-11-04 19:10 ` Dan Williams
2021-11-04 19:49 ` Ben Widawsky
2021-11-04 20:04 ` Dan Williams
2021-11-04 21:25 ` Ben Widawsky
2021-11-04 16:37 ` Ben Widawsky
2021-11-04 19:17 ` Dan Williams
2021-11-04 19:46 ` Ben Widawsky
2021-11-04 20:00 ` Dan Williams
2021-11-04 21:26 ` Ben Widawsky
2021-11-03 15:18 ` Jonathan Cameron
2021-10-22 18:36 ` [RFC PATCH v2 09/28] cxl/acpi: Map single port host bridge component registers Ben Widawsky
2021-10-31 18:03 ` Dan Williams
2021-11-01 17:07 ` Ben Widawsky
2021-11-02 2:15 ` Dan Williams
2021-11-02 16:31 ` Ben Widawsky
2021-11-02 17:46 ` Dan Williams
2021-11-02 17:57 ` Ben Widawsky
2021-11-02 18:10 ` Dan Williams
2021-11-02 18:27 ` Ben Widawsky
2021-11-02 18:49 ` Dan Williams
2021-11-02 21:15 ` Ben Widawsky
2021-11-02 21:34 ` Dan Williams
2021-11-02 21:47 ` Ben Widawsky
2021-10-22 18:36 ` Ben Widawsky [this message]
2021-10-31 18:32 ` [RFC PATCH v2 10/28] cxl/core: Store global list of root ports Dan Williams
2021-11-01 18:43 ` Ben Widawsky
2021-11-02 2:04 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 11/28] cxl/acpi: Rescan bus at probe completion Ben Widawsky
2021-10-31 19:25 ` Dan Williams
2021-11-01 18:56 ` Ben Widawsky
2021-11-01 21:45 ` Ben Widawsky
2021-11-02 1:56 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 12/28] cxl/core: Store component register base for memdevs Ben Widawsky
2021-10-31 20:13 ` Dan Williams
2021-11-01 21:50 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 13/28] cxl: Flesh out register names Ben Widawsky
2021-10-31 20:18 ` Dan Williams
2021-11-01 22:00 ` Ben Widawsky
2021-11-02 1:53 ` Dan Williams
2021-11-03 15:53 ` Jonathan Cameron
2021-11-03 16:03 ` Ben Widawsky
2021-11-03 16:42 ` Jonathan Cameron
2021-11-03 17:05 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 14/28] cxl: Hide devm host for ports Ben Widawsky
2021-10-31 21:14 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 15/28] cxl/core: Introduce API to scan switch ports Ben Widawsky
2021-11-01 5:39 ` Dan Williams
2021-11-01 22:56 ` Ben Widawsky
2021-11-02 1:45 ` Dan Williams
2021-11-02 16:39 ` Ben Widawsky
2021-11-02 20:00 ` Dan Williams
2021-11-16 16:50 ` Ben Widawsky
2021-11-16 17:51 ` Dan Williams
2021-11-16 18:02 ` Ben Widawsky
2021-11-03 16:08 ` Jonathan Cameron
2021-11-10 17:49 ` Ben Widawsky
2021-11-10 18:10 ` Jonathan Cameron
2021-11-10 21:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 16/28] cxl: Introduce cxl_mem driver Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 18/28] cxl/region: Add region creation ABI Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 19/28] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-12-15 17:47 ` Jonathan Cameron
2021-10-22 18:37 ` [RFC PATCH v2 20/28] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 21/28] cxl/acpi: Handle address space allocation Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 22/28] cxl/region: Address " Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 23/28] cxl/region: Implement XHB verification Ben Widawsky
2022-01-06 16:55 ` Jonathan Cameron
2022-01-06 16:58 ` Ben Widawsky
2022-01-06 17:33 ` Jonathan Cameron
2022-01-06 18:10 ` Jonathan Cameron
2022-01-06 18:34 ` Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 24/28] cxl/region: HB port config verification Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 25/28] cxl/region: Record host bridge target list Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 26/28] cxl/mem: Store the endpoint's uport Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 27/28] cxl/region: Gather HDM decoder resources Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 28/28] cxl: Program decoders for regions Ben Widawsky
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