[PATCH V7 0/7] Refactor and add AHCI support for tegra210

[PATCH V7 0/7] Refactor and add AHCI support for tegra210

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

1. ADD AHCI support for tegra210
2. Extend the tegra AHCI controller device tree binding with tegra210
3. Update initialization sequence
4. Initialize regulators based on chip
5. Disable DevSlp
6. Disable DIPM
---
Preetham Ramchandra (7):
  dt-bindings: ahci-tegra: add binding documentation
  arm64: tegra: Enable AHCI on Jetson TX1
  ata: ahci_tegra: Update initialization sequence
  ata: ahci_tegra: initialize regulators from soc_data
  ata: ahci_tegra: disable devslp for t124
  ata: ahci_tegra: disable DIPM
  ata: ahci_tegra: Add AHCI support for Tegra210

 .../bindings/ata/nvidia,tegra124-ahci.txt          |  35 +-
 arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi     |   6 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  16 +
 drivers/ata/ahci_tegra.c                           | 362 ++++++++++++++++-----
 4 files changed, 329 insertions(+), 90 deletions(-)

-- 
2.7.4

[PATCH V7 4/7] ata: ahci_tegra: initialize regulators from soc_data

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru@nvidia.com>

Get the regulator names to be initialized from soc_data
and initialize them.

Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
v7:
* moved tegra124_supply_names definition to just above
   the tegra124_ahci_soc_data structure.
---
 drivers/ata/ahci_tegra.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 7ffe8a97447a..6aaf8a4571c8 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -164,6 +164,8 @@ struct tegra_ahci_ops {
 };
 
 struct tegra_ahci_soc {
+	const char *const	*supply_names;
+	u32			num_supplies;
 	struct tegra_ahci_ops	ops;
 };
 
@@ -175,7 +177,7 @@ struct tegra_ahci_priv {
 	struct reset_control	   *sata_cold_rst;
 	/* Needs special handling, cannot use ahci_platform */
 	struct clk		   *sata_clk;
-	struct regulator_bulk_data supplies[5];
+	struct regulator_bulk_data *supplies;
 	struct tegra_ahci_soc	   *soc_data;
 };
 
@@ -228,7 +230,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 	struct tegra_ahci_priv *tegra = hpriv->plat_data;
 	int ret;
 
-	ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
+	ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
 				    tegra->supplies);
 	if (ret)
 		return ret;
@@ -257,7 +259,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 
 disable_regulators:
-	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
+	regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
 	return ret;
 }
 
@@ -274,7 +276,7 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
 	clk_disable_unprepare(tegra->sata_clk);
 	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 
-	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
+	regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
 }
 
 static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
@@ -432,7 +434,13 @@ static const struct ata_port_info ahci_tegra_port_info = {
 	.port_ops	= &ahci_tegra_port_ops,
 };
 
+static const char *const tegra124_supply_names[] = {
+	"avdd", "hvdd", "vddio", "target-5v", "target-12v"
+};
+
 static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
+	.supply_names = tegra124_supply_names,
+	.num_supplies = ARRAY_SIZE(tegra124_supply_names),
 	.ops = {
 		.init = tegra124_ahci_init,
 	},
@@ -457,6 +465,7 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 	struct tegra_ahci_priv *tegra;
 	struct resource *res;
 	int ret;
+	unsigned int i;
 
 	hpriv = ahci_platform_get_resources(pdev);
 	if (IS_ERR(hpriv))
@@ -501,13 +510,17 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 		return PTR_ERR(tegra->sata_clk);
 	}
 
-	tegra->supplies[0].supply = "avdd";
-	tegra->supplies[1].supply = "hvdd";
-	tegra->supplies[2].supply = "vddio";
-	tegra->supplies[3].supply = "target-5v";
-	tegra->supplies[4].supply = "target-12v";
+	tegra->supplies = devm_kcalloc(&pdev->dev,
+				       tegra->soc_data->num_supplies,
+				       sizeof(*tegra->supplies), GFP_KERNEL);
+	if (!tegra->supplies)
+		return -ENOMEM;
+
+	for (i = 0; i < tegra->soc_data->num_supplies; i++)
+		tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
 
-	ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
+	ret = devm_regulator_bulk_get(&pdev->dev,
+				      tegra->soc_data->num_supplies,
 				      tegra->supplies);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to get regulators\n");
-- 
2.7.4

Re: [PATCH V7 4/7] ata: ahci_tegra: initialize regulators from soc_data

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:43PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> Get the regulator names to be initialized from soc_data
> and initialize them.
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
> v7:
> * moved tegra124_supply_names definition to just above
>    the tegra124_ahci_soc_data structure.
> ---
>  drivers/ata/ahci_tegra.c | 33 +++++++++++++++++++++++----------
>  1 file changed, 23 insertions(+), 10 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>

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[PATCH V7 5/7] ata: ahci_tegra: disable devslp for t124

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru@nvidia.com>

t124 does not support devslp and it should be
disabled.

Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
 drivers/ata/ahci_tegra.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 6aaf8a4571c8..62f2afb54789 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -145,6 +145,10 @@
 #define FUSE_SATA_CALIB					0x124
 #define FUSE_SATA_CALIB_MASK				0x3
 
+enum {
+	NO_DEVSLP	= (1 << 0),
+};
+
 struct sata_pad_calibration {
 	u8 gen1_tx_amp;
 	u8 gen1_tx_peak;
@@ -166,12 +170,14 @@ struct tegra_ahci_ops {
 struct tegra_ahci_soc {
 	const char *const	*supply_names;
 	u32			num_supplies;
+	u32			quirks;
 	struct tegra_ahci_ops	ops;
 };
 
 struct tegra_ahci_priv {
 	struct platform_device	   *pdev;
 	void __iomem		   *sata_regs;
+	void __iomem		   *sata_aux_regs;
 	struct reset_control	   *sata_rst;
 	struct reset_control	   *sata_oob_rst;
 	struct reset_control	   *sata_cold_rst;
@@ -181,6 +187,18 @@ struct tegra_ahci_priv {
 	struct tegra_ahci_soc	   *soc_data;
 };
 
+static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
+{
+	struct tegra_ahci_priv *tegra = hpriv->plat_data;
+	u32 val;
+
+	if (tegra->sata_aux_regs && (tegra->soc_data->quirks & NO_DEVSLP)) {
+		val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+		val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
+		writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+	}
+}
+
 static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
 {
 	struct tegra_ahci_priv *tegra = hpriv->plat_data;
@@ -400,6 +418,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
 	val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
 	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
 
+	tegra_ahci_handle_quirks(hpriv);
 
 	/* Unmask SATA interrupts */
 
@@ -441,6 +460,7 @@ static const char *const tegra124_supply_names[] = {
 static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
 	.supply_names = tegra124_supply_names,
 	.num_supplies = ARRAY_SIZE(tegra124_supply_names),
+	.quirks = NO_DEVSLP,
 	.ops = {
 		.init = tegra124_ahci_init,
 	},
@@ -485,6 +505,15 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(tegra->sata_regs))
 		return PTR_ERR(tegra->sata_regs);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	/*
+	 * Aux register is optional.
+	 */
+	if (res) {
+		tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(tegra->sata_aux_regs))
+			return PTR_ERR(tegra->sata_aux_regs);
+	}
 
 	tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
 	if (IS_ERR(tegra->sata_rst)) {
-- 
2.7.4

Re: [PATCH V7 5/7] ata: ahci_tegra: disable devslp for t124

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:44PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> t124 does not support devslp and it should be
> disabled.

Please spell out t124 as Tegra124 in the subject and the commit message.

> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
>  drivers/ata/ahci_tegra.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index 6aaf8a4571c8..62f2afb54789 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
> @@ -145,6 +145,10 @@
>  #define FUSE_SATA_CALIB					0x124
>  #define FUSE_SATA_CALIB_MASK				0x3
>  
> +enum {
> +	NO_DEVSLP	= (1 << 0),
> +};
> +
>  struct sata_pad_calibration {
>  	u8 gen1_tx_amp;
>  	u8 gen1_tx_peak;
> @@ -166,12 +170,14 @@ struct tegra_ahci_ops {
>  struct tegra_ahci_soc {
>  	const char *const	*supply_names;
>  	u32			num_supplies;
> +	u32			quirks;
>  	struct tegra_ahci_ops	ops;
>  };

I'd prefer these to be simple booleans, which make the code easier to
read, in my opinion. This could be:

	bool supports_devslp;

>  
>  struct tegra_ahci_priv {
>  	struct platform_device	   *pdev;
>  	void __iomem		   *sata_regs;
> +	void __iomem		   *sata_aux_regs;
>  	struct reset_control	   *sata_rst;
>  	struct reset_control	   *sata_oob_rst;
>  	struct reset_control	   *sata_cold_rst;
> @@ -181,6 +187,18 @@ struct tegra_ahci_priv {
>  	struct tegra_ahci_soc	   *soc_data;
>  };
>  
> +static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
> +{
> +	struct tegra_ahci_priv *tegra = hpriv->plat_data;
> +	u32 val;
> +
> +	if (tegra->sata_aux_regs && (tegra->soc_data->quirks & NO_DEVSLP)) {

And then this becomes:

	if (tegra->sata_aux_regs && !tegra->soc->supports_devslp)

> +		val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
> +		val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
> +		writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
> +	}
> +}
> +
>  static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
>  {
>  	struct tegra_ahci_priv *tegra = hpriv->plat_data;
> @@ -400,6 +418,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
>  	val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
>  	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>  
> +	tegra_ahci_handle_quirks(hpriv);
>  
>  	/* Unmask SATA interrupts */
>  
> @@ -441,6 +460,7 @@ static const char *const tegra124_supply_names[] = {
>  static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
>  	.supply_names = tegra124_supply_names,
>  	.num_supplies = ARRAY_SIZE(tegra124_supply_names),
> +	.quirks = NO_DEVSLP,
>  	.ops = {
>  		.init = tegra124_ahci_init,
>  	},
> @@ -485,6 +505,15 @@ static int tegra_ahci_probe(struct platform_device *pdev)
>  	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(tegra->sata_regs))
>  		return PTR_ERR(tegra->sata_regs);
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> +	/*
> +	 * Aux register is optional.
> +	 */

"Aux register" -> "AUX registers". Also, I think it's more idiomatic to
place the comment above platform_get_resource() so that the assignment
and the check below are not separated.

Thierry

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[PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

This adds bindings documentation for the
AHCI controller on Tegra210

Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
v7:
* For Aux register set drop the Tegra210 since this register
  set also works on Tegra124
* rephrase the sentence for cml1 clock
* change the commit subject to include ahci-tegra
* drop pll_e since CCF handles it automatically as
  CML1 is a child clock of it.
v4:
* changed the commit message
* changed 'sata-cold' reset to mandatory for t210 and t124
* Removed the regulators for T210 since these regulators
  will be enabled in phy driver.
v3:
* Add AUX register.
v2:
* change cml1, pll_e and phy regulators as optional
  for T210.
---
 .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3e8915..0f4520a00716 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,20 +1,19 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
 
 Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,
-  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
-  is tegra132.
-- reg : Should contain 2 entries:
+- compatible : Must be one of:
+  - Tegra124 : "nvidia,tegra124-ahci"
+  - Tegra210 : "nvidia,tegra210-ahci"
+- reg : Should contain 3 entries:
   - AHCI register set (SATA BAR5)
   - SATA register set
+  - AUX register set
 - interrupts : Defines the interrupt used by SATA
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - sata
   - sata-oob
-  - cml1
-  - pll_e
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
@@ -24,9 +23,19 @@ Required properties :
 - phys : Must contain an entry for each entry in phy-names.
   See ../phy/phy-bindings.txt for details.
 - phy-names : Must include the following entries:
-  - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+  - For T124:
+    - sata-phy : XUSB PADCTL SATA PHY
+  - For T210:
+    - sata-0
+- For T124:
+  - hvdd-supply : Defines the SATA HVDD regulator
+  - vddio-supply : Defines the SATA VDDIO regulator
+  - avdd-supply : Defines the SATA AVDD regulator
+  - target-5v-supply : Defines the SATA 5V power regulator
+  - target-12v-supply : Defines the SATA 12V power regulator
+
+Optional properties:
+- clock-names :
+  - cml1 :
+    cml1 clock should be defined here if the PHY driver
+    doesn't manage them. If it does, they should not be.
-- 
2.7.4

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Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Rob Herring]

On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> This adds bindings documentation for the
> AHCI controller on Tegra210
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
> v7:
> * For Aux register set drop the Tegra210 since this register
>   set also works on Tegra124
> * rephrase the sentence for cml1 clock
> * change the commit subject to include ahci-tegra
> * drop pll_e since CCF handles it automatically as
>   CML1 is a child clock of it.
> v4:
> * changed the commit message
> * changed 'sata-cold' reset to mandatory for t210 and t124
> * Removed the regulators for T210 since these regulators
>   will be enabled in phy driver.
> v3:
> * Add AUX register.
> v2:
> * change cml1, pll_e and phy regulators as optional
>   for T210.
> ---
>  .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
>  1 file changed, 22 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> index 66c83c3e8915..0f4520a00716 100644
> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> @@ -1,20 +1,19 @@
> -Tegra124 SoC SATA AHCI controller
> +Tegra SoC SATA AHCI controller
>  
>  Required properties :
> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,
> -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
> -  is tegra132.
> -- reg : Should contain 2 entries:
> +- compatible : Must be one of:
> +  - Tegra124 : "nvidia,tegra124-ahci"
> +  - Tegra210 : "nvidia,tegra210-ahci"

Are you dropping T132?

> +- reg : Should contain 3 entries:

You can't just add more entries to existing compatibles. Does this apply 
to T124?

>    - AHCI register set (SATA BAR5)
>    - SATA register set
> +  - AUX register set
>  - interrupts : Defines the interrupt used by SATA
>  - clocks : Must contain an entry for each entry in clock-names.
>    See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    - sata
>    - sata-oob
> -  - cml1
> -  - pll_e
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
> @@ -24,9 +23,19 @@ Required properties :
>  - phys : Must contain an entry for each entry in phy-names.
>    See ../phy/phy-bindings.txt for details.
>  - phy-names : Must include the following entries:
> -  - sata-phy : XUSB PADCTL SATA PHY
> -- hvdd-supply : Defines the SATA HVDD regulator
> -- vddio-supply : Defines the SATA VDDIO regulator
> -- avdd-supply : Defines the SATA AVDD regulator
> -- target-5v-supply : Defines the SATA 5V power regulator
> -- target-12v-supply : Defines the SATA 12V power regulator
> +  - For T124:
> +    - sata-phy : XUSB PADCTL SATA PHY
> +  - For T210:
> +    - sata-0

-names is kind of pointless for a single entry. Differing names is even 
more pointless.

> +- For T124:
> +  - hvdd-supply : Defines the SATA HVDD regulator
> +  - vddio-supply : Defines the SATA VDDIO regulator
> +  - avdd-supply : Defines the SATA AVDD regulator
> +  - target-5v-supply : Defines the SATA 5V power regulator
> +  - target-12v-supply : Defines the SATA 12V power regulator

No supplies on T210? The last 2 sound like board level supplies to the 
drive.

> +
> +Optional properties:
> +- clock-names :
> +  - cml1 :
> +    cml1 clock should be defined here if the PHY driver
> +    doesn't manage them. If it does, they should not be.
> -- 
> 2.7.4
> 

Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Thierry Reding]

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On Sun, Feb 18, 2018 at 08:46:35PM -0600, Rob Herring wrote:
> On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra wrote:
> > From: Preetham Ramchandra <pchandru@nvidia.com>
> > 
> > This adds bindings documentation for the
> > AHCI controller on Tegra210
> > 
> > Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> > ---
> > v7:
> > * For Aux register set drop the Tegra210 since this register
> >   set also works on Tegra124
> > * rephrase the sentence for cml1 clock
> > * change the commit subject to include ahci-tegra
> > * drop pll_e since CCF handles it automatically as
> >   CML1 is a child clock of it.
> > v4:
> > * changed the commit message
> > * changed 'sata-cold' reset to mandatory for t210 and t124
> > * Removed the regulators for T210 since these regulators
> >   will be enabled in phy driver.
> > v3:
> > * Add AUX register.
> > v2:
> > * change cml1, pll_e and phy regulators as optional
> >   for T210.
> > ---
> >  .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
> >  1 file changed, 22 insertions(+), 13 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > index 66c83c3e8915..0f4520a00716 100644
> > --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > @@ -1,20 +1,19 @@
> > -Tegra124 SoC SATA AHCI controller
> > +Tegra SoC SATA AHCI controller
> >  
> >  Required properties :
> > -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,
> > -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
> > -  is tegra132.
> > -- reg : Should contain 2 entries:
> > +- compatible : Must be one of:
> > +  - Tegra124 : "nvidia,tegra124-ahci"
> > +  - Tegra210 : "nvidia,tegra210-ahci"
> 
> Are you dropping T132?

Tegra132 is identical to Tegra124 except for the CPU cores. That said,
we've erred on the side of caution in the past and required that the
compatible properties for Tegra132 contain both "nvidia,tegra132-*" and
"nvidia,tegra124-*". The reason was that we'd get support from drivers
that support Tegra124 automatically while at the same time having a chip
specific compatible string that would allow us to add Tegra132 specific
quirks should there be any.

So I think it'd be best if AHCI followed that and we add an entry for
Tegra132 here:

  - Tegra132: "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"

Thierry

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Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Thierry Reding]

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On Sun, Feb 18, 2018 at 08:46:35PM -0600, Rob Herring wrote:
> On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra wrote:
> > From: Preetham Ramchandra <pchandru@nvidia.com>
> > 
> > This adds bindings documentation for the
> > AHCI controller on Tegra210
> > 
> > Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> > ---
> > v7:
> > * For Aux register set drop the Tegra210 since this register
> >   set also works on Tegra124
> > * rephrase the sentence for cml1 clock
> > * change the commit subject to include ahci-tegra
> > * drop pll_e since CCF handles it automatically as
> >   CML1 is a child clock of it.
> > v4:
> > * changed the commit message
> > * changed 'sata-cold' reset to mandatory for t210 and t124
> > * Removed the regulators for T210 since these regulators
> >   will be enabled in phy driver.
> > v3:
> > * Add AUX register.
> > v2:
> > * change cml1, pll_e and phy regulators as optional
> >   for T210.
> > ---
> >  .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
> >  1 file changed, 22 insertions(+), 13 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > index 66c83c3e8915..0f4520a00716 100644
> > --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> > @@ -1,20 +1,19 @@
> > -Tegra124 SoC SATA AHCI controller
> > +Tegra SoC SATA AHCI controller
> >  
> >  Required properties :
> > -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,
> > -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
> > -  is tegra132.
> > -- reg : Should contain 2 entries:
> > +- compatible : Must be one of:
> > +  - Tegra124 : "nvidia,tegra124-ahci"
> > +  - Tegra210 : "nvidia,tegra210-ahci"
> 
> Are you dropping T132?
> 
> > +- reg : Should contain 3 entries:
> 
> You can't just add more entries to existing compatibles. Does this apply 
> to T124?

I'd consider this a bug in existing DTSs. The SATA AUX registers exist
as far back as Tegra30. The reason why they were never included in the
DTS in because the driver never programmed those registers.

However, the driver change in patch 5/7 which uses this has a comment
that AUX registers are optional, so perhaps we can just add that fact to
the bindings as well.

Thierry

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RE: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Preetham Chandru]

>-----Original Message-----
>From: Thierry Reding [mailto:thierry.reding@gmail.com]
>Sent: Monday, February 19, 2018 7:55 PM
>To: Rob Herring <robh@kernel.org>
>Cc: Preetham Chandru <pchandru@nvidia.com>; tj@kernel.org; cyndis@kapsi.fi;
>mark.rutland@arm.com; devicetree@vger.kernel.org; preetham260@gmail.com;
>linux-tegra@vger.kernel.org; linux-ide@vger.kernel.org; Venu Byravarasu
><vbyravarasu@nvidia.com>; Pavan Kunapuli <pkunapuli@nvidia.com>
>Subject: Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation
>
>* PGP Signed by an unknown key
>
>On Sun, Feb 18, 2018 at 08:46:35PM -0600, Rob Herring wrote:
>> On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra
>wrote:
>> > From: Preetham Ramchandra <pchandru@nvidia.com>
>> >
>> > This adds bindings documentation for the AHCI controller on Tegra210
>> >
>> > Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
>> > ---
>> > v7:
>> > * For Aux register set drop the Tegra210 since this register
>> >   set also works on Tegra124
>> > * rephrase the sentence for cml1 clock
>> > * change the commit subject to include ahci-tegra
>> > * drop pll_e since CCF handles it automatically as
>> >   CML1 is a child clock of it.
>> > v4:
>> > * changed the commit message
>> > * changed 'sata-cold' reset to mandatory for t210 and t124
>> > * Removed the regulators for T210 since these regulators
>> >   will be enabled in phy driver.
>> > v3:
>> > * Add AUX register.
>> > v2:
>> > * change cml1, pll_e and phy regulators as optional
>> >   for T210.
>> > ---
>> >  .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
>> >  1 file changed, 22 insertions(+), 13 deletions(-)
>> >
>> > diff --git
>> > a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> > b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> > index 66c83c3e8915..0f4520a00716 100644
>> > --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> > +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> > @@ -1,20 +1,19 @@
>> > -Tegra124 SoC SATA AHCI controller
>> > +Tegra SoC SATA AHCI controller
>> >
>> >  Required properties :
>> > -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".
>> > Otherwise,
>> > -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"',
>> > where <chip>
>> > -  is tegra132.
>> > -- reg : Should contain 2 entries:
>> > +- compatible : Must be one of:
>> > +  - Tegra124 : "nvidia,tegra124-ahci"
>> > +  - Tegra210 : "nvidia,tegra210-ahci"
>>
>> Are you dropping T132?
>>
>> > +- reg : Should contain 3 entries:
>>
>> You can't just add more entries to existing compatibles. Does this
>> apply to T124?
>
>I'd consider this a bug in existing DTSs. The SATA AUX registers exist as far back as
>Tegra30. The reason why they were never included in the DTS in because the
>driver never programmed those registers.
>
>However, the driver change in patch 5/7 which uses this has a comment that AUX
>registers are optional, so perhaps we can just add that fact to the bindings as
>well.
>
Okay, will make it optional

>Thierry
>
>* Unknown Key
>* 0x7F3EB3A1

RE: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Preetham Chandru]

>-----Original Message-----
>From: Rob Herring [mailto:robh@kernel.org]
>Sent: Monday, February 19, 2018 8:17 AM
>To: Preetham Chandru <pchandru@nvidia.com>
>Cc: thierry.reding@gmail.com; tj@kernel.org; cyndis@kapsi.fi;
>mark.rutland@arm.com; devicetree@vger.kernel.org; preetham260@gmail.com;
>linux-tegra@vger.kernel.org; linux-ide@vger.kernel.org; Venu Byravarasu
><vbyravarasu@nvidia.com>; Pavan Kunapuli <pkunapuli@nvidia.com>
>Subject: Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation
>
>On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra
>wrote:
>> From: Preetham Ramchandra <pchandru@nvidia.com>
>>
>> This adds bindings documentation for the AHCI controller on Tegra210
>>
>> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
>> ---
>> v7:
>> * For Aux register set drop the Tegra210 since this register
>>   set also works on Tegra124
>> * rephrase the sentence for cml1 clock
>> * change the commit subject to include ahci-tegra
>> * drop pll_e since CCF handles it automatically as
>>   CML1 is a child clock of it.
>> v4:
>> * changed the commit message
>> * changed 'sata-cold' reset to mandatory for t210 and t124
>> * Removed the regulators for T210 since these regulators
>>   will be enabled in phy driver.
>> v3:
>> * Add AUX register.
>> v2:
>> * change cml1, pll_e and phy regulators as optional
>>   for T210.
>> ---
>>  .../bindings/ata/nvidia,tegra124-ahci.txt          | 35 ++++++++++++++--------
>>  1 file changed, 22 insertions(+), 13 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> index 66c83c3e8915..0f4520a00716 100644
>> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> @@ -1,20 +1,19 @@
>> -Tegra124 SoC SATA AHCI controller
>> +Tegra SoC SATA AHCI controller
>>
>>  Required properties :
>> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".
>> Otherwise,
>> -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where
>> <chip>
>> -  is tegra132.
>> -- reg : Should contain 2 entries:
>> +- compatible : Must be one of:
>> +  - Tegra124 : "nvidia,tegra124-ahci"
>> +  - Tegra210 : "nvidia,tegra210-ahci"
>
>Are you dropping T132?
>
Okay will add.

>> +- reg : Should contain 3 entries:
>
>You can't just add more entries to existing compatibles. Does this apply to T124?
>
Will keep this as per Thierry's suggestion.

>>    - AHCI register set (SATA BAR5)
>>    - SATA register set
>> +  - AUX register set
>>  - interrupts : Defines the interrupt used by SATA
>>  - clocks : Must contain an entry for each entry in clock-names.
>>    See ../clocks/clock-bindings.txt for details.
>>  - clock-names : Must include the following entries:
>>    - sata
>>    - sata-oob
>> -  - cml1
>> -  - pll_e
>>  - resets : Must contain an entry for each entry in reset-names.
>>    See ../reset/reset.txt for details.
>>  - reset-names : Must include the following entries:
>> @@ -24,9 +23,19 @@ Required properties :
>>  - phys : Must contain an entry for each entry in phy-names.
>>    See ../phy/phy-bindings.txt for details.
>>  - phy-names : Must include the following entries:
>> -  - sata-phy : XUSB PADCTL SATA PHY
>> -- hvdd-supply : Defines the SATA HVDD regulator
>> -- vddio-supply : Defines the SATA VDDIO regulator
>> -- avdd-supply : Defines the SATA AVDD regulator
>> -- target-5v-supply : Defines the SATA 5V power regulator
>> -- target-12v-supply : Defines the SATA 12V power regulator
>> +  - For T124:
>> +    - sata-phy : XUSB PADCTL SATA PHY
>> +  - For T210:
>> +    - sata-0
>
>-names is kind of pointless for a single entry. Differing names is even more
>pointless.
>
Okay, will keep the name same as Tegra124 and move this to optional for T210 alone . Will not try to change the t124 part to optional since it is already present.

>> +- For T124:
>> +  - hvdd-supply : Defines the SATA HVDD regulator
>> +  - vddio-supply : Defines the SATA VDDIO regulator
>> +  - avdd-supply : Defines the SATA AVDD regulator
>> +  - target-5v-supply : Defines the SATA 5V power regulator
>> +  - target-12v-supply : Defines the SATA 12V power regulator
>
>No supplies on T210? The last 2 sound like board level supplies to the drive.
>
This first 3 are related to phy and will be taken care by uphy driver for t210 and the last two are going to the SATA connectors. These two are always on for tegra210.
>> +
>> +Optional properties:
>> +- clock-names :
>> +  - cml1 :
>> +    cml1 clock should be defined here if the PHY driver
>> +    doesn't manage them. If it does, they should not be.
>> --
>> 2.7.4
>>

Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> This adds bindings documentation for the
> AHCI controller on Tegra210

Please avoid lines that are too short. They shouldn't exceed 72
characters, but you're supposed to make fully use of those. Also the
above is a sentence, so should end with a '.'.

> diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> index 66c83c3e8915..0f4520a00716 100644
> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> @@ -1,20 +1,19 @@
> -Tegra124 SoC SATA AHCI controller
> +Tegra SoC SATA AHCI controller
>  
>  Required properties :
> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,
> -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
> -  is tegra132.
> -- reg : Should contain 2 entries:
> +- compatible : Must be one of:
> +  - Tegra124 : "nvidia,tegra124-ahci"
> +  - Tegra210 : "nvidia,tegra210-ahci"
> +- reg : Should contain 3 entries:
>    - AHCI register set (SATA BAR5)
>    - SATA register set
> +  - AUX register set
>  - interrupts : Defines the interrupt used by SATA
>  - clocks : Must contain an entry for each entry in clock-names.
>    See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    - sata
>    - sata-oob
> -  - cml1
> -  - pll_e
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
> @@ -24,9 +23,19 @@ Required properties :
>  - phys : Must contain an entry for each entry in phy-names.
>    See ../phy/phy-bindings.txt for details.
>  - phy-names : Must include the following entries:
> -  - sata-phy : XUSB PADCTL SATA PHY
> -- hvdd-supply : Defines the SATA HVDD regulator
> -- vddio-supply : Defines the SATA VDDIO regulator
> -- avdd-supply : Defines the SATA AVDD regulator
> -- target-5v-supply : Defines the SATA 5V power regulator
> -- target-12v-supply : Defines the SATA 12V power regulator
> +  - For T124:
> +    - sata-phy : XUSB PADCTL SATA PHY
> +  - For T210:
> +    - sata-0
> +- For T124:

Can we please use TegraXYZ here? I find it useful to be consistent here
because those will show up if I grep for "tegra", whereas TXYZ won't.

Thierry

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RE: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Preetham Chandru]

>-----Original Message-----
>From: Thierry Reding [mailto:thierry.reding@gmail.com]
>Sent: Monday, February 19, 2018 7:58 PM
>To: Preetham Chandru <pchandru@nvidia.com>
>Cc: tj@kernel.org; cyndis@kapsi.fi; robh+dt@kernel.org;
>mark.rutland@arm.com; devicetree@vger.kernel.org; preetham260@gmail.com;
>linux-tegra@vger.kernel.org; linux-ide@vger.kernel.org; Venu Byravarasu
><vbyravarasu@nvidia.com>; Pavan Kunapuli <pkunapuli@nvidia.com>
>Subject: Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation
>
>On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra
>wrote:
>> From: Preetham Ramchandra <pchandru@nvidia.com>
>>
>> This adds bindings documentation for the AHCI controller on Tegra210
>
>Please avoid lines that are too short. They shouldn't exceed 72 characters, but
>you're supposed to make fully use of those. Also the above is a sentence, so
>should end with a '.'.
>
okay
>> diff --git
>> a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> index 66c83c3e8915..0f4520a00716 100644
>> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> @@ -1,20 +1,19 @@
>> -Tegra124 SoC SATA AHCI controller
>> +Tegra SoC SATA AHCI controller
>>
>>  Required properties :
>> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".
>> Otherwise,
>> -  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where
>> <chip>
>> -  is tegra132.
>> -- reg : Should contain 2 entries:
>> +- compatible : Must be one of:
>> +  - Tegra124 : "nvidia,tegra124-ahci"
>> +  - Tegra210 : "nvidia,tegra210-ahci"
>> +- reg : Should contain 3 entries:
>>    - AHCI register set (SATA BAR5)
>>    - SATA register set
>> +  - AUX register set
>>  - interrupts : Defines the interrupt used by SATA
>>  - clocks : Must contain an entry for each entry in clock-names.
>>    See ../clocks/clock-bindings.txt for details.
>>  - clock-names : Must include the following entries:
>>    - sata
>>    - sata-oob
>> -  - cml1
>> -  - pll_e
>>  - resets : Must contain an entry for each entry in reset-names.
>>    See ../reset/reset.txt for details.
>>  - reset-names : Must include the following entries:
>> @@ -24,9 +23,19 @@ Required properties :
>>  - phys : Must contain an entry for each entry in phy-names.
>>    See ../phy/phy-bindings.txt for details.
>>  - phy-names : Must include the following entries:
>> -  - sata-phy : XUSB PADCTL SATA PHY
>> -- hvdd-supply : Defines the SATA HVDD regulator
>> -- vddio-supply : Defines the SATA VDDIO regulator
>> -- avdd-supply : Defines the SATA AVDD regulator
>> -- target-5v-supply : Defines the SATA 5V power regulator
>> -- target-12v-supply : Defines the SATA 12V power regulator
>> +  - For T124:
>> +    - sata-phy : XUSB PADCTL SATA PHY
>> +  - For T210:
>> +    - sata-0
>> +- For T124:
>
>Can we please use TegraXYZ here? I find it useful to be consistent here because
>those will show up if I grep for "tegra", whereas TXYZ won't.
>
okay
>Thierry

Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> This adds bindings documentation for the
> AHCI controller on Tegra210
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>

Oh, and you might want to mention Tegra210 in the patch subject.

Thierry

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RE: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation

[Preetham Chandru]

>-----Original Message-----
>From: Thierry Reding [mailto:thierry.reding@gmail.com]
>Sent: Monday, February 19, 2018 7:58 PM
>To: Preetham Chandru <pchandru@nvidia.com>
>Cc: tj@kernel.org; cyndis@kapsi.fi; robh+dt@kernel.org;
>mark.rutland@arm.com; devicetree@vger.kernel.org; preetham260@gmail.com;
>linux-tegra@vger.kernel.org; linux-ide@vger.kernel.org; Venu Byravarasu
><vbyravarasu@nvidia.com>; Pavan Kunapuli <pkunapuli@nvidia.com>
>Subject: Re: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation
>
>On Mon, Feb 12, 2018 at 10:56:40PM +0530, Preetham Chandru Ramchandra
>wrote:
>> From: Preetham Ramchandra <pchandru@nvidia.com>
>>
>> This adds bindings documentation for the AHCI controller on Tegra210
>>
>> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
>
>Oh, and you might want to mention Tegra210 in the patch subject.
>
okay
>Thierry

[PATCH V7 2/7] arm64: tegra: Enable AHCI on Jetson TX1

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add sata node to the Tegra210 device tree, and
enable the device and assign board-specific
properties on Jetson TX1.
Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
v7:
* Change commit message to reflect accordingly
v4:
* Fixed missing space after 'AUX'
---
 arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi |  6 ++++++
 arch/arm64/boot/dts/nvidia/tegra210.dtsi       | 16 ++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index d67ef4319f3b..2aa2979cd6b5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1325,6 +1325,12 @@
 		status = "okay";
 	};
 
+	sata@70020000 {
+		status = "okay";
+		phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+		phy-names = "sata-0";
+	};
+
 	padctl@7009f000 {
 		status = "okay";
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 9c2402108772..bf72db5386a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -798,6 +798,22 @@
 		#iommu-cells = <1>;
 	};
 
+	sata@70020000 {
+		compatible = "nvidia,tegra210-ahci";
+		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+		      <0x0 0x70020000 0x0 0x7000>, /* SATA */
+		      <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_SATA>,
+			<&tegra_car TEGRA210_CLK_SATA_OOB>;
+		clock-names = "sata", "sata-oob";
+		resets = <&tegra_car 124>,
+			 <&tegra_car 123>,
+			 <&tegra_car 129>;
+		reset-names = "sata", "sata-oob", "sata-cold";
+		status = "disabled";
+	};
+
 	hda@70030000 {
 		compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
 		reg = <0x0 0x70030000 0x0 0x10000>;
-- 
2.7.4

Re: [PATCH V7 2/7] arm64: tegra: Enable AHCI on Jetson TX1

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2094 bytes --]

On Mon, Feb 12, 2018 at 10:56:41PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> Add sata node to the Tegra210 device tree, and
> enable the device and assign board-specific
> properties on Jetson TX1.
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>

Tags such as Signed-off-by: should be in a separate paragraph, so the
above is missing a blank line before the Signed-off-by:.

> ---
> v7:
> * Change commit message to reflect accordingly
> v4:
> * Fixed missing space after 'AUX'
> ---
>  arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi |  6 ++++++
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi       | 16 ++++++++++++++++
>  2 files changed, 22 insertions(+)

I prefer these to be two separate patches, one for the SoC .dtsi and
another for the P2597 carrier.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
> index d67ef4319f3b..2aa2979cd6b5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
> @@ -1325,6 +1325,12 @@
>  		status = "okay";
>  	};
>  
> +	sata@70020000 {
> +		status = "okay";
> +		phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
> +		phy-names = "sata-0";
> +	};
> +
>  	padctl@7009f000 {
>  		status = "okay";
>  
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 9c2402108772..bf72db5386a5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -798,6 +798,22 @@
>  		#iommu-cells = <1>;
>  	};
>  
> +	sata@70020000 {
> +		compatible = "nvidia,tegra210-ahci";
> +		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
> +		      <0x0 0x70020000 0x0 0x7000>, /* SATA */
> +		      <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
> +		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA210_CLK_SATA>,
> +			<&tegra_car TEGRA210_CLK_SATA_OOB>;

Nit: these are not properly aligned.

Thierry

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[PATCH V7 3/7] ata: ahci_tegra: Update initialization sequence

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Update the controller initialization sequence and move
t124 specifics to tegra124_ahci_init.

Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
v7:
* moveed tegra124_ahci_soc_data definition to be
  just above the of_device_id table.
---
 drivers/ata/ahci_tegra.c | 288 ++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 223 insertions(+), 65 deletions(-)

diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 3a62eb246d80..7ffe8a97447a 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -34,7 +34,8 @@
 #define DRV_NAME "tegra-ahci"
 
 #define SATA_CONFIGURATION_0				0x180
-#define SATA_CONFIGURATION_EN_FPCI			BIT(0)
+#define SATA_CONFIGURATION_0_EN_FPCI			BIT(0)
+#define SATA_CONFIGURATION_0_CLK_OVERRIDE			BIT(31)
 
 #define SCFG_OFFSET					0x1000
 
@@ -45,17 +46,55 @@
 #define T_SATA0_CFG_1_SERR				BIT(8)
 
 #define T_SATA0_CFG_9					0x24
-#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT		13
+#define T_SATA0_CFG_9_BASE_ADDRESS			0x40020000
 
 #define SATA_FPCI_BAR5					0x94
-#define SATA_FPCI_BAR5_START_SHIFT			4
+#define SATA_FPCI_BAR5_START_MASK			(0xfffffff << 4)
+#define SATA_FPCI_BAR5_START				(0x0040020 << 4)
+#define SATA_FPCI_BAR5_ACCESS_TYPE			(0x1)
 
 #define SATA_INTR_MASK					0x188
 #define SATA_INTR_MASK_IP_INT_MASK			BIT(16)
 
+#define T_SATA0_CFG_35					0x94
+#define T_SATA0_CFG_35_IDP_INDEX_MASK			(0x7ff << 2)
+#define T_SATA0_CFG_35_IDP_INDEX			(0x2a << 2)
+
+#define T_SATA0_AHCI_IDP1				0x98
+#define T_SATA0_AHCI_IDP1_DATA				(0x400040)
+
+#define T_SATA0_CFG_PHY_1				0x12c
+#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN			BIT(23)
+#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN		BIT(22)
+
+#define T_SATA0_NVOOB                                   0x114
+#define T_SATA0_NVOOB_COMMA_CNT_MASK                    (0xff << 16)
+#define T_SATA0_NVOOB_COMMA_CNT                         (0x07 << 16)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK          (0x3 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE               (0x1 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK        (0x3 << 26)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH             (0x3 << 26)
+
+#define T_SATA_CFG_PHY_0                                0x120
+#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD     BIT(11)
+#define T_SATA_CFG_PHY_0_MASK_SQUELCH                   BIT(24)
+
+#define T_SATA0_CFG2NVOOB_2				0x134
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK	(0x1ff << 18)
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW	(0xc << 18)
+
 #define T_SATA0_AHCI_HBA_CAP_BKDR			0x300
+#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP	BIT(13)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP	BIT(14)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP			BIT(26)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM		BIT(17)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ			BIT(30)
 
 #define T_SATA0_BKDOOR_CC				0x4a4
+#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK		(0xffff << 16)
+#define T_SATA0_BKDOOR_CC_CLASS_CODE			(0x0106 << 16)
+#define T_SATA0_BKDOOR_CC_PROG_IF_MASK			(0xff << 8)
+#define T_SATA0_BKDOOR_CC_PROG_IF			(0x01 << 8)
 
 #define T_SATA0_CFG_SATA				0x54c
 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN		BIT(12)
@@ -82,6 +121,27 @@
 #define T_SATA0_CHX_PHY_CTRL11				0x6d0
 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ		(0x2800 << 16)
 
+#define T_SATA0_CHX_PHY_CTRL17_0			0x6e8
+#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1	0x55010000
+#define T_SATA0_CHX_PHY_CTRL18_0			0x6ec
+#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2	0x55010000
+#define T_SATA0_CHX_PHY_CTRL20_0			0x6f4
+#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1	0x1
+#define T_SATA0_CHX_PHY_CTRL21_0			0x6f8
+#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2	0x1
+
+/* AUX Registers */
+#define SATA_AUX_MISC_CNTL_1_0				0x8
+#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE		BIT(17)
+#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT		BIT(13)
+#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT		BIT(15)
+
+#define SATA_AUX_RX_STAT_INT_0				0xc
+#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP		BIT(7)
+
+#define SATA_AUX_SPARE_CFG0_0				0x18
+#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID	BIT(14)
+
 #define FUSE_SATA_CALIB					0x124
 #define FUSE_SATA_CALIB_MASK				0x3
 
@@ -99,6 +159,14 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
 	{0x14, 0x0e, 0x1a, 0x0e},
 };
 
+struct tegra_ahci_ops {
+	int (*init)(struct ahci_host_priv *hpriv);
+};
+
+struct tegra_ahci_soc {
+	struct tegra_ahci_ops	ops;
+};
+
 struct tegra_ahci_priv {
 	struct platform_device	   *pdev;
 	void __iomem		   *sata_regs;
@@ -108,8 +176,53 @@ struct tegra_ahci_priv {
 	/* Needs special handling, cannot use ahci_platform */
 	struct clk		   *sata_clk;
 	struct regulator_bulk_data supplies[5];
+	struct tegra_ahci_soc	   *soc_data;
 };
 
+static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
+{
+	struct tegra_ahci_priv *tegra = hpriv->plat_data;
+	struct sata_pad_calibration calib;
+	int ret;
+	u32 val;
+
+	/* Pad calibration */
+	ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
+	if (ret)
+		return ret;
+
+	calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
+
+	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
+
+	val = readl(tegra->sata_regs +
+		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
+	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
+	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
+	val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
+	val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
+	writel(val, tegra->sata_regs + SCFG_OFFSET +
+	       T_SATA0_CHX_PHY_CTRL1_GEN1);
+
+	val = readl(tegra->sata_regs +
+		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
+	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
+	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
+	val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
+	val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
+	writel(val, tegra->sata_regs + SCFG_OFFSET +
+	       T_SATA0_CHX_PHY_CTRL1_GEN2);
+
+	writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
+	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
+	writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
+	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
+
+	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
+
+	return 0;
+}
+
 static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 {
 	struct tegra_ahci_priv *tegra = hpriv->plat_data;
@@ -145,7 +258,6 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 
 disable_regulators:
 	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
-
 	return ret;
 }
 
@@ -169,8 +281,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
 {
 	struct tegra_ahci_priv *tegra = hpriv->plat_data;
 	int ret;
-	unsigned int val;
-	struct sata_pad_calibration calib;
+	u32 val;
 
 	ret = tegra_ahci_power_on(hpriv);
 	if (ret) {
@@ -179,78 +290,114 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
 		return ret;
 	}
 
+	/*
+	 * Program the following SATA IPFS registers
+	 * to allow SW accesses to SATA's MMIO register range.
+	 */
+	val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
+	val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
+	val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
+	writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
+
+	/* Program the following SATA IPFS register to enable the SATA */
 	val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
-	val |= SATA_CONFIGURATION_EN_FPCI;
+	val |= SATA_CONFIGURATION_0_EN_FPCI;
 	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
 
-	/* Pad calibration */
-
-	ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
-	if (ret) {
-		dev_err(&tegra->pdev->dev,
-			"failed to read calibration fuse: %d\n", ret);
-		return ret;
-	}
-
-	calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
-
-	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
-	val = readl(tegra->sata_regs +
-		SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
-	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
-	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
-	val |= calib.gen1_tx_amp <<
-			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
-	val |= calib.gen1_tx_peak <<
-			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
-	writel(val, tegra->sata_regs + SCFG_OFFSET +
-		T_SATA0_CHX_PHY_CTRL1_GEN1);
-
-	val = readl(tegra->sata_regs +
-			SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
-	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
-	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
-	val |= calib.gen2_tx_amp <<
-			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
-	val |= calib.gen2_tx_peak <<
-			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
-	writel(val, tegra->sata_regs + SCFG_OFFSET +
-		T_SATA0_CHX_PHY_CTRL1_GEN2);
-
-	writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
-		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
-	writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
-		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
-
-	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
-	/* Program controller device ID */
+	/* Electrical settings for better link stability */
+	val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
+	val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
+	val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
+	val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
+
+	/* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
+
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
+	val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
+	val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
+
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
+	val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
+		 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
+		 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
+	val |= (T_SATA0_NVOOB_COMMA_CNT |
+		T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
+		T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
+
+	/*
+	 * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
+	 */
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
+	val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
+	val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
+
+	if (tegra->soc_data->ops.init)
+		tegra->soc_data->ops.init(hpriv);
+
+	/*
+	 * Program the following SATA configuration registers
+	 * to initialize SATA
+	 */
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
+	val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
+		T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
+	val = T_SATA0_CFG_9_BASE_ADDRESS;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
 
+	/* Program Class Code and Programming interface for SATA */
 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 	val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 
-	writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
+	val &=
+	    ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
+	      T_SATA0_BKDOOR_CC_PROG_IF_MASK);
+	val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
 
 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 	val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 
-	/* Enable IO & memory access, bus master mode */
-
-	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
-	val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
-		T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
-	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
-
-	/* Program SATA MMIO */
-
-	writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
-	       tegra->sata_regs + SATA_FPCI_BAR5);
+	/* Enabling LPM capabilities through Backdoor Programming */
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
+	val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
+		T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
+		T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
+		T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
+
+	/* SATA Second Level Clock Gating configuration
+	 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
+	 * IDDQ Signals
+	 */
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
+	val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
+	val |= T_SATA0_CFG_35_IDP_INDEX;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
+
+	val = T_SATA0_AHCI_IDP1_DATA;
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
+
+	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
+	val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
+		T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
+	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
+
+	/* Enabling IPFS Clock Gating */
+	val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
+	val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
+	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
 
-	writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
-	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
 
 	/* Unmask SATA interrupts */
 
@@ -285,8 +432,17 @@ static const struct ata_port_info ahci_tegra_port_info = {
 	.port_ops	= &ahci_tegra_port_ops,
 };
 
+static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
+	.ops = {
+		.init = tegra124_ahci_init,
+	},
+};
+
 static const struct of_device_id tegra_ahci_of_match[] = {
-	{ .compatible = "nvidia,tegra124-ahci" },
+	{
+		.compatible = "nvidia,tegra124-ahci",
+		.data = &tegra124_ahci_soc_data
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -313,6 +469,8 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 	hpriv->plat_data = tegra;
 
 	tegra->pdev = pdev;
+	tegra->soc_data =
+	    (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
-- 
2.7.4

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Re: [PATCH V7 3/7] ata: ahci_tegra: Update initialization sequence

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:42PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> Update the controller initialization sequence and move
> t124 specifics to tegra124_ahci_init.
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
> v7:
> * moveed tegra124_ahci_soc_data definition to be
>   just above the of_device_id table.
> ---
>  drivers/ata/ahci_tegra.c | 288 ++++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 223 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index 3a62eb246d80..7ffe8a97447a 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
[...]
> @@ -99,6 +159,14 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
>  	{0x14, 0x0e, 0x1a, 0x0e},
>  };
>  
> +struct tegra_ahci_ops {
> +	int (*init)(struct ahci_host_priv *hpriv);
> +};
> +
> +struct tegra_ahci_soc {
> +	struct tegra_ahci_ops	ops;
> +};
> +
>  struct tegra_ahci_priv {
>  	struct platform_device	   *pdev;
>  	void __iomem		   *sata_regs;
> @@ -108,8 +176,53 @@ struct tegra_ahci_priv {
>  	/* Needs special handling, cannot use ahci_platform */
>  	struct clk		   *sata_clk;
>  	struct regulator_bulk_data supplies[5];
> +	struct tegra_ahci_soc	   *soc_data;

This should be const. I also think the _data suffix is unnecessary.

> @@ -145,7 +258,6 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
>  
>  disable_regulators:
>  	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
> -
>  	return ret;
>  }

Unneeded whitespace change.

> @@ -179,78 +290,114 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
>  		return ret;
>  	}
>  
> +	/*
> +	 * Program the following SATA IPFS registers
> +	 * to allow SW accesses to SATA's MMIO register range.
> +	 */

You can also use the full width of a line for comments. No need to wrap
at arbitrary points.

> @@ -285,8 +432,17 @@ static const struct ata_port_info ahci_tegra_port_info = {
>  	.port_ops	= &ahci_tegra_port_ops,
>  };
>  
> +static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
> +	.ops = {
> +		.init = tegra124_ahci_init,
> +	},
> +};
> +

Again, I don't think there's a need for _data. Also, you've made this
const, so tegra->soc(_data) should also be const. One rule of thumb is
that if you have const in one place, then you need to make it const
everywhere.

>  static const struct of_device_id tegra_ahci_of_match[] = {
> -	{ .compatible = "nvidia,tegra124-ahci" },
> +	{
> +		.compatible = "nvidia,tegra124-ahci",
> +		.data = &tegra124_ahci_soc_data
> +	},
>  	{}
>  };

of_device_id.data is const as well, which is why this compiles properly.

>  MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
> @@ -313,6 +469,8 @@ static int tegra_ahci_probe(struct platform_device *pdev)
>  	hpriv->plat_data = tegra;
>  
>  	tegra->pdev = pdev;
> +	tegra->soc_data =
> +	    (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);

And if you make tegra->soc(_data) const, then there's no need for this
cast, you can simply assign directly:

	tegra->soc = of_device_get_match_data(&pdev->dev);

void * will be automatically cast to any other pointer. The only reason
why you need the cast above is to avoid the compiler from warning about
the const qualifier being cast away.

Once const, always const.

Thierry

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Re: [PATCH V7 3/7] ata: ahci_tegra: Update initialization sequence

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:42PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> Update the controller initialization sequence and move
> t124 specifics to tegra124_ahci_init.
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
> v7:
> * moveed tegra124_ahci_soc_data definition to be
>   just above the of_device_id table.
> ---
>  drivers/ata/ahci_tegra.c | 288 ++++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 223 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index 3a62eb246d80..7ffe8a97447a 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
[...]
> @@ -99,6 +159,14 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
>  	{0x14, 0x0e, 0x1a, 0x0e},
>  };
>  
> +struct tegra_ahci_ops {
> +	int (*init)(struct ahci_host_priv *hpriv);
> +};
> +
> +struct tegra_ahci_soc {
> +	struct tegra_ahci_ops	ops;
> +};

Just noticed this: it's slightly more customary to make ops a pointer to
a function table, like so:

	struct tegra_ahci_soc {
		const struct tegra_ahci_ops *ops;
	};

and then have:

	static const struct tegra_ahci_ops tegra124_ahci_ops = {
		.init = tegra124_ahci_init,
	};

	static const struct tegra_ahci_soc tegra124_ahci_soc = {
		.ops = &tegra124_ahci_ops,
	};

That's not terribly useful in this case because the ops are not passed
around or shared between multiple instances, so there are no benefits.
Either way is fine here, I guess.

Thierry

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[PATCH V7 6/7] ata: ahci_tegra: disable DIPM

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

tegra does not support DIPM and it should be disabled

Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/ata/ahci_tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 62f2afb54789..ffad5c61e991 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -447,7 +447,7 @@ static struct ata_port_operations ahci_tegra_port_ops = {
 };
 
 static const struct ata_port_info ahci_tegra_port_info = {
-	.flags		= AHCI_FLAG_COMMON,
+	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 	.pio_mask	= ATA_PIO4,
 	.udma_mask	= ATA_UDMA6,
 	.port_ops	= &ahci_tegra_port_ops,
-- 
2.7.4

Re: [PATCH V7 6/7] ata: ahci_tegra: disable DIPM

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:45PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> tegra does not support DIPM and it should be disabled

"Tegra" and finish with a '.'.

Other than that:

Acked-by: Thierry Reding <treding@nvidia.com>

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[PATCH V7 7/7] ata: ahci_tegra: Add AHCI support for Tegra210

[Preetham Chandru Ramchandra]

From: Preetham Ramchandra <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add support for the AHCI-compliant Serial ATA host
controller on the Tegra210 system-on-chip.

Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
v7:
* Added commit message
---
 drivers/ata/ahci_tegra.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index ffad5c61e991..4524755b9b23 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -466,11 +466,19 @@ static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
 	},
 };
 
+static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
+	.quirks = NO_DEVSLP,
+};
+
 static const struct of_device_id tegra_ahci_of_match[] = {
 	{
 		.compatible = "nvidia,tegra124-ahci",
 		.data = &tegra124_ahci_soc_data
 	},
+	{
+		.compatible = "nvidia,tegra210-ahci",
+		.data = &tegra210_ahci_soc_data
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -585,5 +593,5 @@ static struct platform_driver tegra_ahci_driver = {
 module_platform_driver(tegra_ahci_driver);
 
 MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
-MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
+MODULE_DESCRIPTION("Tegra AHCI SATA driver");
 MODULE_LICENSE("GPL v2");
-- 
2.7.4

Re: [PATCH V7 7/7] ata: ahci_tegra: Add AHCI support for Tegra210

[Thierry Reding]

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On Mon, Feb 12, 2018 at 10:56:46PM +0530, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
> 
> Add support for the AHCI-compliant Serial ATA host
> controller on the Tegra210 system-on-chip.
> 
> Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
> ---
> v7:
> * Added commit message
> ---
>  drivers/ata/ahci_tegra.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index ffad5c61e991..4524755b9b23 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
> @@ -466,11 +466,19 @@ static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
>  	},
>  };
>  
> +static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
> +	.quirks = NO_DEVSLP,
> +};
> +
>  static const struct of_device_id tegra_ahci_of_match[] = {
>  	{
>  		.compatible = "nvidia,tegra124-ahci",
>  		.data = &tegra124_ahci_soc_data
>  	},
> +	{
> +		.compatible = "nvidia,tegra210-ahci",
> +		.data = &tegra210_ahci_soc_data
> +	},
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
> @@ -585,5 +593,5 @@ static struct platform_driver tegra_ahci_driver = {
>  module_platform_driver(tegra_ahci_driver);
>  
>  MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
> -MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
> +MODULE_DESCRIPTION("Tegra AHCI SATA driver");
>  MODULE_LICENSE("GPL v2");

I think you should also update the Kconfig file to clarify that this is
no longer Tegra124-only.

With that:

Acked-by: Thierry Reding <treding@nvidia.com>

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Re: [PATCH V7 0/7] Refactor and add AHCI support for tegra210

[Mikko Perttunen]

I think this now looks good enough to merge - others please take a look 
as well.

Series,
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

On 12.02.2018 19:26, Preetham Chandru Ramchandra wrote:
> From: Preetham Ramchandra <pchandru@nvidia.com>
>
> 1. ADD AHCI support for tegra210
> 2. Extend the tegra AHCI controller device tree binding with tegra210
> 3. Update initialization sequence
> 4. Initialize regulators based on chip
> 5. Disable DevSlp
> 6. Disable DIPM
> ---
> Preetham Ramchandra (7):
>   dt-bindings: ahci-tegra: add binding documentation
>   arm64: tegra: Enable AHCI on Jetson TX1
>   ata: ahci_tegra: Update initialization sequence
>   ata: ahci_tegra: initialize regulators from soc_data
>   ata: ahci_tegra: disable devslp for t124
>   ata: ahci_tegra: disable DIPM
>   ata: ahci_tegra: Add AHCI support for Tegra210
>
>  .../bindings/ata/nvidia,tegra124-ahci.txt          |  35 +-
>  arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi     |   6 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  16 +
>  drivers/ata/ahci_tegra.c                           | 362 ++++++++++++++++-----
>  4 files changed, 329 insertions(+), 90 deletions(-)
>