From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Paul Cercueil <paul@crapouillou.net>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
list@opendingux.net, 周琰杰 <zhouyanjie@wanyeetech.com>,
"Paul Cercueil" <paul@crapouillou.net>
Subject: Re: [PATCH v2 4/6] clk: ingenic: Remove pll_info.no_bypass_bit
Date: Sun, 27 Jun 2021 19:49:51 -0700 [thread overview]
Message-ID: <162484859150.2516444.13611912809661364397@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210530164923.18134-5-paul@crapouillou.net>
Quoting Paul Cercueil (2021-05-30 09:49:21)
> We can express that a PLL has no bypass bit by simply setting the
> .bypass_bit field to a negative value.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
Applied to clk-next
next prev parent reply other threads:[~2021-06-28 2:49 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-30 16:49 [PATCH v2 0/6] clk: Ingenic JZ4760(B) support Paul Cercueil
2021-05-30 16:49 ` [PATCH v2 1/6] dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 2/6] clk: Support bypassing dividers Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 3/6] clk: ingenic: Read bypass register only when there is one Paul Cercueil
2021-06-01 14:08 ` Zhou Yanjie
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 4/6] clk: ingenic: Remove pll_info.no_bypass_bit Paul Cercueil
2021-06-01 14:07 ` Zhou Yanjie
2021-06-28 2:49 ` Stephen Boyd [this message]
2021-05-30 16:49 ` [PATCH v2 5/6] clk: ingenic: Support overriding PLLs M/N/OD calc algorithm Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 6/6] clk: ingenic: Add support for the JZ4760 Paul Cercueil
2021-06-28 2:50 ` Stephen Boyd
2021-06-30 12:18 ` Paul Cercueil
2021-06-22 14:48 ` [PATCH v2 0/6] clk: Ingenic JZ4760(B) support 周琰杰
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