Re: [PATCH v2 4/6] clk: ingenic: Remove pll_info.no_bypass_bit

[Zhou Yanjie <zhouyanjie@wanyeetech.com>]

On 2021/5/31 上午12:49, Paul Cercueil wrote:
> We can express that a PLL has no bypass bit by simply setting the
> .bypass_bit field to a negative value.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>   drivers/clk/ingenic/cgu.c        | 4 ++--
>   drivers/clk/ingenic/cgu.h        | 7 +++----
>   drivers/clk/ingenic/jz4770-cgu.c | 3 +--
>   3 files changed, 6 insertions(+), 8 deletions(-)


Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>    # on CU1830-neo/X1830


>
> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> index 7686072aff8f..58f7ab5cf0fe 100644
> --- a/drivers/clk/ingenic/cgu.c
> +++ b/drivers/clk/ingenic/cgu.c
> @@ -99,7 +99,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
>   	od_enc = ctl >> pll_info->od_shift;
>   	od_enc &= GENMASK(pll_info->od_bits - 1, 0);
>   
> -	if (!pll_info->no_bypass_bit) {
> +	if (pll_info->bypass_bit >= 0) {
>   		ctl = readl(cgu->base + pll_info->bypass_reg);
>   
>   		bypass = !!(ctl & BIT(pll_info->bypass_bit));
> @@ -226,7 +226,7 @@ static int ingenic_pll_enable(struct clk_hw *hw)
>   	u32 ctl;
>   
>   	spin_lock_irqsave(&cgu->lock, flags);
> -	if (!pll_info->no_bypass_bit) {
> +	if (pll_info->bypass_bit >= 0) {
>   		ctl = readl(cgu->base + pll_info->bypass_reg);
>   
>   		ctl &= ~BIT(pll_info->bypass_bit);
> diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
> index 44d97a259692..10521d1b7b12 100644
> --- a/drivers/clk/ingenic/cgu.h
> +++ b/drivers/clk/ingenic/cgu.h
> @@ -39,10 +39,10 @@
>    *               their encoded values in the PLL control register, or -1 for
>    *               unsupported values
>    * @bypass_reg: the offset of the bypass control register within the CGU
> - * @bypass_bit: the index of the bypass bit in the PLL control register
> + * @bypass_bit: the index of the bypass bit in the PLL control register, or
> + *              -1 if there is no bypass bit
>    * @enable_bit: the index of the enable bit in the PLL control register
>    * @stable_bit: the index of the stable bit in the PLL control register
> - * @no_bypass_bit: if set, the PLL has no bypass functionality
>    */
>   struct ingenic_cgu_pll_info {
>   	unsigned reg;
> @@ -52,10 +52,9 @@ struct ingenic_cgu_pll_info {
>   	u8 n_shift, n_bits, n_offset;
>   	u8 od_shift, od_bits, od_max;
>   	unsigned bypass_reg;
> -	u8 bypass_bit;
> +	s8 bypass_bit;
>   	u8 enable_bit;
>   	u8 stable_bit;
> -	bool no_bypass_bit;
>   };
>   
>   /**
> diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
> index 381a27f20b51..2321742b3471 100644
> --- a/drivers/clk/ingenic/jz4770-cgu.c
> +++ b/drivers/clk/ingenic/jz4770-cgu.c
> @@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
>   			.od_bits = 2,
>   			.od_max = 8,
>   			.od_encoding = pll_od_encoding,
> -			.bypass_reg = CGU_REG_CPPCR1,
> -			.no_bypass_bit = true,
> +			.bypass_bit = -1,
>   			.enable_bit = 7,
>   			.stable_bit = 6,
>   		},