From: Zhou Yanjie <zhouyanjie@wanyeetech.com>
To: Paul Cercueil <paul@crapouillou.net>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
list@opendingux.net
Subject: Re: [PATCH v2 3/6] clk: ingenic: Read bypass register only when there is one
Date: Tue, 1 Jun 2021 22:08:57 +0800 [thread overview]
Message-ID: <47eeb44b-2752-1c99-4209-09769e267c7f@wanyeetech.com> (raw)
In-Reply-To: <20210530164923.18134-4-paul@crapouillou.net>
On 2021/5/31 上午12:49, Paul Cercueil wrote:
> Rework the clock code so that the bypass register is only read when
> there is actually a bypass functionality.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/clk/ingenic/cgu.c | 19 +++++++++++--------
> 1 file changed, 11 insertions(+), 8 deletions(-)
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
>
> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> index 0619d45a950c..7686072aff8f 100644
> --- a/drivers/clk/ingenic/cgu.c
> +++ b/drivers/clk/ingenic/cgu.c
> @@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> od_enc = ctl >> pll_info->od_shift;
> od_enc &= GENMASK(pll_info->od_bits - 1, 0);
>
> - ctl = readl(cgu->base + pll_info->bypass_reg);
> + if (!pll_info->no_bypass_bit) {
> + ctl = readl(cgu->base + pll_info->bypass_reg);
>
> - bypass = !pll_info->no_bypass_bit &&
> - !!(ctl & BIT(pll_info->bypass_bit));
> + bypass = !!(ctl & BIT(pll_info->bypass_bit));
>
> - if (bypass)
> - return parent_rate;
> + if (bypass)
> + return parent_rate;
> + }
>
> for (od = 0; od < pll_info->od_max; od++) {
> if (pll_info->od_encoding[od] == od_enc)
> @@ -225,11 +226,13 @@ static int ingenic_pll_enable(struct clk_hw *hw)
> u32 ctl;
>
> spin_lock_irqsave(&cgu->lock, flags);
> - ctl = readl(cgu->base + pll_info->bypass_reg);
> + if (!pll_info->no_bypass_bit) {
> + ctl = readl(cgu->base + pll_info->bypass_reg);
>
> - ctl &= ~BIT(pll_info->bypass_bit);
> + ctl &= ~BIT(pll_info->bypass_bit);
>
> - writel(ctl, cgu->base + pll_info->bypass_reg);
> + writel(ctl, cgu->base + pll_info->bypass_reg);
> + }
>
> ctl = readl(cgu->base + pll_info->reg);
>
next prev parent reply other threads:[~2021-06-01 14:09 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-30 16:49 [PATCH v2 0/6] clk: Ingenic JZ4760(B) support Paul Cercueil
2021-05-30 16:49 ` [PATCH v2 1/6] dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 2/6] clk: Support bypassing dividers Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 3/6] clk: ingenic: Read bypass register only when there is one Paul Cercueil
2021-06-01 14:08 ` Zhou Yanjie [this message]
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 4/6] clk: ingenic: Remove pll_info.no_bypass_bit Paul Cercueil
2021-06-01 14:07 ` Zhou Yanjie
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 5/6] clk: ingenic: Support overriding PLLs M/N/OD calc algorithm Paul Cercueil
2021-06-28 2:49 ` Stephen Boyd
2021-05-30 16:49 ` [PATCH v2 6/6] clk: ingenic: Add support for the JZ4760 Paul Cercueil
2021-06-28 2:50 ` Stephen Boyd
2021-06-30 12:18 ` Paul Cercueil
2021-06-22 14:48 ` [PATCH v2 0/6] clk: Ingenic JZ4760(B) support 周琰杰
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