From: Ard Biesheuvel <ardb@kernel.org>
To: devicetree@vger.kernel.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
Brijesh Singh <brijeshkumar.singh@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v3 3/8] dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
Date: Tue, 3 Dec 2019 15:23:01 +0000 [thread overview]
Message-ID: <20191203152306.7839-4-ardb@kernel.org> (raw)
In-Reply-To: <20191203152306.7839-1-ardb@kernel.org>
Upgrade the DT descriptions of the AMD Seattle XGBE network
controllers to use the current SMMU bindings.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 22 +++++++-------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
index d97498361ce3..9259e547e2e8 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
@@ -55,7 +55,7 @@
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
- #stream-id-cells = <16>;
+ iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
@@ -81,11 +81,11 @@
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
- #stream-id-cells = <16>;
+ iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
- xgmac0_smmu: smmu@e0600000 {
+ xgmac0_smmu: iommu@e0600000 {
compatible = "arm,mmu-401";
reg = <0 0xe0600000 0 0x10000>;
#global-interrupts = <1>;
@@ -94,14 +94,11 @@
*/
<0 336 4>,
<0 336 4>;
-
- mmu-masters = <&xgmac0
- 0 1 2 3 4 5 6 7
- 16 17 18 19 20 21 22 23
- >;
+ #iommu-cells = <2>;
+ dma-coherent;
};
- xgmac1_smmu: smmu@e0800000 {
+ xgmac1_smmu: iommu@e0800000 {
compatible = "arm,mmu-401";
reg = <0 0xe0800000 0 0x10000>;
#global-interrupts = <1>;
@@ -110,9 +107,6 @@
*/
<0 335 4>,
<0 335 4>;
-
- mmu-masters = <&xgmac1
- 0 1 2 3 4 5 6 7
- 16 17 18 19 20 21 22 23
- >;
+ #iommu-cells = <2>;
+ dma-coherent;
};
--
2.17.1
next prev parent reply other threads:[~2019-12-03 15:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 15:22 [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Ard Biesheuvel
2019-12-03 15:22 ` [PATCH v3 1/8] dt: amd-seattle: remove Husky platform Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 2/8] dt: amd-seattle: remove Overdrive revision A0 support Ard Biesheuvel
2019-12-03 15:23 ` Ard Biesheuvel [this message]
2019-12-03 15:23 ` [PATCH v3 4/8] dt: amd-seattle: fix PCIe legacy interrupt routing Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 5/8] dt: amd-seattle: add a description of the PCIe SMMU Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 6/8] dt: amd-seattle: add description of the SATA/CCP SMMUs Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 7/8] dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 8/8] dt: amd-seattle: add a description of the CPUs and caches Ard Biesheuvel
2020-01-28 10:23 ` [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Alexandru Elisei
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