Re: [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions

From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Ard Biesheuvel <ardb@kernel.org>, devicetree@vger.kernel.org
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions
Date: Tue, 28 Jan 2020 10:23:28 +0000	[thread overview]
Message-ID: <ab7e20fa-3d4c-6b9c-e74a-fe88f1ba5ccf@arm.com> (raw)
In-Reply-To: <20191203152306.7839-1-ardb@kernel.org>

Hi,

On 12/3/19 3:22 PM, Ard Biesheuvel wrote:
> Bring the DT descriptions for AMD Seattle up to date:
> - upgrade the existing SMMU descriptions to the new binding, and add the
>   missing descriptions of the PCIe and SATA SMMUs
> - fix the description of the PCIe legacy interrupt routing
> - remove the obsolete A0 Overdrive and Husky

This is long overdue, I've been playing with PCI passthrough on an AMD Seattle
machine using these patches since you posted them on the mailing list. With these
patches, PCI passthrough has been tested with the following devices: Intel 82574L
Gigabit Ethernet card, Samsung 970 Pro NVME, Realtek 8168 Gigabit Ethernet card,
NVIDIA Quadro P400, AMD Firepro W2100, Myricom 10 Gigabit Ethernet card and a
Seagate Barracuda 1000GB drive with a generic PCIE SATA card.

For patches #3-#6 (that touch the SMMU):

Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>

Thanks,
Alex
>
> Changes since v2:
> - use Cortex-A57 specific compatible strings for CPUs and PMU
> - use iommu@... not smmu@.... for SMMU DT node identifiers
> - match the entire range of stream IDs 0x0..0x1f for the first SATA port, for
>   compatibility with some B0 silicon revision based boards
>
> Changes since v1:
> - add missing dma-coherent properties to xgbe SMMU nodes
> - add patch to disable GPIO and IPMI blocks on B0 silicon
> - add patch to include DT descriptions of the CPU and cache topologies
>
> Cc: Brijesh Singh <brijeshkumar.singh@amd.com>
> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Cc: Tom Lendacky <thomas.lendacky@amd.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
>
> Ard Biesheuvel (8):
>   dt: amd-seattle: remove Husky platform
>   dt: amd-seattle: remove Overdrive revision A0 support
>   dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
>   dt: amd-seattle: fix PCIe legacy interrupt routing
>   dt: amd-seattle: add a description of the PCIe SMMU
>   dt: amd-seattle: add description of the SATA/CCP SMMUs
>   dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0
>   dt: amd-seattle: add a description of the CPUs and caches
>
>  arch/arm64/boot/dts/amd/Makefile              |   4 +-
>  .../boot/dts/amd/amd-overdrive-rev-b0.dts     |  13 +-
>  .../boot/dts/amd/amd-overdrive-rev-b1.dts     |   1 +
>  arch/arm64/boot/dts/amd/amd-overdrive.dts     |  66 ------
>  arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 224 ++++++++++++++++++
>  arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi  |  70 ++++--
>  .../boot/dts/amd/amd-seattle-xgbe-b.dtsi      |  22 +-
>  arch/arm64/boot/dts/amd/husky.dts             |  84 -------
>  8 files changed, 287 insertions(+), 197 deletions(-)
>  delete mode 100644 arch/arm64/boot/dts/amd/amd-overdrive.dts
>  create mode 100644 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
>  delete mode 100644 arch/arm64/boot/dts/amd/husky.dts
>