From: Ard Biesheuvel <ardb@kernel.org>
To: devicetree@vger.kernel.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
Brijesh Singh <brijeshkumar.singh@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v3 5/8] dt: amd-seattle: add a description of the PCIe SMMU
Date: Tue, 3 Dec 2019 15:23:03 +0000 [thread overview]
Message-ID: <20191203152306.7839-6-ardb@kernel.org> (raw)
In-Reply-To: <20191203152306.7839-1-ardb@kernel.org>
Add a description of the SMMU that covers the PCIe host bridge
on AMD Seattle.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
index 9fa6890fca35..124e58a76be0 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -239,6 +239,16 @@
<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
/* 64-bit MMIO (size= 508G) */
<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
+ iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
+ };
+
+ pcie_smmu: iommu@e0a00000 {
+ compatible = "arm,mmu-401";
+ reg = <0 0xe0a00000 0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <0 333 4>, <0 333 4>;
+ #iommu-cells = <1>;
+ dma-coherent;
};
/* Perf CCN504 PMU */
--
2.17.1
next prev parent reply other threads:[~2019-12-03 15:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 15:22 [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Ard Biesheuvel
2019-12-03 15:22 ` [PATCH v3 1/8] dt: amd-seattle: remove Husky platform Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 2/8] dt: amd-seattle: remove Overdrive revision A0 support Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 3/8] dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 4/8] dt: amd-seattle: fix PCIe legacy interrupt routing Ard Biesheuvel
2019-12-03 15:23 ` Ard Biesheuvel [this message]
2019-12-03 15:23 ` [PATCH v3 6/8] dt: amd-seattle: add description of the SATA/CCP SMMUs Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 7/8] dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 Ard Biesheuvel
2019-12-03 15:23 ` [PATCH v3 8/8] dt: amd-seattle: add a description of the CPUs and caches Ard Biesheuvel
2020-01-28 10:23 ` [PATCH v3 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Alexandru Elisei
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