[PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[Suman Anna]

Hi Nishanth,

The TI K3 R5F remoteproc driver and bindings were merged into 5.10-rc1,
and this series adds the follow-on base dt nodes for the R5F remote
processors on TI K3 AM65x and J721E SoCs. Additional memory nodes were
also added to boot these processors successfully on applicable TI K3
AM65x and J721E EVM boards. The series uses previously accepted mailbox
nodes.

The patches follow slightly different convention between AM65x and
J721E. The reserved-memory nodes are added directly in the relevant
board dts file for AM65x boards, while they are added in the common
k3-j721e-som-p0.dtsi file for J721E SoCs following the similar addition
of K3 C66x and C71x DSP nodes in 5.10-rc1.

Patches apply on top of your 5.10-rc1 based staging branch.

I have validated the IPC functionality using System Firmware v2020.04a
and corresponding IPC example firmwares. 

regards
Suman

Suman Anna (8):
  arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node
  arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs
  arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for
    R5Fs
  arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between
    R5F cores
  arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node
  arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for
    R5Fs

 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi       |  42 ++++++-
 .../arm64/boot/dts/ti/k3-am654-base-board.dts |  45 ++++++-
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     |  82 ++++++++++++-
 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  42 ++++++-
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 110 +++++++++++++++++-
 5 files changed, 316 insertions(+), 5 deletions(-)

-- 
2.28.0

[PATCH 1/8] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node

[Suman Anna]

The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS)
subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the
MCU domain, and can be configured at boot time to be either run in a
LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in
Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM)
internal memories for each core split between two banks - TCMA and TCMB
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5F clusters such as the absence of an ACP
port, presence of an additional TI-specific Region Address Translater
(RAT) module for translating 32-bit CPU addresses into larger system
bus addresses etc.

Add the DT node for this R5F cluster/subsystem, the two R5F cores are
added as child nodes to the main cluster node. The cluster is configured
to run in LockStep mode by default, with the ATCMs enabled to allow the
R5 cores to execute code from DDR with boot-strapping code from ATCM.
The inter-processor communication between the main A53 cores and these
processors is achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
    am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode)
    am65x-mcu-r5f0_1-fw (Core1 in Split mode)

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 42 ++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 044042b166d9..7454c8cec0cc 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
  *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 &cbass_mcu {
@@ -268,4 +268,44 @@ mcu_cpsw_cpts_mux: refclk-mux {
 			};
 		};
 	};
+
+	mcu_r5fss0: r5fss@41000000 {
+		compatible = "ti,am654-r5fss";
+		ti,cluster-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x41000000 0x00 0x41000000 0x20000>,
+			 <0x41400000 0x00 0x41400000 0x20000>;
+		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
+
+		mcu_r5fss0_core0: r5f@41000000 {
+			compatible = "ti,am654-r5f";
+			reg = <0x41000000 0x00008000>,
+			      <0x41010000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <159>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 159 1>;
+			firmware-name = "am65x-mcu-r5f0_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		mcu_r5fss0_core1: r5f@41400000 {
+			compatible = "ti,am654-r5f";
+			reg = <0x41400000 0x00008000>,
+			      <0x41410000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <245>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 245 1>;
+			firmware-name = "am65x-mcu-r5f0_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
 };
-- 
2.28.0

[PATCH 2/8] arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs

[Suman Anna]

Add the required 'mboxes' property to both the R5F processors on all the
TI K3 AM65x boards. The mailboxes and some shared memory are required
for running the Remote Processor Messaging (RPMsg) stack between the
host processor and each of the R5Fs. The chosen sub-mailboxes match the
values used in the current firmware images. This can be changed, if
needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Note that the R5F Core1 resources are needed and used only when the
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index d12dd89f3405..0cb5b9cb65ba 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;
@@ -441,6 +441,14 @@ &mailbox0_cluster11 {
 	status = "disabled";
 };
 
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+};
+
 &ospi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-- 
2.28.0

[PATCH 3/8] arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs

[Suman Anna]

The R5F processors do not have an MMU, and as such require the exact memory
used by the firmwares to be set-aside. Four carveout reserved memory nodes
have been added with two each (1 MB and 15 MB in size) used for each of the
MCU R5F remote processor devices on all the TI K3 AM65x boards. These nodes
are assigned to the respective rproc device nodes as well.

The current carveout addresses and sizes are defined statically for each
device. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions
for the firmware memory.

Note that the R5F1 carveouts are needed only if the corresponding R5F
cluster is running in Split (non-LockStep) mode. The corresponding
reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 .../arm64/boot/dts/ti/k3-am654-base-board.dts | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 0cb5b9cb65ba..23a1f266d1d4 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -29,11 +29,36 @@ reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
+
 		secure_ddr: secure-ddr@9e800000 {
 			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xa0000000 0 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xa0100000 0 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xa1000000 0 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xa1100000 0 0xf00000>;
+			no-map;
+		};
 	};
 
 	gpio-keys {
@@ -442,10 +467,14 @@ &mailbox0_cluster11 {
 };
 
 &mcu_r5fss0_core0 {
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
 	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 };
 
 &mcu_r5fss0_core1 {
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
 	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
 };
 
-- 
2.28.0

[PATCH 4/8] arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores

[Suman Anna]

Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the MCU R5F
remote processors running RTOS on all the TI AM654 boards. This memory
shall be exercised only if the MCU R5FSS cluster is configured for Split
mode.  A single 1 MB of memory at 0xa2000000 is reserved for this purpose,
and this accounts for all the vrings and vring buffers between pair of
these R5F remote processors.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 23a1f266d1d4..17f3a85360e6 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -59,6 +59,12 @@ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
 			reg = <0 0xa1100000 0 0xf00000>;
 			no-map;
 		};
+
+		rtos_ipc_memory_region: ipc-memories@a2000000 {
+			reg = <0x00 0xa2000000 0x00 0x00100000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	gpio-keys {
-- 
2.28.0

[PATCH 5/8] arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node

[Suman Anna]

The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
    MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
    MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      | 42 ++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index e581cb1d87ee..6c44afae9187 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
  *
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 &cbass_mcu_wakeup {
@@ -353,4 +353,44 @@ cpts@3d000 {
 			ti,cpts-periodic-outputs = <2>;
 		};
 	};
+
+	mcu_r5fss0: r5fss@41000000 {
+		compatible = "ti,j721e-r5fss";
+		ti,cluster-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x41000000 0x00 0x41000000 0x20000>,
+			 <0x41400000 0x00 0x41400000 0x20000>;
+		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+		mcu_r5fss0_core0: r5f@41000000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x41000000 0x00008000>,
+			      <0x41010000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <250>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 250 1>;
+			firmware-name = "j7-mcu-r5f0_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		mcu_r5fss0_core1: r5f@41400000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x41400000 0x00008000>,
+			      <0x41410000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <251>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 251 1>;
+			firmware-name = "j7-mcu-r5f0_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
 };
-- 
2.28.0

[PATCH 6/8] arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes

[Suman Anna]

The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.

Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5F cores are each added as child nodes to the corresponding
main cluster node. Both the clusters are configured to run in LockStep
mode by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
    MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes)
    MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode)
    MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes)
    MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode)

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 ++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e2a96b2c423c..b5cae2e03a09 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for J721E SoC Family Main Domain peripherals
  *
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/mux/mux.h>
@@ -1581,6 +1581,86 @@ watchdog1: watchdog@2210000 {
 		assigned-clock-parents = <&k3_clks 253 5>;
 	};
 
+	main_r5fss0: r5fss@5c00000 {
+		compatible = "ti,j721e-r5fss";
+		ti,cluster-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+			 <0x5d00000 0x00 0x5d00000 0x20000>;
+		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f@5c00000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x5c00000 0x00008000>,
+			      <0x5c10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <245>;
+			ti,sci-proc-ids = <0x06 0xff>;
+			resets = <&k3_reset 245 1>;
+			firmware-name = "j7-main-r5f0_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f@5d00000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x5d00000 0x00008000>,
+			      <0x5d10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <246>;
+			ti,sci-proc-ids = <0x07 0xff>;
+			resets = <&k3_reset 246 1>;
+			firmware-name = "j7-main-r5f0_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
+	main_r5fss1: r5fss@5e00000 {
+		compatible = "ti,j721e-r5fss";
+		ti,cluster-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+			 <0x5f00000 0x00 0x5f00000 0x20000>;
+		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss1_core0: r5f@5e00000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x5e00000 0x00008000>,
+			      <0x5e10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <247>;
+			ti,sci-proc-ids = <0x08 0xff>;
+			resets = <&k3_reset 247 1>;
+			firmware-name = "j7-main-r5f1_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss1_core1: r5f@5f00000 {
+			compatible = "ti,j721e-r5f";
+			reg = <0x5f00000 0x00008000>,
+			      <0x5f10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <248>;
+			ti,sci-proc-ids = <0x09 0xff>;
+			resets = <&k3_reset 248 1>;
+			firmware-name = "j7-main-r5f1_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
 	c66_0: dsp@4d80800000 {
 		compatible = "ti,j721e-c66-dsp";
 		reg = <0x4d 0x80800000 0x00 0x00048000>,
-- 
2.28.0

[PATCH 7/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs

[Suman Anna]

Add the required 'mboxes' property to all the R5F processors for the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The nodes are therefore
added in the common k3-j721e-som-p0.dtsi file so that all of these can
be co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 26 ++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 5dc3ba739131..c48f4ffd1435 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;
@@ -208,6 +208,30 @@ &mailbox0_cluster11 {
 	status = "disabled";
 };
 
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+};
+
 &c66_0 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
-- 
2.28.0

[PATCH 8/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within both the MCU and MAIN domains for the
TI J721E EVM boards. These nodes are assigned to the respective rproc
device nodes as well. The first region will be used as the DMA pool for
the rproc device, and the second region will furnish the static carveout
regions for the firmware memory.

The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables either
to allocate the memory for firmware memory segments.

Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding
remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 84 +++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index c48f4ffd1435..57720e6a04c5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -26,6 +26,78 @@ secure_ddr: optee@9e800000 {
 			no-map;
 		};
 
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5100000 0x00 0xf00000>;
+			no-map;
+		};
+
 		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
 			compatible = "shared-dma-pool";
 			reg = <0x00 0xa6000000 0x00 0x100000>;
@@ -210,26 +282,38 @@ &mailbox0_cluster11 {
 
 &mcu_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-- 
2.28.0

Re: [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[Lokesh Vutla]

On 29/10/20 9:07 am, Suman Anna wrote:
> Hi Nishanth,
> 
> The TI K3 R5F remoteproc driver and bindings were merged into 5.10-rc1,
> and this series adds the follow-on base dt nodes for the R5F remote
> processors on TI K3 AM65x and J721E SoCs. Additional memory nodes were
> also added to boot these processors successfully on applicable TI K3
> AM65x and J721E EVM boards. The series uses previously accepted mailbox
> nodes.
> 
> The patches follow slightly different convention between AM65x and
> J721E. The reserved-memory nodes are added directly in the relevant
> board dts file for AM65x boards, while they are added in the common
> k3-j721e-som-p0.dtsi file for J721E SoCs following the similar addition
> of K3 C66x and C71x DSP nodes in 5.10-rc1.
> 
> Patches apply on top of your 5.10-rc1 based staging branch.
> 
> I have validated the IPC functionality using System Firmware v2020.04a
> and corresponding IPC example firmwares. 


Series looks good to me.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

On a side note: any reason not to add R5f nodes for J7200?

Thanks and regards,
Lokesh

Re: [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[Suman Anna]

On 11/6/20 5:43 AM, Lokesh Vutla wrote:
> 
> 
> On 29/10/20 9:07 am, Suman Anna wrote:
>> Hi Nishanth,
>>
>> The TI K3 R5F remoteproc driver and bindings were merged into 5.10-rc1,
>> and this series adds the follow-on base dt nodes for the R5F remote
>> processors on TI K3 AM65x and J721E SoCs. Additional memory nodes were
>> also added to boot these processors successfully on applicable TI K3
>> AM65x and J721E EVM boards. The series uses previously accepted mailbox
>> nodes.
>>
>> The patches follow slightly different convention between AM65x and
>> J721E. The reserved-memory nodes are added directly in the relevant
>> board dts file for AM65x boards, while they are added in the common
>> k3-j721e-som-p0.dtsi file for J721E SoCs following the similar addition
>> of K3 C66x and C71x DSP nodes in 5.10-rc1.
>>
>> Patches apply on top of your 5.10-rc1 based staging branch.
>>
>> I have validated the IPC functionality using System Firmware v2020.04a
>> and corresponding IPC example firmwares. 
> 
> 
> Series looks good to me.
> 
> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
>

Thanks Lokesh.


> On a side note: any reason not to add R5f nodes for J7200?

J7200 nodes would have to wait until the corresponding dt-bindings and driver
updates make it into mainline. They do use different compatibles, and I will
post them in the next couple of weeks.

regards
Suman

Re: [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[Nishanth Menon]

On Wed, 28 Oct 2020 22:37:54 -0500, Suman Anna wrote:
> The TI K3 R5F remoteproc driver and bindings were merged into 5.10-rc1,
> and this series adds the follow-on base dt nodes for the R5F remote
> processors on TI K3 AM65x and J721E SoCs. Additional memory nodes were
> also added to boot these processors successfully on applicable TI K3
> AM65x and J721E EVM boards. The series uses previously accepted mailbox
> nodes.
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/8] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node
      commit: 5bb9e0f6e8505e31159963150104569d9b8a8911
[2/8] arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs
      commit: 10332cd6bcf287e22dac875d121b73adb762f96b
[3/8] arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs
      commit: 954ec5139db091ff51cec4bf57c42f9deebc8747
[4/8] arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores
      commit: f82c5e0a8bc1311aee140bfed0888fc9a99afde0
[5/8] arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node
      commit: dd74c9459cf2c87c3143b4b9005b7c9056fccdb0
[6/8] arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes
      commit: df445ff9de893146107d37e0cd5e542f800d9b39
[7/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs
      commit: 2879b593c3784e5eafc67cae915d8b7d680455f3
[8/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs
      commit: 0f191152bcba6758804eed4f6463f9bd32bdbfdb


Please note:
* I understand the complexity of the code requiring the split up in the
  incremental patches, so I believe it has a case for us to do the same.
* Special note on MCU R5: there are cases on J721e, J7200 and future devices
  where "device management" functionality will run on MCU R5 core 0, which
  means it is capable of running special firmware that may not respond on
  mailbox at all.. The assumption is that the driver is capable of detecting
  and handling such scenarios and this is a hardware description (as it
  should be).

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs

[Suman Anna]

On 11/12/20 11:48 AM, Nishanth Menon wrote:
> On Wed, 28 Oct 2020 22:37:54 -0500, Suman Anna wrote:
>> The TI K3 R5F remoteproc driver and bindings were merged into 5.10-rc1,
>> and this series adds the follow-on base dt nodes for the R5F remote
>> processors on TI K3 AM65x and J721E SoCs. Additional memory nodes were
>> also added to boot these processors successfully on applicable TI K3
>> AM65x and J721E EVM boards. The series uses previously accepted mailbox
>> nodes.
>>
>> [...]
> 
> Hi Suman Anna,
> 
> I have applied the following to branch ti-k3-dts-next on [1].
> Thank you!
> 
> [1/8] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node
>       commit: 5bb9e0f6e8505e31159963150104569d9b8a8911
> [2/8] arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs
>       commit: 10332cd6bcf287e22dac875d121b73adb762f96b
> [3/8] arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs
>       commit: 954ec5139db091ff51cec4bf57c42f9deebc8747
> [4/8] arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores
>       commit: f82c5e0a8bc1311aee140bfed0888fc9a99afde0
> [5/8] arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node
>       commit: dd74c9459cf2c87c3143b4b9005b7c9056fccdb0
> [6/8] arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes
>       commit: df445ff9de893146107d37e0cd5e542f800d9b39
> [7/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs
>       commit: 2879b593c3784e5eafc67cae915d8b7d680455f3
> [8/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs
>       commit: 0f191152bcba6758804eed4f6463f9bd32bdbfdb
> 
> 
> Please note:
> * I understand the complexity of the code requiring the split up in the
>   incremental patches, so I believe it has a case for us to do the same.
> * Special note on MCU R5: there are cases on J721e, J7200 and future devices
>   where "device management" functionality will run on MCU R5 core 0, which
>   means it is capable of running special firmware that may not respond on
>   mailbox at all.. The assumption is that the driver is capable of detecting
>   and handling such scenarios and this is a hardware description (as it
>   should be).

Yep, this is understood.

> 
> All being well this means that it will be integrated into the linux-next
> tree (usually sometime in the next 24 hours) and sent up the chain during
> the next merge window (or sooner if it is a relevant bug fix), however if
> problems are discovered then the patch may be dropped or reverted.
> 
> You may get further e-mails resulting from automated or manual testing
> and review of the tree, please engage with people reporting problems and
> send followup patches addressing any issues that are reported if needed.
> 
> If any updates are required or you are submitting further changes they
> should be sent as incremental updates against current git, existing
> patches will not be replaced.
> 
> Please add any relevant lists and maintainers to the CCs when replying
> to this mail.
> 
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
> 

Thanks, Nishanth!

regards
Suman