[PATCH 0/6] Extend irqchip ocelot driver to support other SoCs

[PATCH 0/6] Extend irqchip ocelot driver to support other SoCs

[Gregory CLEMENT]

Hello,

Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.

This series of patches add support for Luton, Serval and Jaguar2, they
are all MIPS based.

The first patches of the series also updates the binding documentation
with the new compatible strings.

Gregory

Gregory CLEMENT (6):
  dt-bindings: interrupt-controller: Add binding for the Microsemi Luton
    interrupt controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi
    Serval interrupt controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi
    Jaguar2 interrupt controller
  irqchip: ocelot: Add support for Luton platforms
  irqchip: ocelot: Add support for Serval platforms
  irqchip: ocelot: Add support for Jaguar2 platforms

 .../mscc,ocelot-icpu-intr.txt                 |   6 +-
 drivers/irqchip/irq-mscc-ocelot.c             | 183 ++++++++++++++++--
 2 files changed, 167 insertions(+), 22 deletions(-)

-- 
2.28.0

[PATCH 1/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Luton interrupt controller

[Gregory CLEMENT]

Add the Device Tree binding documentation for the Microsemi Luton
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index f5baeccb689f..94dc95cb815c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,8 +1,10 @@
 Microsemi Ocelot SoC ICPU Interrupt Controller
 
+Luton belongs the same family of Ocelot: the VCoreIII family
+
 Required properties:
 
-- compatible : should be "mscc,ocelot-icpu-intr"
+- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.28.0

Re: [PATCH 1/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Luton interrupt controller

[Rob Herring]

On Thu, Nov 05, 2020 at 06:15:30PM +0100, Gregory CLEMENT wrote:
> Add the Device Tree binding documentation for the Microsemi Luton
> interrupt controller that is part of the ICPU. It is connected directly to
> the MIPS core interrupt controller.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>  .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt   | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

The patches look fine, but can you convert this to schema first.

> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> index f5baeccb689f..94dc95cb815c 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> @@ -1,8 +1,10 @@
>  Microsemi Ocelot SoC ICPU Interrupt Controller
>  
> +Luton belongs the same family of Ocelot: the VCoreIII family
> +
>  Required properties:
>  
> -- compatible : should be "mscc,ocelot-icpu-intr"
> +- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
>  - reg : Specifies base physical address and size of the registers.
>  - interrupt-controller : Identifies the node as an interrupt controller
>  - #interrupt-cells : Specifies the number of cells needed to encode an
> -- 
> 2.28.0
> 

[PATCH 2/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Serval interrupt controller

[Gregory CLEMENT]

Add the Device Tree binding documentation for the Microsemi Serval
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt    | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index 94dc95cb815c..42de86e023a6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,10 +1,11 @@
 Microsemi Ocelot SoC ICPU Interrupt Controller
 
-Luton belongs the same family of Ocelot: the VCoreIII family
+Luton and Servals belong the same family as Ocelot: the VCoreIII family
 
 Required properties:
 
 - compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
+               or "mscc,serval-icpu-intr"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.28.0

[PATCH 3/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Jaguar2 interrupt controller

[Gregory CLEMENT]

Add the Device Tree binding documentation for the Microsemi Jaguar2
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 .../interrupt-controller/mscc,ocelot-icpu-intr.txt         | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index 42de86e023a6..916832064d64 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,11 +1,12 @@
 Microsemi Ocelot SoC ICPU Interrupt Controller
 
-Luton and Servals belong the same family as Ocelot: the VCoreIII family
+Luton, Servals and Jaguar 2 belong the same family as Ocelot: the
+VCoreIII family
 
 Required properties:
 
-- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
-               or "mscc,serval-icpu-intr"
+- compatible : should be "mscc,ocelot-icpu-intr", "mscc,luton-icpu-intr",
+               "mscc,serval-icpu-intr" or "mscc,jaguar2-icpu-intr"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.28.0

[PATCH 4/6] irqchip: ocelot: Add support for Luton platforms

[Gregory CLEMENT]

This patch extends irqchip driver for oceleot to be used with an other
vcoreiii base platform: Luton.

Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 145 +++++++++++++++++++++++++-----
 1 file changed, 123 insertions(+), 22 deletions(-)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 88143c0b700c..9964800c53c2 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -12,39 +12,115 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/interrupt.h>
 
-#define ICPU_CFG_INTR_INTR_STICKY	0x10
-#define ICPU_CFG_INTR_INTR_ENA		0x18
-#define ICPU_CFG_INTR_INTR_ENA_CLR	0x1c
-#define ICPU_CFG_INTR_INTR_ENA_SET	0x20
-#define ICPU_CFG_INTR_DST_INTR_IDENT(x)	(0x38 + 0x4 * (x))
-#define ICPU_CFG_INTR_INTR_TRIGGER(x)	(0x5c + 0x4 * (x))
-
-#define OCELOT_NR_IRQ 24
+#define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x)	(_p->reg_off_ident + 0x4 * (x))
+#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x)	(_p->reg_off_trigger + 0x4 * (x))
+
+#define FLAGS_NEED_INIT_ENABLE	BIT(0)
+#define FLAGS_FORCE_LUTON_STYLE	BIT(1)
+#define FLAGS_HAS_TRIGGER	BIT(2)
+
+struct chip_props {
+	u32 flags;
+	u32 reg_off_sticky;
+	u32 reg_off_ena;
+	u32 reg_off_ena_clr;
+	u32 reg_off_ena_set;
+	u32 reg_off_ident;
+	u32 reg_off_trigger;
+	u32 reg_off_force;
+	u32 reg_off_ena_irq0;
+	u32 n_irq;
+};
+
+static const struct chip_props ocelot_props = {
+	.flags			= FLAGS_HAS_TRIGGER,
+	.reg_off_sticky		= 0x10,
+	.reg_off_ena		= 0x18,
+	.reg_off_ena_clr	= 0x1c,
+	.reg_off_ena_set	= 0x20,
+	.reg_off_ident		= 0x38,
+	.reg_off_trigger	= 0x5c,
+	.reg_off_force		= 0xc,
+	.n_irq			= 24,
+};
+
+static const struct chip_props luton_props = {
+	.flags			= FLAGS_NEED_INIT_ENABLE |
+				  FLAGS_FORCE_LUTON_STYLE,
+	.reg_off_sticky		= 0,
+	.reg_off_ena		= 0x4,
+	.reg_off_ena_clr	= 0x8,
+	.reg_off_ena_set	= 0xc,
+	.reg_off_ident		= 0x18,
+	.reg_off_trigger	= 0,
+	.reg_off_force		= 0x38,
+	.reg_off_ena_irq0	= 0x14,
+	.n_irq			= 28,
+};
 
 static void ocelot_irq_unmask(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	struct irq_domain *d = data->domain;
+	struct chip_props *p = d->host_data;
 	struct irq_chip_type *ct = irq_data_get_chip_type(data);
 	unsigned int mask = data->mask;
 	u32 val;
 
 	irq_gc_lock(gc);
-	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |
-	      irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));
-	if (!(val & mask))
-		irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);
+	if (p->flags & FLAGS_HAS_TRIGGER) {
+		val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
+			irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
+		if (!(val & mask))
+			irq_reg_writel(gc, mask, p->reg_off_sticky);
+	}
 
 	*ct->mask_cache &= ~mask;
-	irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);
+	irq_reg_writel(gc, mask, p->reg_off_ena_set);
 	irq_gc_unlock(gc);
 }
 
+static void luton_irq_force(struct irq_data *data,
+			    struct irq_chip_generic *gc,
+			    struct chip_props *p)
+{
+	int off = p->reg_off_force + (data->hwirq * sizeof(u32));
+	u32 val = irq_reg_readl(gc, off);
+
+	irq_reg_writel(gc, val | BIT(3), off);
+}
+
+static int ocelot_irq_force(struct irq_data *data,
+			    enum irqchip_irq_state which, bool state)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	struct irq_domain *d = data->domain;
+	struct chip_props *p = d->host_data;
+	int ret = -EINVAL;
+
+	/* Only supports triggering */
+	if ((which == IRQCHIP_STATE_PENDING ||
+	     which == IRQCHIP_STATE_ACTIVE) &&
+	    state && p->reg_off_force) {
+		if (p->flags & FLAGS_FORCE_LUTON_STYLE)
+			/* Config register style */
+			luton_irq_force(data, gc, p);
+		else
+			/* New, bitmask style */
+			irq_reg_writel(gc, data->mask, p->reg_off_force);
+		ret = 0;
+	}
+
+	return ret;
+}
+
 static void ocelot_irq_handler(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct irq_domain *d = irq_desc_get_handler_data(desc);
+	struct chip_props *p = d->host_data;
 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
-	u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));
+	u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0));
 
 	chained_irq_enter(chip, desc);
 
@@ -58,25 +134,28 @@ static void ocelot_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static int __init ocelot_irq_init(struct device_node *node,
-				  struct device_node *parent)
+static int __init vcoreiii_irq_init(struct device_node *node,
+				    struct device_node *parent,
+				    const struct chip_props *p)
 {
 	struct irq_domain *domain;
 	struct irq_chip_generic *gc;
 	int parent_irq, ret;
 
+	pr_info("%s: Load, %d irqs\n", node->name, p->n_irq);
+
 	parent_irq = irq_of_parse_and_map(node, 0);
 	if (!parent_irq)
 		return -EINVAL;
 
-	domain = irq_domain_add_linear(node, OCELOT_NR_IRQ,
+	domain = irq_domain_add_linear(node, p->n_irq,
 				       &irq_generic_chip_ops, NULL);
 	if (!domain) {
 		pr_err("%pOFn: unable to add irq domain\n", node);
 		return -ENOMEM;
 	}
 
-	ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1,
+	ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1,
 					     "icpu", handle_level_irq,
 					     0, 0, 0);
 	if (ret) {
@@ -92,16 +171,23 @@ static int __init ocelot_irq_init(struct device_node *node,
 		goto err_gc_free;
 	}
 
-	gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;
-	gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;
+	gc->chip_types[0].regs.ack = p->reg_off_sticky;
+	gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
 	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
 	gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
+	gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
+	gc->chip_types[0].chip.irq_set_irqchip_state = ocelot_irq_force;
 
 	/* Mask and ack all interrupts */
-	irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);
-	irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);
+	irq_reg_writel(gc, 0, p->reg_off_ena);
+	irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
+
+	/* Overall init */
+	if (p->flags & FLAGS_NEED_INIT_ENABLE)
+		irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);
 
+	domain->host_data = (void *)p;
 	irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
 					 domain);
 
@@ -115,4 +201,19 @@ static int __init ocelot_irq_init(struct device_node *node,
 
 	return ret;
 }
+
+static int __init ocelot_irq_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	return vcoreiii_irq_init(node, parent, &ocelot_props);
+}
+
 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
+
+static int __init luton_irq_init(struct device_node *node,
+				 struct device_node *parent)
+{
+	return vcoreiii_irq_init(node, parent, &luton_props);
+}
+
+IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
-- 
2.28.0

[PATCH 5/6] irqchip: ocelot: Add support for Serval platforms

[Gregory CLEMENT]

This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Serval.

Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 9964800c53c2..584af3b0a9e2 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -44,6 +44,18 @@ static const struct chip_props ocelot_props = {
 	.n_irq			= 24,
 };
 
+static const struct chip_props serval_props = {
+	.flags			= FLAGS_HAS_TRIGGER,
+	.reg_off_sticky		= 0xc,
+	.reg_off_ena		= 0x14,
+	.reg_off_ena_clr	= 0x18,
+	.reg_off_ena_set	= 0x1c,
+	.reg_off_ident		= 0x20,
+	.reg_off_trigger	= 0x4,
+	.reg_off_force		= 0x8,
+	.n_irq			= 24,
+};
+
 static const struct chip_props luton_props = {
 	.flags			= FLAGS_NEED_INIT_ENABLE |
 				  FLAGS_FORCE_LUTON_STYLE,
@@ -210,6 +222,14 @@ static int __init ocelot_irq_init(struct device_node *node,
 
 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
 
+static int __init serval_irq_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	return vcoreiii_irq_init(node, parent, &serval_props);
+}
+
+IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init);
+
 static int __init luton_irq_init(struct device_node *node,
 				 struct device_node *parent)
 {
-- 
2.28.0

[PATCH 6/6] irqchip: ocelot: Add support for Jaguar2 platforms

[Gregory CLEMENT]

This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.

Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 584af3b0a9e2..0dfea8771172 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -70,6 +70,18 @@ static const struct chip_props luton_props = {
 	.n_irq			= 28,
 };
 
+static const struct chip_props jaguar2_props = {
+	.flags			= FLAGS_HAS_TRIGGER,
+	.reg_off_sticky		= 0x10,
+	.reg_off_ena		= 0x18,
+	.reg_off_ena_clr	= 0x1c,
+	.reg_off_ena_set	= 0x20,
+	.reg_off_ident		= 0x38,
+	.reg_off_trigger	= 0x5c,
+	.reg_off_force		= 0xc,
+	.n_irq			= 29,
+};
+
 static void ocelot_irq_unmask(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
@@ -237,3 +249,11 @@ static int __init luton_irq_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
+
+static int __init jaguar2_irq_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	return vcoreiii_irq_init(node, parent, &jaguar2_props);
+}
+
+IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init);
-- 
2.28.0