* [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML
@ 2022-01-12 15:15 Michael Tretter
2022-01-12 15:15 ` [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml Michael Tretter
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Michael Tretter @ 2022-01-12 15:15 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, m.tretter, kernel
Hi,
This series converts the ZynqMP dma engine dt bindings to yaml and fixes the
ZynqMP device tree following the stricter yaml bindings.
The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt to
avoid conflicts when applying the patches to the zynqmp/dt tree.
Patch 1 converts the binding to yaml, Patches 2 and 3 cleanup the dma engine
nodes in the zynqmp.dtsi that is included by actual board device trees.
Michael
Michael Tretter (3):
dt-bindings: dmaengine: zynqmp_dma: convert to yaml
arm64: zynqmp: Add missing #dma-cells property
arm64: zynqmp: Rename dma to dma-controller
.../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 85 +++++++++++++++++++
.../bindings/dma/xilinx/zynqmp_dma.txt | 26 ------
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 +++++++----
3 files changed, 117 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
--
2.30.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
@ 2022-01-12 15:15 ` Michael Tretter
2022-01-22 0:59 ` Rob Herring
2022-01-12 15:15 ` [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property Michael Tretter
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Michael Tretter @ 2022-01-12 15:15 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, m.tretter, kernel
Convert the Xilinx ZynqMP DMA engine bindings to Yaml.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
.../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 85 +++++++++++++++++++
.../bindings/dma/xilinx/zynqmp_dma.txt | 26 ------
2 files changed, 85 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
new file mode 100644
index 000000000000..c0a1408b12ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP DMA Engine
+
+description: |
+ The Xilinx ZynqMP DMA engine supports memory to memory transfers,
+ memory to device and device to memory transfers. It also has flow
+ control and rate control support for slave/peripheral dma access.
+
+maintainers:
+ - Michael Tretter <m.tretter@pengutronix.de>
+
+allOf:
+ - $ref: "../dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+
+ compatible:
+ const: xlnx,zynqmp-dma-1.0
+
+ reg:
+ description: memory map for gdma/adma module access
+ maxItems: 1
+
+ interrupts:
+ description: DMA channel interrupt
+ maxItems: 1
+
+ clocks:
+ description: input clocks
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: clk_main
+ - const: clk_apb
+
+ xlnx,bus-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 64
+ - 128
+ description: AXI bus width in bits
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dma-coherent:
+ description: present if dma operations are coherent
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+
+ fpd_dma_chan1: dma-controller@fd500000 {
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0xfd500000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 117 0x4>;
+ #dma-cells = <1>;
+ clock-names = "clk_main", "clk_apb";
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+ xlnx,bus-width = <128>;
+ dma-coherent;
+ };
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
deleted file mode 100644
index 07a5a7aa9ea0..000000000000
--- a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
-memory to device and device to memory transfers. It also has flow
-control and rate control support for slave/peripheral dma access.
-
-Required properties:
-- compatible : Should be "xlnx,zynqmp-dma-1.0"
-- reg : Memory map for gdma/adma module access.
-- interrupts : Should contain DMA channel interrupt.
-- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
-- clock-names : List of input clocks "clk_main", "clk_apb"
- (see clock bindings for details)
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent.
-
-Example:
-++++++++
-fpd_dma_chan1: dma@fd500000 {
- compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xFD500000 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <0 117 4>;
- clock-names = "clk_main", "clk_apb";
- xlnx,bus-width = <128>;
- dma-coherent;
-};
--
2.30.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
2022-01-12 15:15 ` [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml Michael Tretter
@ 2022-01-12 15:15 ` Michael Tretter
2022-01-24 12:18 ` Michal Simek
2022-01-12 15:15 ` [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller Michael Tretter
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Michael Tretter @ 2022-01-12 15:15 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, m.tretter, kernel
Requesting the dma controllers fails if #dma-cells is not defined. Add
the missing property.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 493719f71fb5..6d96b6b99f84 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -261,6 +261,7 @@ fpd_dma_chan1: dma@fd500000 {
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -273,6 +274,7 @@ fpd_dma_chan2: dma@fd510000 {
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -285,6 +287,7 @@ fpd_dma_chan3: dma@fd520000 {
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -297,6 +300,7 @@ fpd_dma_chan4: dma@fd530000 {
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -309,6 +313,7 @@ fpd_dma_chan5: dma@fd540000 {
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -321,6 +326,7 @@ fpd_dma_chan6: dma@fd550000 {
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -333,6 +339,7 @@ fpd_dma_chan7: dma@fd560000 {
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -345,6 +352,7 @@ fpd_dma_chan8: dma@fd570000 {
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
@@ -374,6 +382,7 @@ lpd_dma_chan1: dma@ffa80000 {
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x868>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -386,6 +395,7 @@ lpd_dma_chan2: dma@ffa90000 {
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x869>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -398,6 +408,7 @@ lpd_dma_chan3: dma@ffaa0000 {
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86a>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -410,6 +421,7 @@ lpd_dma_chan4: dma@ffab0000 {
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86b>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -422,6 +434,7 @@ lpd_dma_chan5: dma@ffac0000 {
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86c>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -434,6 +447,7 @@ lpd_dma_chan6: dma@ffad0000 {
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86d>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -446,6 +460,7 @@ lpd_dma_chan7: dma@ffae0000 {
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86e>;
power-domains = <&zynqmp_firmware PD_ADMA>;
@@ -458,6 +473,7 @@ lpd_dma_chan8: dma@ffaf0000 {
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86f>;
power-domains = <&zynqmp_firmware PD_ADMA>;
--
2.30.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
2022-01-12 15:15 ` [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml Michael Tretter
2022-01-12 15:15 ` [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property Michael Tretter
@ 2022-01-12 15:15 ` Michael Tretter
2022-01-24 12:18 ` Michal Simek
2022-01-21 10:16 ` [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Harini Katakam
2022-01-21 11:58 ` Michal Simek
4 siblings, 1 reply; 9+ messages in thread
From: Michael Tretter @ 2022-01-12 15:15 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, m.tretter, kernel
The ZynqMP dma engines are actually dma-controllers as specified by the
device tree binding. Rename the device tree nodes accordingly.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 +++++++++++++-------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 6d96b6b99f84..3e15391e5b37 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -254,7 +254,7 @@ pmu@9000 {
};
/* GDMA */
- fpd_dma_chan1: dma@fd500000 {
+ fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
@@ -267,7 +267,7 @@ fpd_dma_chan1: dma@fd500000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan2: dma@fd510000 {
+ fpd_dma_chan2: dma-controller@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
@@ -280,7 +280,7 @@ fpd_dma_chan2: dma@fd510000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan3: dma@fd520000 {
+ fpd_dma_chan3: dma-controller@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
@@ -293,7 +293,7 @@ fpd_dma_chan3: dma@fd520000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan4: dma@fd530000 {
+ fpd_dma_chan4: dma-controller@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
@@ -306,7 +306,7 @@ fpd_dma_chan4: dma@fd530000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan5: dma@fd540000 {
+ fpd_dma_chan5: dma-controller@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
@@ -319,7 +319,7 @@ fpd_dma_chan5: dma@fd540000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan6: dma@fd550000 {
+ fpd_dma_chan6: dma-controller@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
@@ -332,7 +332,7 @@ fpd_dma_chan6: dma@fd550000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan7: dma@fd560000 {
+ fpd_dma_chan7: dma-controller@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
@@ -345,7 +345,7 @@ fpd_dma_chan7: dma@fd560000 {
power-domains = <&zynqmp_firmware PD_GDMA>;
};
- fpd_dma_chan8: dma@fd570000 {
+ fpd_dma_chan8: dma-controller@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
@@ -375,7 +375,7 @@ gic: interrupt-controller@f9010000 {
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
- lpd_dma_chan1: dma@ffa80000 {
+ lpd_dma_chan1: dma-controller@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
@@ -388,7 +388,7 @@ lpd_dma_chan1: dma@ffa80000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan2: dma@ffa90000 {
+ lpd_dma_chan2: dma-controller@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
@@ -401,7 +401,7 @@ lpd_dma_chan2: dma@ffa90000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan3: dma@ffaa0000 {
+ lpd_dma_chan3: dma-controller@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
@@ -414,7 +414,7 @@ lpd_dma_chan3: dma@ffaa0000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan4: dma@ffab0000 {
+ lpd_dma_chan4: dma-controller@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
@@ -427,7 +427,7 @@ lpd_dma_chan4: dma@ffab0000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan5: dma@ffac0000 {
+ lpd_dma_chan5: dma-controller@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
@@ -440,7 +440,7 @@ lpd_dma_chan5: dma@ffac0000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan6: dma@ffad0000 {
+ lpd_dma_chan6: dma-controller@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
@@ -453,7 +453,7 @@ lpd_dma_chan6: dma@ffad0000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan7: dma@ffae0000 {
+ lpd_dma_chan7: dma-controller@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
@@ -466,7 +466,7 @@ lpd_dma_chan7: dma@ffae0000 {
power-domains = <&zynqmp_firmware PD_ADMA>;
};
- lpd_dma_chan8: dma@ffaf0000 {
+ lpd_dma_chan8: dma-controller@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
--
2.30.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
` (2 preceding siblings ...)
2022-01-12 15:15 ` [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller Michael Tretter
@ 2022-01-21 10:16 ` Harini Katakam
2022-01-21 11:58 ` Michal Simek
4 siblings, 0 replies; 9+ messages in thread
From: Harini Katakam @ 2022-01-21 10:16 UTC (permalink / raw)
To: Michael Tretter
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, dmaengine, Rob Herring, Michal Simek, kernel
Hi Michael,
On Thu, Jan 13, 2022 at 4:52 AM Michael Tretter
<m.tretter@pengutronix.de> wrote:
>
> Hi,
>
> This series converts the ZynqMP dma engine dt bindings to yaml and fixes the
> ZynqMP device tree following the stricter yaml bindings.
>
> The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt to
> avoid conflicts when applying the patches to the zynqmp/dt tree.
>
> Patch 1 converts the binding to yaml, Patches 2 and 3 cleanup the dma engine
> nodes in the zynqmp.dtsi that is included by actual board device trees.
Thanks for the series Michael.
Reviewed-by: Harini Katakam <harini.katakam@xilinx.com>
Regards,
Harini
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
` (3 preceding siblings ...)
2022-01-21 10:16 ` [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Harini Katakam
@ 2022-01-21 11:58 ` Michal Simek
4 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2022-01-21 11:58 UTC (permalink / raw)
To: Michael Tretter, devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, kernel
On 1/12/22 16:15, Michael Tretter wrote:
> Hi,
>
> This series converts the ZynqMP dma engine dt bindings to yaml and fixes the
> ZynqMP device tree following the stricter yaml bindings.
>
> The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt to
> avoid conflicts when applying the patches to the zynqmp/dt tree.
>
> Patch 1 converts the binding to yaml, Patches 2 and 3 cleanup the dma engine
> nodes in the zynqmp.dtsi that is included by actual board device trees.
>
> Michael
>
> Michael Tretter (3):
> dt-bindings: dmaengine: zynqmp_dma: convert to yaml
> arm64: zynqmp: Add missing #dma-cells property
> arm64: zynqmp: Rename dma to dma-controller
>
> .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 85 +++++++++++++++++++
> .../bindings/dma/xilinx/zynqmp_dma.txt | 26 ------
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 +++++++----
> 3 files changed, 117 insertions(+), 42 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
> delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>
Rob/Vinod:
Not sure how you want to split it but feel free to take 2/3 and 3/3 via your
tree with my ack.
Acked-by: Michal Simek <michal.simek@xilinx.com>
If you want to take just 1/3 I will take the rest via my soc tree.
Thanks,
Michal
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml
2022-01-12 15:15 ` [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml Michael Tretter
@ 2022-01-22 0:59 ` Rob Herring
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-01-22 0:59 UTC (permalink / raw)
To: Michael Tretter
Cc: robh+dt, michal.simek, devicetree, linux-arm-kernel, kernel, dmaengine
On Wed, 12 Jan 2022 16:15:39 +0100, Michael Tretter wrote:
> Convert the Xilinx ZynqMP DMA engine bindings to Yaml.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 85 +++++++++++++++++++
> .../bindings/dma/xilinx/zynqmp_dma.txt | 26 ------
> 2 files changed, 85 insertions(+), 26 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
> delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>
Applied, thanks!
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property
2022-01-12 15:15 ` [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property Michael Tretter
@ 2022-01-24 12:18 ` Michal Simek
0 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2022-01-24 12:18 UTC (permalink / raw)
To: Michael Tretter, devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, kernel
On 1/12/22 16:15, Michael Tretter wrote:
> Requesting the dma controllers fails if #dma-cells is not defined. Add
> the missing property.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 493719f71fb5..6d96b6b99f84 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -261,6 +261,7 @@ fpd_dma_chan1: dma@fd500000 {
> interrupt-parent = <&gic>;
> interrupts = <0 124 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14e8>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -273,6 +274,7 @@ fpd_dma_chan2: dma@fd510000 {
> interrupt-parent = <&gic>;
> interrupts = <0 125 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14e9>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -285,6 +287,7 @@ fpd_dma_chan3: dma@fd520000 {
> interrupt-parent = <&gic>;
> interrupts = <0 126 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ea>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -297,6 +300,7 @@ fpd_dma_chan4: dma@fd530000 {
> interrupt-parent = <&gic>;
> interrupts = <0 127 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14eb>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -309,6 +313,7 @@ fpd_dma_chan5: dma@fd540000 {
> interrupt-parent = <&gic>;
> interrupts = <0 128 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ec>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -321,6 +326,7 @@ fpd_dma_chan6: dma@fd550000 {
> interrupt-parent = <&gic>;
> interrupts = <0 129 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ed>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -333,6 +339,7 @@ fpd_dma_chan7: dma@fd560000 {
> interrupt-parent = <&gic>;
> interrupts = <0 130 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ee>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -345,6 +352,7 @@ fpd_dma_chan8: dma@fd570000 {
> interrupt-parent = <&gic>;
> interrupts = <0 131 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ef>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -374,6 +382,7 @@ lpd_dma_chan1: dma@ffa80000 {
> interrupt-parent = <&gic>;
> interrupts = <0 77 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x868>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -386,6 +395,7 @@ lpd_dma_chan2: dma@ffa90000 {
> interrupt-parent = <&gic>;
> interrupts = <0 78 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x869>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -398,6 +408,7 @@ lpd_dma_chan3: dma@ffaa0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 79 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86a>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -410,6 +421,7 @@ lpd_dma_chan4: dma@ffab0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 80 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86b>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -422,6 +434,7 @@ lpd_dma_chan5: dma@ffac0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 81 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86c>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -434,6 +447,7 @@ lpd_dma_chan6: dma@ffad0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 82 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86d>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -446,6 +460,7 @@ lpd_dma_chan7: dma@ffae0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 83 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86e>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -458,6 +473,7 @@ lpd_dma_chan8: dma@ffaf0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 84 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86f>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
Applied.
M
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller
2022-01-12 15:15 ` [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller Michael Tretter
@ 2022-01-24 12:18 ` Michal Simek
0 siblings, 0 replies; 9+ messages in thread
From: Michal Simek @ 2022-01-24 12:18 UTC (permalink / raw)
To: Michael Tretter, devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, kernel
On 1/12/22 16:15, Michael Tretter wrote:
> The ZynqMP dma engines are actually dma-controllers as specified by the
> device tree binding. Rename the device tree nodes accordingly.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 +++++++++++++-------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 6d96b6b99f84..3e15391e5b37 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -254,7 +254,7 @@ pmu@9000 {
> };
>
> /* GDMA */
> - fpd_dma_chan1: dma@fd500000 {
> + fpd_dma_chan1: dma-controller@fd500000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd500000 0x0 0x1000>;
> @@ -267,7 +267,7 @@ fpd_dma_chan1: dma@fd500000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan2: dma@fd510000 {
> + fpd_dma_chan2: dma-controller@fd510000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd510000 0x0 0x1000>;
> @@ -280,7 +280,7 @@ fpd_dma_chan2: dma@fd510000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan3: dma@fd520000 {
> + fpd_dma_chan3: dma-controller@fd520000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd520000 0x0 0x1000>;
> @@ -293,7 +293,7 @@ fpd_dma_chan3: dma@fd520000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan4: dma@fd530000 {
> + fpd_dma_chan4: dma-controller@fd530000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd530000 0x0 0x1000>;
> @@ -306,7 +306,7 @@ fpd_dma_chan4: dma@fd530000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan5: dma@fd540000 {
> + fpd_dma_chan5: dma-controller@fd540000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd540000 0x0 0x1000>;
> @@ -319,7 +319,7 @@ fpd_dma_chan5: dma@fd540000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan6: dma@fd550000 {
> + fpd_dma_chan6: dma-controller@fd550000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd550000 0x0 0x1000>;
> @@ -332,7 +332,7 @@ fpd_dma_chan6: dma@fd550000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan7: dma@fd560000 {
> + fpd_dma_chan7: dma-controller@fd560000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd560000 0x0 0x1000>;
> @@ -345,7 +345,7 @@ fpd_dma_chan7: dma@fd560000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan8: dma@fd570000 {
> + fpd_dma_chan8: dma-controller@fd570000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd570000 0x0 0x1000>;
> @@ -375,7 +375,7 @@ gic: interrupt-controller@f9010000 {
> * These dma channels, Users should ensure that these dma
> * Channels are allowed for non secure access.
> */
> - lpd_dma_chan1: dma@ffa80000 {
> + lpd_dma_chan1: dma-controller@ffa80000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa80000 0x0 0x1000>;
> @@ -388,7 +388,7 @@ lpd_dma_chan1: dma@ffa80000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan2: dma@ffa90000 {
> + lpd_dma_chan2: dma-controller@ffa90000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa90000 0x0 0x1000>;
> @@ -401,7 +401,7 @@ lpd_dma_chan2: dma@ffa90000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan3: dma@ffaa0000 {
> + lpd_dma_chan3: dma-controller@ffaa0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaa0000 0x0 0x1000>;
> @@ -414,7 +414,7 @@ lpd_dma_chan3: dma@ffaa0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan4: dma@ffab0000 {
> + lpd_dma_chan4: dma-controller@ffab0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffab0000 0x0 0x1000>;
> @@ -427,7 +427,7 @@ lpd_dma_chan4: dma@ffab0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan5: dma@ffac0000 {
> + lpd_dma_chan5: dma-controller@ffac0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffac0000 0x0 0x1000>;
> @@ -440,7 +440,7 @@ lpd_dma_chan5: dma@ffac0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan6: dma@ffad0000 {
> + lpd_dma_chan6: dma-controller@ffad0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffad0000 0x0 0x1000>;
> @@ -453,7 +453,7 @@ lpd_dma_chan6: dma@ffad0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan7: dma@ffae0000 {
> + lpd_dma_chan7: dma-controller@ffae0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffae0000 0x0 0x1000>;
> @@ -466,7 +466,7 @@ lpd_dma_chan7: dma@ffae0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan8: dma@ffaf0000 {
> + lpd_dma_chan8: dma-controller@ffaf0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaf0000 0x0 0x1000>;
Applied.
M
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-01-24 12:18 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-12 15:15 [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Michael Tretter
2022-01-12 15:15 ` [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml Michael Tretter
2022-01-22 0:59 ` Rob Herring
2022-01-12 15:15 ` [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property Michael Tretter
2022-01-24 12:18 ` Michal Simek
2022-01-12 15:15 ` [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller Michael Tretter
2022-01-24 12:18 ` Michal Simek
2022-01-21 10:16 ` [PATCH 0/3] dt-bindings: dmaengine: zynqmp_dma: Convert binding to YAML Harini Katakam
2022-01-21 11:58 ` Michal Simek
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