* [PATCH v3 0/4] Add RZ/G2L MTU3a MFD, Counter and pwm driver
@ 2022-10-06 13:57 Biju Das
2022-10-06 13:57 ` [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
0 siblings, 1 reply; 12+ messages in thread
From: Biju Das @ 2022-10-06 13:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, William Breathitt Gray, Thierry Reding
Cc: Biju Das, Lee Jones, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
This patch series aim to add MFD and pwm driver for MTU3a.
The 8/16/32 bit registers are mixed in each channel. The HW
specifications of the IP is described in patch#1.
Current patch set is tested for PWM mode1 on MTU3 channel
and 16 and 32 bit phase counting modes.
v2->v3:
* Dropped counter bindings and integrated with mfd as it has only one property.
* Removed "#address-cells" and "#size-cells" as it do not have children with
unit addresses.
* Removed quotes from counter and pwm.
* Provided full path for pwm bindings.
* Updated the binding example.
* removed unwanted header files
* Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
* Exported 32 bit read/write functions.
* Modelled as a counter device supporting 3 counters(2 16-bit and
32-bit)
* Add kernel-doc comments to document struct rz_mtu3_cnt
* Removed mmio variable from struct rz_mtu3_cnt
* Removed cnt local variable from rz_mtu3_count_read()
* Replaced -EINVAL->-ERANGE for out of range error conditions.
* Removed explicit cast from write functions.
* Removed local variable val from rz_mtu3_count_ceiling_read()
* Added lock for RMW for counter/ceiling updates.
* Added different synapses for counter0 and counter{1,2}
* Used ARRAY for assigning num_counts.
* Added PM runtime for managing clocks.
* Add MODULE_IMPORT_NS(COUNTER) to import the COUNTER namespace.
RFC->v2:
* replaced devm_reset_control_get->devm_reset_control_get_exclusive
* Dropped 'bindings' from the binding title
* Updated the binding example
* Added additionalProperties: false for counter bindings
* Squashed all the binding patches
* Modelled as a single counter device providing both 16-bit
and 32-bit phase counting modes
* Modelled as a single pwm device for supporting different pwm modes.
* Moved counter and pwm bindings to respective subsystems.
Biju Das (4):
dt-bindings: mfd: Document RZ/G2L MTU3a bindings
mfd: Add RZ/G2L MTU3 driver
pwm: Add support for RZ/G2L MTU3 PWM
counter: Add RZ/G2L MTU3 counter driver
.../bindings/mfd/renesas,rz-mtu3.yaml | 304 ++++++++++
.../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 ++
drivers/counter/Kconfig | 9 +
drivers/counter/Makefile | 1 +
drivers/counter/rz-mtu3-cnt.c | 568 ++++++++++++++++++
drivers/mfd/Kconfig | 9 +
drivers/mfd/Makefile | 1 +
drivers/mfd/rz-mtu3.c | 436 ++++++++++++++
drivers/pwm/Kconfig | 11 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rz-mtu3.c | 462 ++++++++++++++
include/linux/mfd/rz-mtu3.h | 183 ++++++
12 files changed, 2035 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
create mode 100644 drivers/counter/rz-mtu3-cnt.c
create mode 100644 drivers/mfd/rz-mtu3.c
create mode 100644 drivers/pwm/pwm-rz-mtu3.c
create mode 100644 include/linux/mfd/rz-mtu3.h
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-06 13:57 [PATCH v3 0/4] Add RZ/G2L MTU3a MFD, Counter and pwm driver Biju Das
@ 2022-10-06 13:57 ` Biju Das
2022-10-06 20:17 ` Rob Herring
0 siblings, 1 reply; 12+ messages in thread
From: Biju Das @ 2022-10-06 13:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, William Breathitt Gray, Thierry Reding
Cc: Biju Das, Lee Jones, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* Dropped counter bindings and integrated with mfd as it has only one property.
* Removed "#address-cells" and "#size-cells" as it do not have children with
unit addresses.
* Removed quotes from counter and pwm.
* Provided full path for pwm bindings.
* Updated the example.
v1->v2:
* Modelled counter and pwm as a single device that handles
multiple channels.
* Moved counter and pwm bindings to respective subsystems
* Dropped 'bindings' from MFD binding title.
* Updated the example
* Changed the compatible names.
---
.../bindings/mfd/renesas,rz-mtu3.yaml | 304 ++++++++++++++++++
.../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
2 files changed, 354 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
new file mode 100644
index 000000000000..44c952ad8d35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
@@ -0,0 +1,304 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/renesas,rz-mtu3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This hardware block pconsisting of eight 16-bit timer channels and one
+ 32- bit timer channel. It supports the following specifications:
+ - Pulse input/output: 28 lines max.
+ - Pulse input 3 lines
+ - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
+ for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
+ (when LWA = 1))
+ - Operating frequency Up to 100 MHz
+ - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
+ - Waveform output on compare match
+ - Input capture function (noise filter setting available)
+ - Counter-clearing operation
+ - Simultaneous writing to multiple timer counters (TCNT)
+ (excluding MTU8).
+ - Simultaneous clearing on compare match or input capture
+ (excluding MTU8).
+ - Simultaneous input and output to registers in synchronization with
+ counter operations (excluding MTU8).
+ - Up to 12-phase PWM output in combination with synchronous operation
+ (excluding MTU8)
+ - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
+ - Buffer operation specifiable
+ - [MTU1, MTU2]
+ - Phase counting mode can be specified independently
+ - 32-bit phase counting mode can be specified for interlocked operation
+ of MTU1 and MTU2 (when TMDR3.LWA = 1)
+ - Cascade connection operation available
+ - [MTU3, MTU4, MTU6, and MTU7]
+ - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
+ negative signals in six phases (12 phases in total) can be output in
+ complementary PWM and reset-synchronized PWM operation.
+ - In complementary PWM mode, values can be transferred from buffer
+ registers to temporary registers at crests and troughs of the timer-
+ counter values or when the buffer registers (TGRD registers in MTU4
+ and MTU7) are written to.
+ - Double-buffering selectable in complementary PWM mode.
+ - [MTU3 and MTU4]
+ - Through interlocking with MTU0, a mode for driving AC synchronous
+ motors (brushless DC motors) by using complementary PWM output and
+ reset-synchronized PWM output is settable and allows the selection
+ of two types of waveform output (chopping or level).
+ - [MTU5]
+ - Capable of operation as a dead-time compensation counter.
+ - [MTU0/MTU5, MTU1, MTU2, and MTU8]
+ - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
+ through interlocked operation with MTU0/MTU5 and MTU8.
+ - Interrupt-skipping function
+ - In complementary PWM mode, interrupts on crests and troughs of counter
+ values and triggers to start conversion by the A/D converter can be
+ skipped.
+ - Interrupt sources: 43 sources.
+ - Buffer operation:
+ - Automatic transfer of register data (transfer from the buffer
+ register to the timer register).
+ - Trigger generation
+ - A/D converter start triggers can be generated
+ - A/D converter start request delaying function enables A/D converter
+ to be started with any desired timing and to be synchronized with
+ PWM output.
+ - Low power consumption function
+ - The MTU3a can be placed in the module-stop state.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
+ - renesas,r9a07g054-mtu3 # RZ/V2L
+ - const: renesas,rz-mtu3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: MTU0.TGRA input capture/compare match
+ - description: MTU0.TGRB input capture/compare match
+ - description: MTU0.TGRC input capture/compare match
+ - description: MTU0.TGRD input capture/compare match
+ - description: MTU0.TCNT overflow
+ - description: MTU0.TGRE compare match
+ - description: MTU0.TGRF compare match
+ - description: MTU1.TGRA input capture/compare match
+ - description: MTU1.TGRB input capture/compare match
+ - description: MTU1.TCNT overflow
+ - description: MTU1.TCNT underflow
+ - description: MTU2.TGRA input capture/compare match
+ - description: MTU2.TGRB input capture/compare match
+ - description: MTU2.TCNT overflow
+ - description: MTU2.TCNT underflow
+ - description: MTU3.TGRA input capture/compare match
+ - description: MTU3.TGRB input capture/compare match
+ - description: MTU3.TGRC input capture/compare match
+ - description: MTU3.TGRD input capture/compare match
+ - description: MTU3.TCNT overflow
+ - description: MTU4.TGRA input capture/compare match
+ - description: MTU4.TGRB input capture/compare match
+ - description: MTU4.TGRC input capture/compare match
+ - description: MTU4.TGRD input capture/compare match
+ - description: MTU4.TCNT overflow/underflow
+ - description: MTU5.TGRU input capture/compare match
+ - description: MTU5.TGRV input capture/compare match
+ - description: MTU5.TGRW input capture/compare match
+ - description: MTU6.TGRA input capture/compare match
+ - description: MTU6.TGRB input capture/compare match
+ - description: MTU6.TGRC input capture/compare match
+ - description: MTU6.TGRD input capture/compare match
+ - description: MTU6.TCNT overflow
+ - description: MTU7.TGRA input capture/compare match
+ - description: MTU7.TGRB input capture/compare match
+ - description: MTU7.TGRC input capture/compare match
+ - description: MTU7.TGRD input capture/compare match
+ - description: MTU7.TCNT overflow/underflow
+ - description: MTU8.TGRA input capture/compare match
+ - description: MTU8.TGRB input capture/compare match
+ - description: MTU8.TGRC input capture/compare match
+ - description: MTU8.TGRD input capture/compare match
+ - description: MTU8.TCNT overflow
+ - description: MTU8.TCNT underflow
+
+ interrupt-names:
+ items:
+ - const: tgia0
+ - const: tgib0
+ - const: tgic0
+ - const: tgid0
+ - const: tgiv0
+ - const: tgie0
+ - const: tgif0
+ - const: tgia1
+ - const: tgib1
+ - const: tgiv1
+ - const: tgiu1
+ - const: tgia2
+ - const: tgib2
+ - const: tgiv2
+ - const: tgiu2
+ - const: tgia3
+ - const: tgib3
+ - const: tgic3
+ - const: tgid3
+ - const: tgiv3
+ - const: tgia4
+ - const: tgib4
+ - const: tgic4
+ - const: tgid4
+ - const: tgiv4
+ - const: tgiu5
+ - const: tgiv5
+ - const: tgiw5
+ - const: tgia6
+ - const: tgib6
+ - const: tgic6
+ - const: tgid6
+ - const: tgiv6
+ - const: tgia7
+ - const: tgib7
+ - const: tgic7
+ - const: tgid7
+ - const: tgiv7
+ - const: tgia8
+ - const: tgib8
+ - const: tgic8
+ - const: tgid8
+ - const: tgiv8
+ - const: tgiu8
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ counter:
+ description:
+ There are two phase counting modes. 16-bit phase counting mode in which
+ MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
+ counting mode in which MTU1 and MTU2 are cascaded.
+
+ In phase counting mode, the phase difference between two external input
+ clocks is detected and the corresponding TCNT is incremented or
+ decremented.
+ The below counters are supported
+ count0 - MTU1 16-bit phase counting
+ count1 - MTU2 16-bit phase counting
+ count2 - MTU1+ MTU2 32-bit phase counting
+
+ type: object
+
+ properties:
+ compatible:
+ const: renesas,rz-mtu3-counter
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+ pwm:
+ $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
+ reg = <0x10001200 0xb00>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+ "tgif0",
+ "tgia1", "tgib1", "tgiv1", "tgiu1",
+ "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
+ "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
+ "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
+ "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+ clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+
+ counter {
+ compatible = "renesas,rz-mtu3-counter";
+ };
+
+ pwm {
+ compatible = "renesas,rz-mtu3-pwm";
+ #pwm-cells = <2>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
new file mode 100644
index 000000000000..29d7d0fdf7f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rz-mtu3-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PWM driver for the RZ/G2L multi-function timer pulse unit 3 (MTU3a)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This module is part of the RZ/G2L MTU3a multi-function device. For more
+ details see ../mfd/renesas,rz-mtu3.yaml.
+
+ The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
+ complementary PWM mode{1,2,3}.
+
+ In complementary PWM mode, six positive-phase and six negative-phase PWM
+ waveforms (12 phases in total) with dead time can be output by
+ combining MTU{3,4} and MTU{6,7}.
+
+ The pwm channels corresponding to each hardware channels.
+ 0 - MTU0.MTIOC0A PWM mode 1
+ 1 - MTU0.MTIOC0C PWM mode 1
+ 2 - MTU1.MTIOC1A PWM mode 1
+ 3 - MTU2.MTIOC2A PWM mode 1
+ 4 - MTU3.MTIOC3A PWM mode 1
+ 5 - MTU3.MTIOC3C PWM mode 1
+ 6 - MTU4.MTIOC4A PWM mode 1
+ 7 - MTU4.MTIOC4C PWM mode 1
+ 8 - MTU6.MTIOC6A PWM mode 1
+ 9 - MTU6.MTIOC6C PWM mode 1
+ 10 - MTU7.MTIOC7A PWM mode 1
+ 11 - MTU7.MTIOC7C PWM mode 1
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: renesas,rz-mtu3-pwm
+
+ "#pwm-cells":
+ const: 2
+
+required:
+ - compatible
+
+additionalProperties: false
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-06 13:57 ` [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
@ 2022-10-06 20:17 ` Rob Herring
2022-10-07 12:40 ` Biju Das
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2022-10-06 20:17 UTC (permalink / raw)
To: Biju Das
Cc: Krzysztof Kozlowski, William Breathitt Gray, Thierry Reding,
Lee Jones, Uwe Kleine-König, devicetree, linux-pwm,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> channels and one 32-bit timer channel. It supports the following
> functions
> - Counter
> - Timer
> - PWM
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
> * Dropped counter bindings and integrated with mfd as it has only one property.
> * Removed "#address-cells" and "#size-cells" as it do not have children with
> unit addresses.
> * Removed quotes from counter and pwm.
> * Provided full path for pwm bindings.
> * Updated the example.
> v1->v2:
> * Modelled counter and pwm as a single device that handles
> multiple channels.
> * Moved counter and pwm bindings to respective subsystems
> * Dropped 'bindings' from MFD binding title.
> * Updated the example
> * Changed the compatible names.
> ---
> .../bindings/mfd/renesas,rz-mtu3.yaml | 304 ++++++++++++++++++
> .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> 2 files changed, 354 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> new file mode 100644
> index 000000000000..44c952ad8d35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> @@ -0,0 +1,304 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/renesas,rz-mtu3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> + This hardware block pconsisting of eight 16-bit timer channels and one
> + 32- bit timer channel. It supports the following specifications:
> + - Pulse input/output: 28 lines max.
> + - Pulse input 3 lines
> + - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
> + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
> + (when LWA = 1))
> + - Operating frequency Up to 100 MHz
> + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> + - Waveform output on compare match
> + - Input capture function (noise filter setting available)
> + - Counter-clearing operation
> + - Simultaneous writing to multiple timer counters (TCNT)
> + (excluding MTU8).
> + - Simultaneous clearing on compare match or input capture
> + (excluding MTU8).
> + - Simultaneous input and output to registers in synchronization with
> + counter operations (excluding MTU8).
> + - Up to 12-phase PWM output in combination with synchronous operation
> + (excluding MTU8)
> + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> + - Buffer operation specifiable
> + - [MTU1, MTU2]
> + - Phase counting mode can be specified independently
> + - 32-bit phase counting mode can be specified for interlocked operation
> + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> + - Cascade connection operation available
> + - [MTU3, MTU4, MTU6, and MTU7]
> + - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
> + negative signals in six phases (12 phases in total) can be output in
> + complementary PWM and reset-synchronized PWM operation.
> + - In complementary PWM mode, values can be transferred from buffer
> + registers to temporary registers at crests and troughs of the timer-
> + counter values or when the buffer registers (TGRD registers in MTU4
> + and MTU7) are written to.
> + - Double-buffering selectable in complementary PWM mode.
> + - [MTU3 and MTU4]
> + - Through interlocking with MTU0, a mode for driving AC synchronous
> + motors (brushless DC motors) by using complementary PWM output and
> + reset-synchronized PWM output is settable and allows the selection
> + of two types of waveform output (chopping or level).
> + - [MTU5]
> + - Capable of operation as a dead-time compensation counter.
> + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> + - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
> + through interlocked operation with MTU0/MTU5 and MTU8.
> + - Interrupt-skipping function
> + - In complementary PWM mode, interrupts on crests and troughs of counter
> + values and triggers to start conversion by the A/D converter can be
> + skipped.
> + - Interrupt sources: 43 sources.
> + - Buffer operation:
> + - Automatic transfer of register data (transfer from the buffer
> + register to the timer register).
> + - Trigger generation
> + - A/D converter start triggers can be generated
> + - A/D converter start request delaying function enables A/D converter
> + to be started with any desired timing and to be synchronized with
> + PWM output.
> + - Low power consumption function
> + - The MTU3a can be placed in the module-stop state.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> + - renesas,r9a07g054-mtu3 # RZ/V2L
> + - const: renesas,rz-mtu3
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: MTU0.TGRA input capture/compare match
> + - description: MTU0.TGRB input capture/compare match
> + - description: MTU0.TGRC input capture/compare match
> + - description: MTU0.TGRD input capture/compare match
> + - description: MTU0.TCNT overflow
> + - description: MTU0.TGRE compare match
> + - description: MTU0.TGRF compare match
> + - description: MTU1.TGRA input capture/compare match
> + - description: MTU1.TGRB input capture/compare match
> + - description: MTU1.TCNT overflow
> + - description: MTU1.TCNT underflow
> + - description: MTU2.TGRA input capture/compare match
> + - description: MTU2.TGRB input capture/compare match
> + - description: MTU2.TCNT overflow
> + - description: MTU2.TCNT underflow
> + - description: MTU3.TGRA input capture/compare match
> + - description: MTU3.TGRB input capture/compare match
> + - description: MTU3.TGRC input capture/compare match
> + - description: MTU3.TGRD input capture/compare match
> + - description: MTU3.TCNT overflow
> + - description: MTU4.TGRA input capture/compare match
> + - description: MTU4.TGRB input capture/compare match
> + - description: MTU4.TGRC input capture/compare match
> + - description: MTU4.TGRD input capture/compare match
> + - description: MTU4.TCNT overflow/underflow
> + - description: MTU5.TGRU input capture/compare match
> + - description: MTU5.TGRV input capture/compare match
> + - description: MTU5.TGRW input capture/compare match
> + - description: MTU6.TGRA input capture/compare match
> + - description: MTU6.TGRB input capture/compare match
> + - description: MTU6.TGRC input capture/compare match
> + - description: MTU6.TGRD input capture/compare match
> + - description: MTU6.TCNT overflow
> + - description: MTU7.TGRA input capture/compare match
> + - description: MTU7.TGRB input capture/compare match
> + - description: MTU7.TGRC input capture/compare match
> + - description: MTU7.TGRD input capture/compare match
> + - description: MTU7.TCNT overflow/underflow
> + - description: MTU8.TGRA input capture/compare match
> + - description: MTU8.TGRB input capture/compare match
> + - description: MTU8.TGRC input capture/compare match
> + - description: MTU8.TGRD input capture/compare match
> + - description: MTU8.TCNT overflow
> + - description: MTU8.TCNT underflow
> +
> + interrupt-names:
> + items:
> + - const: tgia0
> + - const: tgib0
> + - const: tgic0
> + - const: tgid0
> + - const: tgiv0
> + - const: tgie0
> + - const: tgif0
> + - const: tgia1
> + - const: tgib1
> + - const: tgiv1
> + - const: tgiu1
> + - const: tgia2
> + - const: tgib2
> + - const: tgiv2
> + - const: tgiu2
> + - const: tgia3
> + - const: tgib3
> + - const: tgic3
> + - const: tgid3
> + - const: tgiv3
> + - const: tgia4
> + - const: tgib4
> + - const: tgic4
> + - const: tgid4
> + - const: tgiv4
> + - const: tgiu5
> + - const: tgiv5
> + - const: tgiw5
> + - const: tgia6
> + - const: tgib6
> + - const: tgic6
> + - const: tgid6
> + - const: tgiv6
> + - const: tgia7
> + - const: tgib7
> + - const: tgic7
> + - const: tgid7
> + - const: tgiv7
> + - const: tgia8
> + - const: tgib8
> + - const: tgic8
> + - const: tgid8
> + - const: tgiv8
> + - const: tgiu8
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + counter:
> + description:
> + There are two phase counting modes. 16-bit phase counting mode in which
> + MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
> + counting mode in which MTU1 and MTU2 are cascaded.
> +
> + In phase counting mode, the phase difference between two external input
> + clocks is detected and the corresponding TCNT is incremented or
> + decremented.
> + The below counters are supported
> + count0 - MTU1 16-bit phase counting
> + count1 - MTU2 16-bit phase counting
> + count2 - MTU1+ MTU2 32-bit phase counting
> +
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rz-mtu3-counter
> +
> + required:
> + - compatible
> +
> + additionalProperties: false
> +
> + pwm:
> + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - power-domains
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + mtu3: timer@10001200 {
> + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
> + reg = <0x10001200 0xb00>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
> + "tgif0",
> + "tgia1", "tgib1", "tgiv1", "tgiu1",
> + "tgia2", "tgib2", "tgiv2", "tgiu2",
> + "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
> + "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
> + "tgiu5", "tgiv5", "tgiw5",
> + "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
> + "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
> + "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
> + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> +
> + counter {
> + compatible = "renesas,rz-mtu3-counter";
You don't have any resources for the counter in DT, so you don't even
need a node here. Just have the parent driver instaniate the counter
driver.
> + };
> +
> + pwm {
> + compatible = "renesas,rz-mtu3-pwm";
> + #pwm-cells = <2>;
Here too, just declaring a PWM provider. Just move this to the parent
node.
Rob
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-06 20:17 ` Rob Herring
@ 2022-10-07 12:40 ` Biju Das
2022-10-08 7:42 ` Biju Das
0 siblings, 1 reply; 12+ messages in thread
From: Biju Das @ 2022-10-07 12:40 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, William Breathitt Gray, Thierry Reding,
Lee Jones, Uwe Kleine-König, devicetree, linux-pwm,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > channels and one 32-bit timer channel. It supports the following
> > functions
> > - Counter
> > - Timer
> > - PWM
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> > * Dropped counter bindings and integrated with mfd as it has only
> one property.
> > * Removed "#address-cells" and "#size-cells" as it do not have
> children with
> > unit addresses.
> > * Removed quotes from counter and pwm.
> > * Provided full path for pwm bindings.
> > * Updated the example.
> > v1->v2:
> > * Modelled counter and pwm as a single device that handles
> > multiple channels.
> > * Moved counter and pwm bindings to respective subsystems
> > * Dropped 'bindings' from MFD binding title.
> > * Updated the example
> > * Changed the compatible names.
> > ---
> > .../bindings/mfd/renesas,rz-mtu3.yaml | 304
> ++++++++++++++++++
> > .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> > 2 files changed, 354 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > new file mode 100644
> > index 000000000000..44c952ad8d35
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > @@ -0,0 +1,304 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> > +
> > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description: |
> > + This hardware block pconsisting of eight 16-bit timer channels
> and
> > +one
> > + 32- bit timer channel. It supports the following specifications:
> > + - Pulse input/output: 28 lines max.
> > + - Pulse input 3 lines
> > + - Count clock 11 clocks for each channel (14 clocks for MTU0,
> 12 clocks
> > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2
> combination
> > + (when LWA = 1))
> > + - Operating frequency Up to 100 MHz
> > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > + - Waveform output on compare match
> > + - Input capture function (noise filter setting available)
> > + - Counter-clearing operation
> > + - Simultaneous writing to multiple timer counters (TCNT)
> > + (excluding MTU8).
> > + - Simultaneous clearing on compare match or input capture
> > + (excluding MTU8).
> > + - Simultaneous input and output to registers in
> synchronization with
> > + counter operations (excluding MTU8).
> > + - Up to 12-phase PWM output in combination with synchronous
> operation
> > + (excluding MTU8)
> > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > + - Buffer operation specifiable
> > + - [MTU1, MTU2]
> > + - Phase counting mode can be specified independently
> > + - 32-bit phase counting mode can be specified for
> interlocked operation
> > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > + - Cascade connection operation available
> > + - [MTU3, MTU4, MTU6, and MTU7]
> > + - Through interlocked operation of MTU3/4 and MTU6/7, the
> positive and
> > + negative signals in six phases (12 phases in total) can
> be output in
> > + complementary PWM and reset-synchronized PWM operation.
> > + - In complementary PWM mode, values can be transferred from
> buffer
> > + registers to temporary registers at crests and troughs of
> the timer-
> > + counter values or when the buffer registers (TGRD
> registers in MTU4
> > + and MTU7) are written to.
> > + - Double-buffering selectable in complementary PWM mode.
> > + - [MTU3 and MTU4]
> > + - Through interlocking with MTU0, a mode for driving AC
> synchronous
> > + motors (brushless DC motors) by using complementary PWM
> output and
> > + reset-synchronized PWM output is settable and allows the
> selection
> > + of two types of waveform output (chopping or level).
> > + - [MTU5]
> > + - Capable of operation as a dead-time compensation counter.
> > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > + - 32-bit phase counting mode specifiable by combining MTU1
> and MTU2 and
> > + through interlocked operation with MTU0/MTU5 and MTU8.
> > + - Interrupt-skipping function
> > + - In complementary PWM mode, interrupts on crests and
> troughs of counter
> > + values and triggers to start conversion by the A/D
> converter can be
> > + skipped.
> > + - Interrupt sources: 43 sources.
> > + - Buffer operation:
> > + - Automatic transfer of register data (transfer from the
> buffer
> > + register to the timer register).
> > + - Trigger generation
> > + - A/D converter start triggers can be generated
> > + - A/D converter start request delaying function enables A/D
> converter
> > + to be started with any desired timing and to be
> synchronized with
> > + PWM output.
> > + - Low power consumption function
> > + - The MTU3a can be placed in the module-stop state.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > + - const: renesas,rz-mtu3
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: MTU0.TGRA input capture/compare match
> > + - description: MTU0.TGRB input capture/compare match
> > + - description: MTU0.TGRC input capture/compare match
> > + - description: MTU0.TGRD input capture/compare match
> > + - description: MTU0.TCNT overflow
> > + - description: MTU0.TGRE compare match
> > + - description: MTU0.TGRF compare match
> > + - description: MTU1.TGRA input capture/compare match
> > + - description: MTU1.TGRB input capture/compare match
> > + - description: MTU1.TCNT overflow
> > + - description: MTU1.TCNT underflow
> > + - description: MTU2.TGRA input capture/compare match
> > + - description: MTU2.TGRB input capture/compare match
> > + - description: MTU2.TCNT overflow
> > + - description: MTU2.TCNT underflow
> > + - description: MTU3.TGRA input capture/compare match
> > + - description: MTU3.TGRB input capture/compare match
> > + - description: MTU3.TGRC input capture/compare match
> > + - description: MTU3.TGRD input capture/compare match
> > + - description: MTU3.TCNT overflow
> > + - description: MTU4.TGRA input capture/compare match
> > + - description: MTU4.TGRB input capture/compare match
> > + - description: MTU4.TGRC input capture/compare match
> > + - description: MTU4.TGRD input capture/compare match
> > + - description: MTU4.TCNT overflow/underflow
> > + - description: MTU5.TGRU input capture/compare match
> > + - description: MTU5.TGRV input capture/compare match
> > + - description: MTU5.TGRW input capture/compare match
> > + - description: MTU6.TGRA input capture/compare match
> > + - description: MTU6.TGRB input capture/compare match
> > + - description: MTU6.TGRC input capture/compare match
> > + - description: MTU6.TGRD input capture/compare match
> > + - description: MTU6.TCNT overflow
> > + - description: MTU7.TGRA input capture/compare match
> > + - description: MTU7.TGRB input capture/compare match
> > + - description: MTU7.TGRC input capture/compare match
> > + - description: MTU7.TGRD input capture/compare match
> > + - description: MTU7.TCNT overflow/underflow
> > + - description: MTU8.TGRA input capture/compare match
> > + - description: MTU8.TGRB input capture/compare match
> > + - description: MTU8.TGRC input capture/compare match
> > + - description: MTU8.TGRD input capture/compare match
> > + - description: MTU8.TCNT overflow
> > + - description: MTU8.TCNT underflow
> > +
> > + interrupt-names:
> > + items:
> > + - const: tgia0
> > + - const: tgib0
> > + - const: tgic0
> > + - const: tgid0
> > + - const: tgiv0
> > + - const: tgie0
> > + - const: tgif0
> > + - const: tgia1
> > + - const: tgib1
> > + - const: tgiv1
> > + - const: tgiu1
> > + - const: tgia2
> > + - const: tgib2
> > + - const: tgiv2
> > + - const: tgiu2
> > + - const: tgia3
> > + - const: tgib3
> > + - const: tgic3
> > + - const: tgid3
> > + - const: tgiv3
> > + - const: tgia4
> > + - const: tgib4
> > + - const: tgic4
> > + - const: tgid4
> > + - const: tgiv4
> > + - const: tgiu5
> > + - const: tgiv5
> > + - const: tgiw5
> > + - const: tgia6
> > + - const: tgib6
> > + - const: tgic6
> > + - const: tgid6
> > + - const: tgiv6
> > + - const: tgia7
> > + - const: tgib7
> > + - const: tgic7
> > + - const: tgid7
> > + - const: tgiv7
> > + - const: tgia8
> > + - const: tgib8
> > + - const: tgic8
> > + - const: tgid8
> > + - const: tgiv8
> > + - const: tgiu8
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + counter:
> > + description:
> > + There are two phase counting modes. 16-bit phase counting
> mode in which
> > + MTU1 and MTU2 operate independently, and cascade connection
> 32-bit phase
> > + counting mode in which MTU1 and MTU2 are cascaded.
> > +
> > + In phase counting mode, the phase difference between two
> external input
> > + clocks is detected and the corresponding TCNT is incremented
> or
> > + decremented.
> > + The below counters are supported
> > + count0 - MTU1 16-bit phase counting
> > + count1 - MTU2 16-bit phase counting
> > + count2 - MTU1+ MTU2 32-bit phase counting
> > +
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: renesas,rz-mtu3-counter
> > +
> > + required:
> > + - compatible
> > +
> > + additionalProperties: false
> > +
> > + pwm:
> > + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - power-domains
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + mtu3: timer@10001200 {
> > + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
> > + reg = <0x10001200 0xb00>;
> > + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
> "tgiv0", "tgie0",
> > + "tgif0",
> > + "tgia1", "tgib1", "tgiv1", "tgiu1",
> > + "tgia2", "tgib2", "tgiv2", "tgiu2",
> > + "tgia3", "tgib3", "tgic3", "tgid3",
> "tgiv3",
> > + "tgia4", "tgib4", "tgic4", "tgid4",
> "tgiv4",
> > + "tgiu5", "tgiv5", "tgiw5",
> > + "tgia6", "tgib6", "tgic6", "tgid6",
> "tgiv6",
> > + "tgia7", "tgib7", "tgic7", "tgid7",
> "tgiv7",
> > + "tgia8", "tgib8", "tgic8", "tgid8",
> "tgiv8", "tgiu8";
> > + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> > +
> > + counter {
> > + compatible = "renesas,rz-mtu3-counter";
>
> You don't have any resources for the counter in DT, so you don't even
> need a node here. Just have the parent driver instaniate the counter
> driver.
OK will remove the node and compatible(renesas,rz-mtu3-counter) and will add
support for parent driver Instaniate the counter driver by just using
"renesas,rz-mtu3" as it has resources.
>
> > + };
> > +
> > + pwm {
> > + compatible = "renesas,rz-mtu3-pwm";
> > + #pwm-cells = <2>;
>
> Here too, just declaring a PWM provider. Just move this to the parent
> node.
OK, will remove node and compatible. Will add support for parent driver instaniate
the PWM driver and also declaring as a PWM provider.
Cheers,
Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-07 12:40 ` Biju Das
@ 2022-10-08 7:42 ` Biju Das
2022-10-08 10:51 ` Biju Das
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Biju Das @ 2022-10-08 7:42 UTC (permalink / raw)
To: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel
Cc: Krzysztof Kozlowski, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob and all,
> Subject: RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > bindings
> >
> > On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded
> in
> > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > channels and one 32-bit timer channel. It supports the following
> > > functions
> > > - Counter
> > > - Timer
> > > - PWM
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v2->v3:
> > > * Dropped counter bindings and integrated with mfd as it has only
> > one property.
> > > * Removed "#address-cells" and "#size-cells" as it do not have
> > children with
> > > unit addresses.
> > > * Removed quotes from counter and pwm.
> > > * Provided full path for pwm bindings.
> > > * Updated the example.
> > > v1->v2:
> > > * Modelled counter and pwm as a single device that handles
> > > multiple channels.
> > > * Moved counter and pwm bindings to respective subsystems
> > > * Dropped 'bindings' from MFD binding title.
> > > * Updated the example
> > > * Changed the compatible names.
> > > ---
> > > .../bindings/mfd/renesas,rz-mtu3.yaml | 304
> > ++++++++++++++++++
> > > .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> > > 2 files changed, 354 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > new file mode 100644
> > > index 000000000000..44c952ad8d35
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > @@ -0,0 +1,304 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> 1.2
> > > +---
> > > +$id:
> > >
> > > +
> > > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description: |
> > > + This hardware block pconsisting of eight 16-bit timer channels
> > and
> > > +one
> > > + 32- bit timer channel. It supports the following
> specifications:
> > > + - Pulse input/output: 28 lines max.
> > > + - Pulse input 3 lines
> > > + - Count clock 11 clocks for each channel (14 clocks for MTU0,
> > 12 clocks
> > > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2
> > combination
> > > + (when LWA = 1))
> > > + - Operating frequency Up to 100 MHz
> > > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > > + - Waveform output on compare match
> > > + - Input capture function (noise filter setting available)
> > > + - Counter-clearing operation
> > > + - Simultaneous writing to multiple timer counters (TCNT)
> > > + (excluding MTU8).
> > > + - Simultaneous clearing on compare match or input capture
> > > + (excluding MTU8).
> > > + - Simultaneous input and output to registers in
> > synchronization with
> > > + counter operations (excluding MTU8).
> > > + - Up to 12-phase PWM output in combination with
> synchronous
> > operation
> > > + (excluding MTU8)
> > > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > > + - Buffer operation specifiable
> > > + - [MTU1, MTU2]
> > > + - Phase counting mode can be specified independently
> > > + - 32-bit phase counting mode can be specified for
> > interlocked operation
> > > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > > + - Cascade connection operation available
> > > + - [MTU3, MTU4, MTU6, and MTU7]
> > > + - Through interlocked operation of MTU3/4 and MTU6/7, the
> > positive and
> > > + negative signals in six phases (12 phases in total) can
> > be output in
> > > + complementary PWM and reset-synchronized PWM operation.
> > > + - In complementary PWM mode, values can be transferred
> from
> > buffer
> > > + registers to temporary registers at crests and troughs
> of
> > the timer-
> > > + counter values or when the buffer registers (TGRD
> > registers in MTU4
> > > + and MTU7) are written to.
> > > + - Double-buffering selectable in complementary PWM mode.
> > > + - [MTU3 and MTU4]
> > > + - Through interlocking with MTU0, a mode for driving AC
> > synchronous
> > > + motors (brushless DC motors) by using complementary PWM
> > output and
> > > + reset-synchronized PWM output is settable and allows
> the
> > selection
> > > + of two types of waveform output (chopping or level).
> > > + - [MTU5]
> > > + - Capable of operation as a dead-time compensation
> counter.
> > > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > > + - 32-bit phase counting mode specifiable by combining
> MTU1
> > and MTU2 and
> > > + through interlocked operation with MTU0/MTU5 and MTU8.
> > > + - Interrupt-skipping function
> > > + - In complementary PWM mode, interrupts on crests and
> > troughs of counter
> > > + values and triggers to start conversion by the A/D
> > converter can be
> > > + skipped.
> > > + - Interrupt sources: 43 sources.
> > > + - Buffer operation:
> > > + - Automatic transfer of register data (transfer from the
> > buffer
> > > + register to the timer register).
> > > + - Trigger generation
> > > + - A/D converter start triggers can be generated
> > > + - A/D converter start request delaying function enables
> A/D
> > converter
> > > + to be started with any desired timing and to be
> > synchronized with
> > > + PWM output.
> > > + - Low power consumption function
> > > + - The MTU3a can be placed in the module-stop state.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > > + - const: renesas,rz-mtu3
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + items:
> > > + - description: MTU0.TGRA input capture/compare match
> > > + - description: MTU0.TGRB input capture/compare match
> > > + - description: MTU0.TGRC input capture/compare match
> > > + - description: MTU0.TGRD input capture/compare match
> > > + - description: MTU0.TCNT overflow
> > > + - description: MTU0.TGRE compare match
> > > + - description: MTU0.TGRF compare match
> > > + - description: MTU1.TGRA input capture/compare match
> > > + - description: MTU1.TGRB input capture/compare match
> > > + - description: MTU1.TCNT overflow
> > > + - description: MTU1.TCNT underflow
> > > + - description: MTU2.TGRA input capture/compare match
> > > + - description: MTU2.TGRB input capture/compare match
> > > + - description: MTU2.TCNT overflow
> > > + - description: MTU2.TCNT underflow
> > > + - description: MTU3.TGRA input capture/compare match
> > > + - description: MTU3.TGRB input capture/compare match
> > > + - description: MTU3.TGRC input capture/compare match
> > > + - description: MTU3.TGRD input capture/compare match
> > > + - description: MTU3.TCNT overflow
> > > + - description: MTU4.TGRA input capture/compare match
> > > + - description: MTU4.TGRB input capture/compare match
> > > + - description: MTU4.TGRC input capture/compare match
> > > + - description: MTU4.TGRD input capture/compare match
> > > + - description: MTU4.TCNT overflow/underflow
> > > + - description: MTU5.TGRU input capture/compare match
> > > + - description: MTU5.TGRV input capture/compare match
> > > + - description: MTU5.TGRW input capture/compare match
> > > + - description: MTU6.TGRA input capture/compare match
> > > + - description: MTU6.TGRB input capture/compare match
> > > + - description: MTU6.TGRC input capture/compare match
> > > + - description: MTU6.TGRD input capture/compare match
> > > + - description: MTU6.TCNT overflow
> > > + - description: MTU7.TGRA input capture/compare match
> > > + - description: MTU7.TGRB input capture/compare match
> > > + - description: MTU7.TGRC input capture/compare match
> > > + - description: MTU7.TGRD input capture/compare match
> > > + - description: MTU7.TCNT overflow/underflow
> > > + - description: MTU8.TGRA input capture/compare match
> > > + - description: MTU8.TGRB input capture/compare match
> > > + - description: MTU8.TGRC input capture/compare match
> > > + - description: MTU8.TGRD input capture/compare match
> > > + - description: MTU8.TCNT overflow
> > > + - description: MTU8.TCNT underflow
> > > +
> > > + interrupt-names:
> > > + items:
> > > + - const: tgia0
> > > + - const: tgib0
> > > + - const: tgic0
> > > + - const: tgid0
> > > + - const: tgiv0
> > > + - const: tgie0
> > > + - const: tgif0
> > > + - const: tgia1
> > > + - const: tgib1
> > > + - const: tgiv1
> > > + - const: tgiu1
> > > + - const: tgia2
> > > + - const: tgib2
> > > + - const: tgiv2
> > > + - const: tgiu2
> > > + - const: tgia3
> > > + - const: tgib3
> > > + - const: tgic3
> > > + - const: tgid3
> > > + - const: tgiv3
> > > + - const: tgia4
> > > + - const: tgib4
> > > + - const: tgic4
> > > + - const: tgid4
> > > + - const: tgiv4
> > > + - const: tgiu5
> > > + - const: tgiv5
> > > + - const: tgiw5
> > > + - const: tgia6
> > > + - const: tgib6
> > > + - const: tgic6
> > > + - const: tgid6
> > > + - const: tgiv6
> > > + - const: tgia7
> > > + - const: tgib7
> > > + - const: tgic7
> > > + - const: tgid7
> > > + - const: tgiv7
> > > + - const: tgia8
> > > + - const: tgib8
> > > + - const: tgic8
> > > + - const: tgid8
> > > + - const: tgiv8
> > > + - const: tgiu8
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + counter:
> > > + description:
> > > + There are two phase counting modes. 16-bit phase counting
> > mode in which
> > > + MTU1 and MTU2 operate independently, and cascade connection
> > 32-bit phase
> > > + counting mode in which MTU1 and MTU2 are cascaded.
> > > +
> > > + In phase counting mode, the phase difference between two
> > external input
> > > + clocks is detected and the corresponding TCNT is
> incremented
> > or
> > > + decremented.
> > > + The below counters are supported
> > > + count0 - MTU1 16-bit phase counting
> > > + count1 - MTU2 16-bit phase counting
> > > + count2 - MTU1+ MTU2 32-bit phase counting
> > > +
> > > + type: object
> > > +
> > > + properties:
> > > + compatible:
> > > + const: renesas,rz-mtu3-counter
> > > +
> > > + required:
> > > + - compatible
> > > +
> > > + additionalProperties: false
> > > +
> > > + pwm:
> > > + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - interrupts
> > > + - interrupt-names
> > > + - clocks
> > > + - power-domains
> > > + - resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > + mtu3: timer@10001200 {
> > > + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
> > > + reg = <0x10001200 0xb00>;
> > > + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> > > + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
> > "tgiv0", "tgie0",
> > > + "tgif0",
> > > + "tgia1", "tgib1", "tgiv1", "tgiu1",
> > > + "tgia2", "tgib2", "tgiv2", "tgiu2",
> > > + "tgia3", "tgib3", "tgic3", "tgid3",
> > "tgiv3",
> > > + "tgia4", "tgib4", "tgic4", "tgid4",
> > "tgiv4",
> > > + "tgiu5", "tgiv5", "tgiw5",
> > > + "tgia6", "tgib6", "tgic6", "tgid6",
> > "tgiv6",
> > > + "tgia7", "tgib7", "tgic7", "tgid7",
> > "tgiv7",
> > > + "tgia8", "tgib8", "tgic8", "tgid8",
> > "tgiv8", "tgiu8";
> > > + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> > > + power-domains = <&cpg>;
> > > + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> > > +
> > > + counter {
> > > + compatible = "renesas,rz-mtu3-counter";
> >
> > You don't have any resources for the counter in DT, so you don't
> even
> > need a node here. Just have the parent driver instaniate the counter
> > driver.
>
If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then instantiating
the counter and pwm driver from parent driver by directly calling probe function is
giving cyclic dependency error[1].
So looks like either we need to use compatible "renesas,rz-mtu3-counter" and
"renesas,rz-mtu3-pwm" if these functionalities to be in respective subsystem tree
or
squash counter and pwm functionalities to MFD subsystem.
Please share your views on this. Is there any better way to handle this?
[1]
depmod: ../tools/depmod.c:1792: depmod_report_cycles_from_root: Assertion `is < stack_size' failed.
depmod: ERROR: Cycle detected: rz_mtu3 -> rz_mtu3_cnt -> rz_mtu3
depmod: ERROR: Cycle detected: rz_mtu3 -> rz_mtu3_pwm -> rz_mtu3
depmod: ERROR: Found 3 modules in dependency cycles!
make: *** [Makefile:1781: modules_install] Error 1
Cheers,
Biju
>
> >
> > > + };
> > > +
> > > + pwm {
> > > + compatible = "renesas,rz-mtu3-pwm";
> > > + #pwm-cells = <2>;
> >
> > Here too, just declaring a PWM provider. Just move this to the
> parent
> > node.
>
> OK, will remove node and compatible. Will add support for parent
> driver instaniate the PWM driver and also declaring as a PWM provider.
>
> Cheers,
> Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-08 7:42 ` Biju Das
@ 2022-10-08 10:51 ` Biju Das
2022-10-09 14:38 ` Geert Uytterhoeven
2022-10-09 15:16 ` Krzysztof Kozlowski
2 siblings, 0 replies; 12+ messages in thread
From: Biju Das @ 2022-10-08 10:51 UTC (permalink / raw)
To: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel
Cc: Krzysztof Kozlowski, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
> -----Original Message-----
> From: Biju Das
> Sent: 08 October 2022 08:43
> To: Rob Herring <robh@kernel.org>; William Breathitt Gray
> <william.gray@linaro.org>; Thierry Reding <thierry.reding@gmail.com>;
> Lee Jones <lee@kernel.org>; Philipp Zabel <p.zabel@pengutronix.de>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Uwe
> Kleine-König <u.kleine-koenig@pengutronix.de>;
> devicetree@vger.kernel.org; linux-pwm@vger.kernel.org; Geert
> Uytterhoeven <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> linux-renesas-soc@vger.kernel.org
> Subject: RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> Hi Rob and all,
>
> > Subject: RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > bindings
> >
> > Hi Rob,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L
> MTU3a
> > > bindings
> > >
> > > On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded
> > in
> > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit
> timer
> > > > channels and one 32-bit timer channel. It supports the following
> > > > functions
> > > > - Counter
> > > > - Timer
> > > > - PWM
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > v2->v3:
> > > > * Dropped counter bindings and integrated with mfd as it has
> only
> > > one property.
> > > > * Removed "#address-cells" and "#size-cells" as it do not have
> > > children with
> > > > unit addresses.
> > > > * Removed quotes from counter and pwm.
> > > > * Provided full path for pwm bindings.
> > > > * Updated the example.
> > > > v1->v2:
> > > > * Modelled counter and pwm as a single device that handles
> > > > multiple channels.
> > > > * Moved counter and pwm bindings to respective subsystems
> > > > * Dropped 'bindings' from MFD binding title.
> > > > * Updated the example
> > > > * Changed the compatible names.
> > > > ---
> > > > .../bindings/mfd/renesas,rz-mtu3.yaml | 304
> > > ++++++++++++++++++
> > > > .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> > > > 2 files changed, 354 insertions(+) create mode 100644
> > > > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > new file mode 100644
> > > > index 000000000000..44c952ad8d35
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > @@ -0,0 +1,304 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > 1.2
> > > > +---
> > > > +$id:
> > > >
> > > > +
> > > > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> > > > +
> > > > +maintainers:
> > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +description: |
> > > > + This hardware block pconsisting of eight 16-bit timer
> channels
> > > and
> > > > +one
> > > > + 32- bit timer channel. It supports the following
> > specifications:
> > > > + - Pulse input/output: 28 lines max.
> > > > + - Pulse input 3 lines
> > > > + - Count clock 11 clocks for each channel (14 clocks for
> MTU0,
> > > 12 clocks
> > > > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-
> MTU2
> > > combination
> > > > + (when LWA = 1))
> > > > + - Operating frequency Up to 100 MHz
> > > > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > > > + - Waveform output on compare match
> > > > + - Input capture function (noise filter setting
> available)
> > > > + - Counter-clearing operation
> > > > + - Simultaneous writing to multiple timer counters
> (TCNT)
> > > > + (excluding MTU8).
> > > > + - Simultaneous clearing on compare match or input
> capture
> > > > + (excluding MTU8).
> > > > + - Simultaneous input and output to registers in
> > > synchronization with
> > > > + counter operations (excluding MTU8).
> > > > + - Up to 12-phase PWM output in combination with
> > synchronous
> > > operation
> > > > + (excluding MTU8)
> > > > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > > > + - Buffer operation specifiable
> > > > + - [MTU1, MTU2]
> > > > + - Phase counting mode can be specified independently
> > > > + - 32-bit phase counting mode can be specified for
> > > interlocked operation
> > > > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > > > + - Cascade connection operation available
> > > > + - [MTU3, MTU4, MTU6, and MTU7]
> > > > + - Through interlocked operation of MTU3/4 and MTU6/7,
> the
> > > positive and
> > > > + negative signals in six phases (12 phases in total)
> can
> > > be output in
> > > > + complementary PWM and reset-synchronized PWM
> operation.
> > > > + - In complementary PWM mode, values can be transferred
> > from
> > > buffer
> > > > + registers to temporary registers at crests and
> troughs
> > of
> > > the timer-
> > > > + counter values or when the buffer registers (TGRD
> > > registers in MTU4
> > > > + and MTU7) are written to.
> > > > + - Double-buffering selectable in complementary PWM
> mode.
> > > > + - [MTU3 and MTU4]
> > > > + - Through interlocking with MTU0, a mode for driving AC
> > > synchronous
> > > > + motors (brushless DC motors) by using complementary
> PWM
> > > output and
> > > > + reset-synchronized PWM output is settable and allows
> > the
> > > selection
> > > > + of two types of waveform output (chopping or level).
> > > > + - [MTU5]
> > > > + - Capable of operation as a dead-time compensation
> > counter.
> > > > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > > > + - 32-bit phase counting mode specifiable by combining
> > MTU1
> > > and MTU2 and
> > > > + through interlocked operation with MTU0/MTU5 and
> MTU8.
> > > > + - Interrupt-skipping function
> > > > + - In complementary PWM mode, interrupts on crests and
> > > troughs of counter
> > > > + values and triggers to start conversion by the A/D
> > > converter can be
> > > > + skipped.
> > > > + - Interrupt sources: 43 sources.
> > > > + - Buffer operation:
> > > > + - Automatic transfer of register data (transfer from
> the
> > > buffer
> > > > + register to the timer register).
> > > > + - Trigger generation
> > > > + - A/D converter start triggers can be generated
> > > > + - A/D converter start request delaying function enables
> > A/D
> > > converter
> > > > + to be started with any desired timing and to be
> > > synchronized with
> > > > + PWM output.
> > > > + - Low power consumption function
> > > > + - The MTU3a can be placed in the module-stop state.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > > > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > > > + - const: renesas,rz-mtu3
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + interrupts:
> > > > + items:
> > > > + - description: MTU0.TGRA input capture/compare match
> > > > + - description: MTU0.TGRB input capture/compare match
> > > > + - description: MTU0.TGRC input capture/compare match
> > > > + - description: MTU0.TGRD input capture/compare match
> > > > + - description: MTU0.TCNT overflow
> > > > + - description: MTU0.TGRE compare match
> > > > + - description: MTU0.TGRF compare match
> > > > + - description: MTU1.TGRA input capture/compare match
> > > > + - description: MTU1.TGRB input capture/compare match
> > > > + - description: MTU1.TCNT overflow
> > > > + - description: MTU1.TCNT underflow
> > > > + - description: MTU2.TGRA input capture/compare match
> > > > + - description: MTU2.TGRB input capture/compare match
> > > > + - description: MTU2.TCNT overflow
> > > > + - description: MTU2.TCNT underflow
> > > > + - description: MTU3.TGRA input capture/compare match
> > > > + - description: MTU3.TGRB input capture/compare match
> > > > + - description: MTU3.TGRC input capture/compare match
> > > > + - description: MTU3.TGRD input capture/compare match
> > > > + - description: MTU3.TCNT overflow
> > > > + - description: MTU4.TGRA input capture/compare match
> > > > + - description: MTU4.TGRB input capture/compare match
> > > > + - description: MTU4.TGRC input capture/compare match
> > > > + - description: MTU4.TGRD input capture/compare match
> > > > + - description: MTU4.TCNT overflow/underflow
> > > > + - description: MTU5.TGRU input capture/compare match
> > > > + - description: MTU5.TGRV input capture/compare match
> > > > + - description: MTU5.TGRW input capture/compare match
> > > > + - description: MTU6.TGRA input capture/compare match
> > > > + - description: MTU6.TGRB input capture/compare match
> > > > + - description: MTU6.TGRC input capture/compare match
> > > > + - description: MTU6.TGRD input capture/compare match
> > > > + - description: MTU6.TCNT overflow
> > > > + - description: MTU7.TGRA input capture/compare match
> > > > + - description: MTU7.TGRB input capture/compare match
> > > > + - description: MTU7.TGRC input capture/compare match
> > > > + - description: MTU7.TGRD input capture/compare match
> > > > + - description: MTU7.TCNT overflow/underflow
> > > > + - description: MTU8.TGRA input capture/compare match
> > > > + - description: MTU8.TGRB input capture/compare match
> > > > + - description: MTU8.TGRC input capture/compare match
> > > > + - description: MTU8.TGRD input capture/compare match
> > > > + - description: MTU8.TCNT overflow
> > > > + - description: MTU8.TCNT underflow
> > > > +
> > > > + interrupt-names:
> > > > + items:
> > > > + - const: tgia0
> > > > + - const: tgib0
> > > > + - const: tgic0
> > > > + - const: tgid0
> > > > + - const: tgiv0
> > > > + - const: tgie0
> > > > + - const: tgif0
> > > > + - const: tgia1
> > > > + - const: tgib1
> > > > + - const: tgiv1
> > > > + - const: tgiu1
> > > > + - const: tgia2
> > > > + - const: tgib2
> > > > + - const: tgiv2
> > > > + - const: tgiu2
> > > > + - const: tgia3
> > > > + - const: tgib3
> > > > + - const: tgic3
> > > > + - const: tgid3
> > > > + - const: tgiv3
> > > > + - const: tgia4
> > > > + - const: tgib4
> > > > + - const: tgic4
> > > > + - const: tgid4
> > > > + - const: tgiv4
> > > > + - const: tgiu5
> > > > + - const: tgiv5
> > > > + - const: tgiw5
> > > > + - const: tgia6
> > > > + - const: tgib6
> > > > + - const: tgic6
> > > > + - const: tgid6
> > > > + - const: tgiv6
> > > > + - const: tgia7
> > > > + - const: tgib7
> > > > + - const: tgic7
> > > > + - const: tgid7
> > > > + - const: tgiv7
> > > > + - const: tgia8
> > > > + - const: tgib8
> > > > + - const: tgic8
> > > > + - const: tgid8
> > > > + - const: tgiv8
> > > > + - const: tgiu8
> > > > +
> > > > + clocks:
> > > > + maxItems: 1
> > > > +
> > > > + power-domains:
> > > > + maxItems: 1
> > > > +
> > > > + resets:
> > > > + maxItems: 1
> > > > +
> > > > + counter:
> > > > + description:
> > > > + There are two phase counting modes. 16-bit phase counting
> > > mode in which
> > > > + MTU1 and MTU2 operate independently, and cascade
> connection
> > > 32-bit phase
> > > > + counting mode in which MTU1 and MTU2 are cascaded.
> > > > +
> > > > + In phase counting mode, the phase difference between two
> > > external input
> > > > + clocks is detected and the corresponding TCNT is
> > incremented
> > > or
> > > > + decremented.
> > > > + The below counters are supported
> > > > + count0 - MTU1 16-bit phase counting
> > > > + count1 - MTU2 16-bit phase counting
> > > > + count2 - MTU1+ MTU2 32-bit phase counting
> > > > +
> > > > + type: object
> > > > +
> > > > + properties:
> > > > + compatible:
> > > > + const: renesas,rz-mtu3-counter
> > > > +
> > > > + required:
> > > > + - compatible
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > + pwm:
> > > > + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - interrupts
> > > > + - interrupt-names
> > > > + - clocks
> > > > + - power-domains
> > > > + - resets
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > + mtu3: timer@10001200 {
> > > > + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
> > > > + reg = <0x10001200 0xb00>;
> > > > + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > > > + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> > > > + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
> > > "tgiv0", "tgie0",
> > > > + "tgif0",
> > > > + "tgia1", "tgib1", "tgiv1", "tgiu1",
> > > > + "tgia2", "tgib2", "tgiv2", "tgiu2",
> > > > + "tgia3", "tgib3", "tgic3", "tgid3",
> > > "tgiv3",
> > > > + "tgia4", "tgib4", "tgic4", "tgid4",
> > > "tgiv4",
> > > > + "tgiu5", "tgiv5", "tgiw5",
> > > > + "tgia6", "tgib6", "tgic6", "tgid6",
> > > "tgiv6",
> > > > + "tgia7", "tgib7", "tgic7", "tgid7",
> > > "tgiv7",
> > > > + "tgia8", "tgib8", "tgic8", "tgid8",
> > > "tgiv8", "tgiu8";
> > > > + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> > > > + power-domains = <&cpg>;
> > > > + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> > > > +
> > > > + counter {
> > > > + compatible = "renesas,rz-mtu3-counter";
> > >
> > > You don't have any resources for the counter in DT, so you don't
> > even
> > > need a node here. Just have the parent driver instaniate the
> counter
> > > driver.
> >
>
> If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then
> instantiating the counter and pwm driver from parent driver by
> directly calling probe function is giving cyclic dependency error[1].
>
> So looks like either we need to use compatible "renesas,rz-mtu3-
> counter" and "renesas,rz-mtu3-pwm" if these functionalities to be in
> respective subsystem tree
>
> or
>
> squash counter and pwm functionalities to MFD subsystem.
>
> Please share your views on this. Is there any better way to handle
> this?
>
> [1]
> depmod: ../tools/depmod.c:1792: depmod_report_cycles_from_root:
> Assertion `is < stack_size' failed.
> depmod: ERROR: Cycle detected: rz_mtu3 -> rz_mtu3_cnt -> rz_mtu3
> depmod: ERROR: Cycle detected: rz_mtu3 -> rz_mtu3_pwm -> rz_mtu3
> depmod: ERROR: Found 3 modules in dependency cycles!
> make: *** [Makefile:1781: modules_install] Error 1
Just to add the below drivers have compatibles that does not have any resources. Am I missing anything here?
[1] https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml#L209
[2] https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml#L105
[3] https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml#L71
Cheers,
Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-08 7:42 ` Biju Das
2022-10-08 10:51 ` Biju Das
@ 2022-10-09 14:38 ` Geert Uytterhoeven
2022-10-09 15:17 ` Krzysztof Kozlowski
2022-10-10 7:10 ` Biju Das
2022-10-09 15:16 ` Krzysztof Kozlowski
2 siblings, 2 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-09 14:38 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel, Krzysztof Kozlowski, Uwe Kleine-König,
devicetree, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Hi Biju,
On Sat, Oct 8, 2022 at 9:42 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded
> > in
> > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > > channels and one 32-bit timer channel. It supports the following
> > > > functions
> > > > - Counter
> > > > - Timer
> > > > - PWM
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > v2->v3:
> > > > * Dropped counter bindings and integrated with mfd as it has only
> > > one property.
> > > > * Removed "#address-cells" and "#size-cells" as it do not have
> > > children with
> > > > unit addresses.
> > > > * Removed quotes from counter and pwm.
> > > > * Provided full path for pwm bindings.
> > > > * Updated the example.
> > > > v1->v2:
> > > > * Modelled counter and pwm as a single device that handles
> > > > multiple channels.
> > > > * Moved counter and pwm bindings to respective subsystems
> > > > * Dropped 'bindings' from MFD binding title.
> > > > * Updated the example
> > > > * Changed the compatible names.
> > > > ---
> > > > .../bindings/mfd/renesas,rz-mtu3.yaml | 304
> > > ++++++++++++++++++
> > > > .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> > > > 2 files changed, 354 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > new file mode 100644
> > > > index 000000000000..44c952ad8d35
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > @@ -0,0 +1,304 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > 1.2
> > > > +---
> > > > +$id:
> > > >
> > > > +
> > > > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> > > > +
> > > > +maintainers:
> > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +description: |
> > > > + This hardware block pconsisting of eight 16-bit timer channels
> > > and
> > > > +one
> > > > + 32- bit timer channel. It supports the following
> > specifications:
> > > > + - Pulse input/output: 28 lines max.
> > > > + - Pulse input 3 lines
> > > > + - Count clock 11 clocks for each channel (14 clocks for MTU0,
> > > 12 clocks
> > > > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2
> > > combination
> > > > + (when LWA = 1))
> > > > + - Operating frequency Up to 100 MHz
> > > > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > > > + - Waveform output on compare match
> > > > + - Input capture function (noise filter setting available)
> > > > + - Counter-clearing operation
> > > > + - Simultaneous writing to multiple timer counters (TCNT)
> > > > + (excluding MTU8).
> > > > + - Simultaneous clearing on compare match or input capture
> > > > + (excluding MTU8).
> > > > + - Simultaneous input and output to registers in
> > > synchronization with
> > > > + counter operations (excluding MTU8).
> > > > + - Up to 12-phase PWM output in combination with
> > synchronous
> > > operation
> > > > + (excluding MTU8)
> > > > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > > > + - Buffer operation specifiable
> > > > + - [MTU1, MTU2]
> > > > + - Phase counting mode can be specified independently
> > > > + - 32-bit phase counting mode can be specified for
> > > interlocked operation
> > > > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > > > + - Cascade connection operation available
> > > > + - [MTU3, MTU4, MTU6, and MTU7]
> > > > + - Through interlocked operation of MTU3/4 and MTU6/7, the
> > > positive and
> > > > + negative signals in six phases (12 phases in total) can
> > > be output in
> > > > + complementary PWM and reset-synchronized PWM operation.
> > > > + - In complementary PWM mode, values can be transferred
> > from
> > > buffer
> > > > + registers to temporary registers at crests and troughs
> > of
> > > the timer-
> > > > + counter values or when the buffer registers (TGRD
> > > registers in MTU4
> > > > + and MTU7) are written to.
> > > > + - Double-buffering selectable in complementary PWM mode.
> > > > + - [MTU3 and MTU4]
> > > > + - Through interlocking with MTU0, a mode for driving AC
> > > synchronous
> > > > + motors (brushless DC motors) by using complementary PWM
> > > output and
> > > > + reset-synchronized PWM output is settable and allows
> > the
> > > selection
> > > > + of two types of waveform output (chopping or level).
> > > > + - [MTU5]
> > > > + - Capable of operation as a dead-time compensation
> > counter.
> > > > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > > > + - 32-bit phase counting mode specifiable by combining
> > MTU1
> > > and MTU2 and
> > > > + through interlocked operation with MTU0/MTU5 and MTU8.
> > > > + - Interrupt-skipping function
> > > > + - In complementary PWM mode, interrupts on crests and
> > > troughs of counter
> > > > + values and triggers to start conversion by the A/D
> > > converter can be
> > > > + skipped.
> > > > + - Interrupt sources: 43 sources.
> > > > + - Buffer operation:
> > > > + - Automatic transfer of register data (transfer from the
> > > buffer
> > > > + register to the timer register).
> > > > + - Trigger generation
> > > > + - A/D converter start triggers can be generated
> > > > + - A/D converter start request delaying function enables
> > A/D
> > > converter
> > > > + to be started with any desired timing and to be
> > > synchronized with
> > > > + PWM output.
> > > > + - Low power consumption function
> > > > + - The MTU3a can be placed in the module-stop state.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > > > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > > > + - const: renesas,rz-mtu3
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + interrupts:
> > > > + items:
> > > > + - description: MTU0.TGRA input capture/compare match
> > > > + - description: MTU0.TGRB input capture/compare match
> > > > + - description: MTU0.TGRC input capture/compare match
> > > > + - description: MTU0.TGRD input capture/compare match
> > > > + - description: MTU0.TCNT overflow
> > > > + - description: MTU0.TGRE compare match
> > > > + - description: MTU0.TGRF compare match
> > > > + - description: MTU1.TGRA input capture/compare match
> > > > + - description: MTU1.TGRB input capture/compare match
> > > > + - description: MTU1.TCNT overflow
> > > > + - description: MTU1.TCNT underflow
> > > > + - description: MTU2.TGRA input capture/compare match
> > > > + - description: MTU2.TGRB input capture/compare match
> > > > + - description: MTU2.TCNT overflow
> > > > + - description: MTU2.TCNT underflow
> > > > + - description: MTU3.TGRA input capture/compare match
> > > > + - description: MTU3.TGRB input capture/compare match
> > > > + - description: MTU3.TGRC input capture/compare match
> > > > + - description: MTU3.TGRD input capture/compare match
> > > > + - description: MTU3.TCNT overflow
> > > > + - description: MTU4.TGRA input capture/compare match
> > > > + - description: MTU4.TGRB input capture/compare match
> > > > + - description: MTU4.TGRC input capture/compare match
> > > > + - description: MTU4.TGRD input capture/compare match
> > > > + - description: MTU4.TCNT overflow/underflow
> > > > + - description: MTU5.TGRU input capture/compare match
> > > > + - description: MTU5.TGRV input capture/compare match
> > > > + - description: MTU5.TGRW input capture/compare match
> > > > + - description: MTU6.TGRA input capture/compare match
> > > > + - description: MTU6.TGRB input capture/compare match
> > > > + - description: MTU6.TGRC input capture/compare match
> > > > + - description: MTU6.TGRD input capture/compare match
> > > > + - description: MTU6.TCNT overflow
> > > > + - description: MTU7.TGRA input capture/compare match
> > > > + - description: MTU7.TGRB input capture/compare match
> > > > + - description: MTU7.TGRC input capture/compare match
> > > > + - description: MTU7.TGRD input capture/compare match
> > > > + - description: MTU7.TCNT overflow/underflow
> > > > + - description: MTU8.TGRA input capture/compare match
> > > > + - description: MTU8.TGRB input capture/compare match
> > > > + - description: MTU8.TGRC input capture/compare match
> > > > + - description: MTU8.TGRD input capture/compare match
> > > > + - description: MTU8.TCNT overflow
> > > > + - description: MTU8.TCNT underflow
> > > > +
> > > > + interrupt-names:
> > > > + items:
> > > > + - const: tgia0
> > > > + - const: tgib0
> > > > + - const: tgic0
> > > > + - const: tgid0
> > > > + - const: tgiv0
> > > > + - const: tgie0
> > > > + - const: tgif0
> > > > + - const: tgia1
> > > > + - const: tgib1
> > > > + - const: tgiv1
> > > > + - const: tgiu1
> > > > + - const: tgia2
> > > > + - const: tgib2
> > > > + - const: tgiv2
> > > > + - const: tgiu2
> > > > + - const: tgia3
> > > > + - const: tgib3
> > > > + - const: tgic3
> > > > + - const: tgid3
> > > > + - const: tgiv3
> > > > + - const: tgia4
> > > > + - const: tgib4
> > > > + - const: tgic4
> > > > + - const: tgid4
> > > > + - const: tgiv4
> > > > + - const: tgiu5
> > > > + - const: tgiv5
> > > > + - const: tgiw5
> > > > + - const: tgia6
> > > > + - const: tgib6
> > > > + - const: tgic6
> > > > + - const: tgid6
> > > > + - const: tgiv6
> > > > + - const: tgia7
> > > > + - const: tgib7
> > > > + - const: tgic7
> > > > + - const: tgid7
> > > > + - const: tgiv7
> > > > + - const: tgia8
> > > > + - const: tgib8
> > > > + - const: tgic8
> > > > + - const: tgid8
> > > > + - const: tgiv8
> > > > + - const: tgiu8
> > > > +
> > > > + clocks:
> > > > + maxItems: 1
> > > > +
> > > > + power-domains:
> > > > + maxItems: 1
> > > > +
> > > > + resets:
> > > > + maxItems: 1
> > > > +
> > > > + counter:
> > > > + description:
> > > > + There are two phase counting modes. 16-bit phase counting
> > > mode in which
> > > > + MTU1 and MTU2 operate independently, and cascade connection
> > > 32-bit phase
> > > > + counting mode in which MTU1 and MTU2 are cascaded.
> > > > +
> > > > + In phase counting mode, the phase difference between two
> > > external input
> > > > + clocks is detected and the corresponding TCNT is
> > incremented
> > > or
> > > > + decremented.
> > > > + The below counters are supported
> > > > + count0 - MTU1 16-bit phase counting
> > > > + count1 - MTU2 16-bit phase counting
> > > > + count2 - MTU1+ MTU2 32-bit phase counting
> > > > +
> > > > + type: object
> > > > +
> > > > + properties:
> > > > + compatible:
> > > > + const: renesas,rz-mtu3-counter
> > > > +
> > > > + required:
> > > > + - compatible
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > + pwm:
> > > > + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - interrupts
> > > > + - interrupt-names
> > > > + - clocks
> > > > + - power-domains
> > > > + - resets
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > + mtu3: timer@10001200 {
> > > > + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
> > > > + reg = <0x10001200 0xb00>;
> > > > +
> > > > + counter {
> > > > + compatible = "renesas,rz-mtu3-counter";
> > >
> > > You don't have any resources for the counter in DT, so you don't
> > even
> > > need a node here. Just have the parent driver instaniate the counter
> > > driver.
> >
>
> If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then instantiating
> the counter and pwm driver from parent driver by directly calling probe function is
> giving cyclic dependency error[1].
>
> So looks like either we need to use compatible "renesas,rz-mtu3-counter" and
> "renesas,rz-mtu3-pwm" if these functionalities to be in respective subsystem tree
>
> or
>
> squash counter and pwm functionalities to MFD subsystem.
>
> Please share your views on this. Is there any better way to handle this?
I think what Rob means is that you can have a single driver that binds
against "renesas,rz-mtu3", and registers both the counter and the pwm
functionalities. Just like the clock driver, which registers clock,
reset, and PM Domain functionalities. I.e. no mfd would be involved
anymore.
You can still split the driver functionality across multiple source
files (core, counter, pwm).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-08 7:42 ` Biju Das
2022-10-08 10:51 ` Biju Das
2022-10-09 14:38 ` Geert Uytterhoeven
@ 2022-10-09 15:16 ` Krzysztof Kozlowski
2022-10-10 15:13 ` Biju Das
2 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-09 15:16 UTC (permalink / raw)
To: Biju Das, Rob Herring, William Breathitt Gray, Thierry Reding,
Lee Jones, Philipp Zabel
Cc: Krzysztof Kozlowski, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On 08/10/2022 09:42, Biju Das wrote:
>>>> + "tgia8", "tgib8", "tgic8", "tgid8",
>>> "tgiv8", "tgiu8";
>>>> + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
>>>> + power-domains = <&cpg>;
>>>> + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
>>>> +
>>>> + counter {
>>>> + compatible = "renesas,rz-mtu3-counter";
>>>
>>> You don't have any resources for the counter in DT, so you don't
>> even
>>> need a node here. Just have the parent driver instaniate the counter
>>> driver.
>>
>
> If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then instantiating
> the counter and pwm driver from parent driver by directly calling probe function is
> giving cyclic dependency error[1].
How is this related to DT? Purpose of DT is not to solve your probe
problems.
>
> So looks like either we need to use compatible "renesas,rz-mtu3-counter" and
> "renesas,rz-mtu3-pwm" if these functionalities to be in respective subsystem tree
>
No, you don't need. Your driver implementation is not really related to
the bindings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-09 14:38 ` Geert Uytterhoeven
@ 2022-10-09 15:17 ` Krzysztof Kozlowski
2022-10-10 13:00 ` Biju Das
2022-10-10 7:10 ` Biju Das
1 sibling, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-09 15:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Biju Das
Cc: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel, Krzysztof Kozlowski, Uwe Kleine-König,
devicetree, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
On 09/10/2022 16:38, Geert Uytterhoeven wrote:
>>
>> So looks like either we need to use compatible "renesas,rz-mtu3-counter" and
>> "renesas,rz-mtu3-pwm" if these functionalities to be in respective subsystem tree
>>
>> or
>>
>> squash counter and pwm functionalities to MFD subsystem.
>>
>> Please share your views on this. Is there any better way to handle this?
>
> I think what Rob means is that you can have a single driver that binds
> against "renesas,rz-mtu3", and registers both the counter and the pwm
> functionalities. Just like the clock driver, which registers clock,
> reset, and PM Domain functionalities. I.e. no mfd would be involved
> anymore.
> You can still split the driver functionality across multiple source
> files (core, counter, pwm).
Yes.
Bindings design is independent of driver design (e.g. still MFD framework).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-09 14:38 ` Geert Uytterhoeven
2022-10-09 15:17 ` Krzysztof Kozlowski
@ 2022-10-10 7:10 ` Biju Das
1 sibling, 0 replies; 12+ messages in thread
From: Biju Das @ 2022-10-10 7:10 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel, Krzysztof Kozlowski, Uwe Kleine-König,
devicetree, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> Hi Biju,
>
> On Sat, Oct 8, 2022 at 9:42 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > > On Thu, Oct 06, 2022 at 02:57:14PM +0100, Biju Das wrote:
> > > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is
> embedded
> > > in
> > > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit
> > > > > timer channels and one 32-bit timer channel. It supports the
> > > > > following functions
> > > > > - Counter
> > > > > - Timer
> > > > > - PWM
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > ---
> > > > > v2->v3:
> > > > > * Dropped counter bindings and integrated with mfd as it has
> > > > > only
> > > > one property.
> > > > > * Removed "#address-cells" and "#size-cells" as it do not
> have
> > > > children with
> > > > > unit addresses.
> > > > > * Removed quotes from counter and pwm.
> > > > > * Provided full path for pwm bindings.
> > > > > * Updated the example.
> > > > > v1->v2:
> > > > > * Modelled counter and pwm as a single device that handles
> > > > > multiple channels.
> > > > > * Moved counter and pwm bindings to respective subsystems
> > > > > * Dropped 'bindings' from MFD binding title.
> > > > > * Updated the example
> > > > > * Changed the compatible names.
> > > > > ---
> > > > > .../bindings/mfd/renesas,rz-mtu3.yaml | 304
> > > > ++++++++++++++++++
> > > > > .../bindings/pwm/renesas,rz-mtu3-pwm.yaml | 50 +++
> > > > > 2 files changed, 354 insertions(+) create mode 100644
> > > > > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/pwm/renesas,rz-mtu3-pwm.yaml
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..44c952ad8d35
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-
> mtu3.yaml
> > > > > @@ -0,0 +1,304 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML
> > > 1.2
> > > > > +---
> > > > > +$id:
> > > > >
> > > > > +
> > > > > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3
> (MTU3a)
> > > > > +
> > > > > +maintainers:
> > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > +
> > > > > +description: |
> > > > > + This hardware block pconsisting of eight 16-bit timer
> > > > > +channels
> > > > and
> > > > > +one
> > > > > + 32- bit timer channel. It supports the following
> > > specifications:
> > > > > + - Pulse input/output: 28 lines max.
> > > > > + - Pulse input 3 lines
> > > > > + - Count clock 11 clocks for each channel (14 clocks for
> > > > > + MTU0,
> > > > 12 clocks
> > > > > + for MTU2, and 10 clocks for MTU5, four clocks for
> > > > > + MTU1-MTU2
> > > > combination
> > > > > + (when LWA = 1))
> > > > > + - Operating frequency Up to 100 MHz
> > > > > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and
> MTU8]
> > > > > + - Waveform output on compare match
> > > > > + - Input capture function (noise filter setting
> available)
> > > > > + - Counter-clearing operation
> > > > > + - Simultaneous writing to multiple timer counters
> (TCNT)
> > > > > + (excluding MTU8).
> > > > > + - Simultaneous clearing on compare match or input
> capture
> > > > > + (excluding MTU8).
> > > > > + - Simultaneous input and output to registers in
> > > > synchronization with
> > > > > + counter operations (excluding MTU8).
> > > > > + - Up to 12-phase PWM output in combination with
> > > synchronous
> > > > operation
> > > > > + (excluding MTU8)
> > > > > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > > > > + - Buffer operation specifiable
> > > > > + - [MTU1, MTU2]
> > > > > + - Phase counting mode can be specified independently
> > > > > + - 32-bit phase counting mode can be specified for
> > > > interlocked operation
> > > > > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > > > > + - Cascade connection operation available
> > > > > + - [MTU3, MTU4, MTU6, and MTU7]
> > > > > + - Through interlocked operation of MTU3/4 and MTU6/7,
> > > > > + the
> > > > positive and
> > > > > + negative signals in six phases (12 phases in total)
> > > > > + can
> > > > be output in
> > > > > + complementary PWM and reset-synchronized PWM
> operation.
> > > > > + - In complementary PWM mode, values can be
> transferred
> > > from
> > > > buffer
> > > > > + registers to temporary registers at crests and
> > > > > + troughs
> > > of
> > > > the timer-
> > > > > + counter values or when the buffer registers (TGRD
> > > > registers in MTU4
> > > > > + and MTU7) are written to.
> > > > > + - Double-buffering selectable in complementary PWM
> mode.
> > > > > + - [MTU3 and MTU4]
> > > > > + - Through interlocking with MTU0, a mode for driving
> AC
> > > > synchronous
> > > > > + motors (brushless DC motors) by using complementary
> > > > > + PWM
> > > > output and
> > > > > + reset-synchronized PWM output is settable and
> allows
> > > the
> > > > selection
> > > > > + of two types of waveform output (chopping or
> level).
> > > > > + - [MTU5]
> > > > > + - Capable of operation as a dead-time compensation
> > > counter.
> > > > > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > > > > + - 32-bit phase counting mode specifiable by combining
> > > MTU1
> > > > and MTU2 and
> > > > > + through interlocked operation with MTU0/MTU5 and
> MTU8.
> > > > > + - Interrupt-skipping function
> > > > > + - In complementary PWM mode, interrupts on crests and
> > > > troughs of counter
> > > > > + values and triggers to start conversion by the A/D
> > > > converter can be
> > > > > + skipped.
> > > > > + - Interrupt sources: 43 sources.
> > > > > + - Buffer operation:
> > > > > + - Automatic transfer of register data (transfer from
> > > > > + the
> > > > buffer
> > > > > + register to the timer register).
> > > > > + - Trigger generation
> > > > > + - A/D converter start triggers can be generated
> > > > > + - A/D converter start request delaying function
> enables
> > > A/D
> > > > converter
> > > > > + to be started with any desired timing and to be
> > > > synchronized with
> > > > > + PWM output.
> > > > > + - Low power consumption function
> > > > > + - The MTU3a can be placed in the module-stop state.
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > > > > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > > > > + - const: renesas,rz-mtu3
> > > > > +
> > > > > + reg:
> > > > > + maxItems: 1
> > > > > +
> > > > > + interrupts:
> > > > > + items:
> > > > > + - description: MTU0.TGRA input capture/compare match
> > > > > + - description: MTU0.TGRB input capture/compare match
> > > > > + - description: MTU0.TGRC input capture/compare match
> > > > > + - description: MTU0.TGRD input capture/compare match
> > > > > + - description: MTU0.TCNT overflow
> > > > > + - description: MTU0.TGRE compare match
> > > > > + - description: MTU0.TGRF compare match
> > > > > + - description: MTU1.TGRA input capture/compare match
> > > > > + - description: MTU1.TGRB input capture/compare match
> > > > > + - description: MTU1.TCNT overflow
> > > > > + - description: MTU1.TCNT underflow
> > > > > + - description: MTU2.TGRA input capture/compare match
> > > > > + - description: MTU2.TGRB input capture/compare match
> > > > > + - description: MTU2.TCNT overflow
> > > > > + - description: MTU2.TCNT underflow
> > > > > + - description: MTU3.TGRA input capture/compare match
> > > > > + - description: MTU3.TGRB input capture/compare match
> > > > > + - description: MTU3.TGRC input capture/compare match
> > > > > + - description: MTU3.TGRD input capture/compare match
> > > > > + - description: MTU3.TCNT overflow
> > > > > + - description: MTU4.TGRA input capture/compare match
> > > > > + - description: MTU4.TGRB input capture/compare match
> > > > > + - description: MTU4.TGRC input capture/compare match
> > > > > + - description: MTU4.TGRD input capture/compare match
> > > > > + - description: MTU4.TCNT overflow/underflow
> > > > > + - description: MTU5.TGRU input capture/compare match
> > > > > + - description: MTU5.TGRV input capture/compare match
> > > > > + - description: MTU5.TGRW input capture/compare match
> > > > > + - description: MTU6.TGRA input capture/compare match
> > > > > + - description: MTU6.TGRB input capture/compare match
> > > > > + - description: MTU6.TGRC input capture/compare match
> > > > > + - description: MTU6.TGRD input capture/compare match
> > > > > + - description: MTU6.TCNT overflow
> > > > > + - description: MTU7.TGRA input capture/compare match
> > > > > + - description: MTU7.TGRB input capture/compare match
> > > > > + - description: MTU7.TGRC input capture/compare match
> > > > > + - description: MTU7.TGRD input capture/compare match
> > > > > + - description: MTU7.TCNT overflow/underflow
> > > > > + - description: MTU8.TGRA input capture/compare match
> > > > > + - description: MTU8.TGRB input capture/compare match
> > > > > + - description: MTU8.TGRC input capture/compare match
> > > > > + - description: MTU8.TGRD input capture/compare match
> > > > > + - description: MTU8.TCNT overflow
> > > > > + - description: MTU8.TCNT underflow
> > > > > +
> > > > > + interrupt-names:
> > > > > + items:
> > > > > + - const: tgia0
> > > > > + - const: tgib0
> > > > > + - const: tgic0
> > > > > + - const: tgid0
> > > > > + - const: tgiv0
> > > > > + - const: tgie0
> > > > > + - const: tgif0
> > > > > + - const: tgia1
> > > > > + - const: tgib1
> > > > > + - const: tgiv1
> > > > > + - const: tgiu1
> > > > > + - const: tgia2
> > > > > + - const: tgib2
> > > > > + - const: tgiv2
> > > > > + - const: tgiu2
> > > > > + - const: tgia3
> > > > > + - const: tgib3
> > > > > + - const: tgic3
> > > > > + - const: tgid3
> > > > > + - const: tgiv3
> > > > > + - const: tgia4
> > > > > + - const: tgib4
> > > > > + - const: tgic4
> > > > > + - const: tgid4
> > > > > + - const: tgiv4
> > > > > + - const: tgiu5
> > > > > + - const: tgiv5
> > > > > + - const: tgiw5
> > > > > + - const: tgia6
> > > > > + - const: tgib6
> > > > > + - const: tgic6
> > > > > + - const: tgid6
> > > > > + - const: tgiv6
> > > > > + - const: tgia7
> > > > > + - const: tgib7
> > > > > + - const: tgic7
> > > > > + - const: tgid7
> > > > > + - const: tgiv7
> > > > > + - const: tgia8
> > > > > + - const: tgib8
> > > > > + - const: tgic8
> > > > > + - const: tgid8
> > > > > + - const: tgiv8
> > > > > + - const: tgiu8
> > > > > +
> > > > > + clocks:
> > > > > + maxItems: 1
> > > > > +
> > > > > + power-domains:
> > > > > + maxItems: 1
> > > > > +
> > > > > + resets:
> > > > > + maxItems: 1
> > > > > +
> > > > > + counter:
> > > > > + description:
> > > > > + There are two phase counting modes. 16-bit phase
> counting
> > > > mode in which
> > > > > + MTU1 and MTU2 operate independently, and cascade
> > > > > + connection
> > > > 32-bit phase
> > > > > + counting mode in which MTU1 and MTU2 are cascaded.
> > > > > +
> > > > > + In phase counting mode, the phase difference between
> two
> > > > external input
> > > > > + clocks is detected and the corresponding TCNT is
> > > incremented
> > > > or
> > > > > + decremented.
> > > > > + The below counters are supported
> > > > > + count0 - MTU1 16-bit phase counting
> > > > > + count1 - MTU2 16-bit phase counting
> > > > > + count2 - MTU1+ MTU2 32-bit phase counting
> > > > > +
> > > > > + type: object
> > > > > +
> > > > > + properties:
> > > > > + compatible:
> > > > > + const: renesas,rz-mtu3-counter
> > > > > +
> > > > > + required:
> > > > > + - compatible
> > > > > +
> > > > > + additionalProperties: false
> > > > > +
> > > > > + pwm:
> > > > > + $ref: /schemas/pwm/renesas,rz-mtu3-pwm.yaml
> > > > > +
> > > > > +required:
> > > > > + - compatible
> > > > > + - reg
> > > > > + - interrupts
> > > > > + - interrupt-names
> > > > > + - clocks
> > > > > + - power-domains
> > > > > + - resets
> > > > > +
> > > > > +additionalProperties: false
> > > > > +
> > > > > +examples:
> > > > > + - |
> > > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > +
> > > > > + mtu3: timer@10001200 {
> > > > > + compatible = "renesas,r9a07g044-mtu3", "renesas,rz-
> mtu3";
> > > > > + reg = <0x10001200 0xb00>;
>
> > > > > +
> > > > > + counter {
> > > > > + compatible = "renesas,rz-mtu3-counter";
> > > >
> > > > You don't have any resources for the counter in DT, so you don't
> > > even
> > > > need a node here. Just have the parent driver instaniate the
> > > > counter driver.
> > >
> >
> > If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then
> > instantiating the counter and pwm driver from parent driver by
> > directly calling probe function is giving cyclic dependency
> error[1].
> >
> > So looks like either we need to use compatible
> > "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" if these
> > functionalities to be in respective subsystem tree
> >
> > or
> >
> > squash counter and pwm functionalities to MFD subsystem.
> >
> > Please share your views on this. Is there any better way to handle
> this?
>
> I think what Rob means is that you can have a single driver that binds
> against "renesas,rz-mtu3", and registers both the counter and the pwm
> functionalities. Just like the clock driver, which registers clock,
> reset, and PM Domain functionalities. I.e. no mfd would be involved
> anymore.
Thanks for clarification. OK, will use single driver that binds
against "renesas,rz-mtu3".
> You can still split the driver functionality across multiple source
> files (core, counter, pwm).
Yep, Will do. This split will give clear separation to make reviews easier
for the relevant subsystem people.
Cheers,
Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-09 15:17 ` Krzysztof Kozlowski
@ 2022-10-10 13:00 ` Biju Das
0 siblings, 0 replies; 12+ messages in thread
From: Biju Das @ 2022-10-10 13:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: Rob Herring, William Breathitt Gray, Thierry Reding, Lee Jones,
Philipp Zabel, Krzysztof Kozlowski, Uwe Kleine-König,
devicetree, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Hi Krzysztof Kozlowski,
Thanks for the feedback.
> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> On 09/10/2022 16:38, Geert Uytterhoeven wrote:
> >>
> >> So looks like either we need to use compatible
> >> "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" if these
> >> functionalities to be in respective subsystem tree
> >>
> >> or
> >>
> >> squash counter and pwm functionalities to MFD subsystem.
> >>
> >> Please share your views on this. Is there any better way to handle
> this?
> >
> > I think what Rob means is that you can have a single driver that
> binds
> > against "renesas,rz-mtu3", and registers both the counter and the
> pwm
> > functionalities. Just like the clock driver, which registers clock,
> > reset, and PM Domain functionalities. I.e. no mfd would be involved
> > anymore.
> > You can still split the driver functionality across multiple source
> > files (core, counter, pwm).
>
> Yes.
Ok.
>
> Bindings design is independent of driver design (e.g. still MFD
> framework).
I agree, binding is for describing hardware.
Cheers,
Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-09 15:16 ` Krzysztof Kozlowski
@ 2022-10-10 15:13 ` Biju Das
0 siblings, 0 replies; 12+ messages in thread
From: Biju Das @ 2022-10-10 15:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, William Breathitt Gray,
Thierry Reding, Lee Jones, Philipp Zabel
Cc: Krzysztof Kozlowski, Uwe Kleine-König, devicetree,
linux-pwm, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Krzysztof Kozlowski,
> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> On 08/10/2022 09:42, Biju Das wrote:
>
> >>>> + "tgia8", "tgib8", "tgic8", "tgid8",
> >>> "tgiv8", "tgiu8";
> >>>> + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> >>>> + power-domains = <&cpg>;
> >>>> + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> >>>> +
> >>>> + counter {
> >>>> + compatible = "renesas,rz-mtu3-counter";
> >>>
> >>> You don't have any resources for the counter in DT, so you don't
> >> even
> >>> need a node here. Just have the parent driver instaniate the
> counter
> >>> driver.
> >>
> >
> > If I remove "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" then
> > instantiating the counter and pwm driver from parent driver by
> > directly calling probe function is giving cyclic dependency
> error[1].
>
> How is this related to DT? Purpose of DT is not to solve your probe
> problems.
OK.
>
> >
> > So looks like either we need to use compatible
> > "renesas,rz-mtu3-counter" and "renesas,rz-mtu3-pwm" if these
> > functionalities to be in respective subsystem tree
> >
>
> No, you don't need. Your driver implementation is not really related
> to the bindings.
OK. Posted [1] with the suggested binding changes.
[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=684233
Cheers,
Biju
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-10-10 15:13 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-06 13:57 [PATCH v3 0/4] Add RZ/G2L MTU3a MFD, Counter and pwm driver Biju Das
2022-10-06 13:57 ` [PATCH v3 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
2022-10-06 20:17 ` Rob Herring
2022-10-07 12:40 ` Biju Das
2022-10-08 7:42 ` Biju Das
2022-10-08 10:51 ` Biju Das
2022-10-09 14:38 ` Geert Uytterhoeven
2022-10-09 15:17 ` Krzysztof Kozlowski
2022-10-10 13:00 ` Biju Das
2022-10-10 7:10 ` Biju Das
2022-10-09 15:16 ` Krzysztof Kozlowski
2022-10-10 15:13 ` Biju Das
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