From: Jon Hunter <jonathanh@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
mturquette@baylibre.com, sboyd@codeaurora.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, lgirdwood@gmail.com,
broonie@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework
Date: Thu, 8 Mar 2018 22:26:40 +0000 [thread overview]
Message-ID: <4ccd7c38-45f5-03d2-cb28-84fd5f967401@nvidia.com> (raw)
In-Reply-To: <1517934852-23255-3-git-send-email-pdeschrijver@nvidia.com>
On 06/02/18 16:34, Peter De Schrijver wrote:
> The CVB table contains calibration data for the CPU DFLL based on
> process charaterization. The regulator step and offset parameters depend
> on the regulator supplying vdd-cpu , not on the specific Tegra SKU.
> Hence than hardcoding those regulator parameters in the CVB table,
> retrieve them from the regulator framework and store them as part of the
> tegra_dfll_soc_data struct.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-dfll.h | 2 ++
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 42 +++++++++++++++++++++++++-----
> drivers/clk/tegra/cvb.c | 16 +++++++++---
> drivers/clk/tegra/cvb.h | 6 ++---
> 4 files changed, 53 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h
> index 83352c8..e7cbc5b 100644
> --- a/drivers/clk/tegra/clk-dfll.h
> +++ b/drivers/clk/tegra/clk-dfll.h
> @@ -21,6 +21,7 @@
> #include <linux/platform_device.h>
> #include <linux/reset.h>
> #include <linux/types.h>
> +#include "cvb.h"
>
> /**
> * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
> @@ -35,6 +36,7 @@ struct tegra_dfll_soc_data {
> struct device *dev;
> unsigned long max_freq;
> const struct cvb_table *cvb;
> + struct rail_alignment alignment;
>
> void (*init_clock_trimmers)(void);
> void (*set_clock_trimmers_high)(void);
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index 269d359..e2dbb79 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -22,6 +22,7 @@
> #include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> #include <soc/tegra/fuse.h>
>
> #include "clk.h"
> @@ -42,9 +43,6 @@
> .process_id = -1,
> .min_millivolts = 900,
> .max_millivolts = 1260,
> - .alignment = {
> - .step_uv = 10000, /* 10mV */
> - },
> .speedo_scale = 100,
> .voltage_scale = 1000,
> .entries = {
> @@ -82,6 +80,34 @@
> },
> };
>
> +static int get_alignment_from_regulator(struct device *dev,
> + struct rail_alignment *align)
> +{
> + int min_uV, max_uV, n_voltages, ret;
> + struct regulator *reg;
> +
> + reg = devm_regulator_get(dev, "vdd-cpu");
> + if (IS_ERR(reg))
> + return PTR_ERR(reg);
> +
> + ret = regulator_get_constraint_voltages(reg, &min_uV, &max_uV);
> + if (!ret)
> + align->offset_uv = min_uV;
> + else
> + return ret;
Nit-pick ... looks a bit odd, why not ...
if (ret)
return ret;
align->offset_uv = min_uV;
> +
> + align->step_uv = regulator_get_linear_step(reg);
> + if (!align->step_uv && !ret) {
Do you need to test 'ret' here?
> + n_voltages = regulator_count_voltages(reg);
> + if (n_voltages > 1)
> + align->step_uv = (max_uV - min_uV) / (n_voltages - 1);
Later in the patch !align->step_uv is treated as an error, so if
n_voltages should always be greater 1 then why not return an error here?
Seems that this should not happen?
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2018-03-08 22:26 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver
[not found] ` <1517934852-23255-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-06 16:34 ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver
2018-02-06 16:35 ` Mark Brown
[not found] ` <20180206163544.GI5681-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07 8:47 ` Peter De Schrijver
2018-02-07 10:43 ` Mark Brown
[not found] ` <20180207104351.GA6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07 12:37 ` Peter De Schrijver
[not found] ` <20180207123750.GA5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 14:18 ` Mark Brown
2018-02-07 14:32 ` Peter De Schrijver
[not found] ` <20180207143213.GB5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:01 ` Mark Brown
2018-02-07 15:20 ` Peter De Schrijver
[not found] ` <20180207152045.GC5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:37 ` Mark Brown
[not found] ` <20180207153711.GE6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-08 10:04 ` Laxman Dewangan
[not found] ` <86cd40ac-d255-f4b9-87cb-0cd34efba7d8-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-08 14:58 ` Mark Brown
2018-02-06 16:34 ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver
2018-03-08 22:26 ` Jon Hunter [this message]
2018-02-06 16:34 ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver
2018-03-08 22:15 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver
2018-03-08 22:28 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver
2018-03-08 22:50 ` Jon Hunter
2018-03-12 9:14 ` Peter De Schrijver
2018-03-12 11:08 ` Jon Hunter
2018-03-13 9:03 ` Peter De Schrijver
2018-03-13 10:07 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding " Peter De Schrijver
[not found] ` <1517934852-23255-8-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-09 23:19 ` Rob Herring
2018-03-08 23:21 ` Jon Hunter
2018-03-12 9:10 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver
2018-03-08 23:25 ` Jon Hunter
2018-03-09 8:14 ` Peter De Schrijver
2018-03-12 10:14 ` Jon Hunter
2018-03-13 9:28 ` Peter De Schrijver
2018-03-09 9:11 ` Viresh Kumar
2018-03-12 12:15 ` Jon Hunter
2018-03-13 9:51 ` Peter De Schrijver
2018-03-13 10:20 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver
2018-03-08 23:15 ` Jon Hunter
2018-03-09 8:12 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver
2018-03-08 23:22 ` Jon Hunter
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