From: Jon Hunter <jonathanh@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
mturquette@baylibre.com, sboyd@codeaurora.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, lgirdwood@gmail.com,
broonie@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs
Date: Thu, 8 Mar 2018 22:15:51 +0000 [thread overview]
Message-ID: <80ee8493-6741-43dd-691a-eade94ec924f@nvidia.com> (raw)
In-Reply-To: <1517934852-23255-4-git-send-email-pdeschrijver@nvidia.com>
On 06/02/18 16:34, Peter De Schrijver wrote:
> In a future patch, support for the DFLL in Tegra210 will be introduced.
> This requires support for more than 1 set of CVB and CPU max frequency
> tables.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 37 ++++++++++++++++++++++++------
> 1 file changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index e2dbb79..6486ad9 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -21,6 +21,7 @@
> #include <linux/err.h>
> #include <linux/kernel.h>
> #include <linux/init.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/regulator/consumer.h>
> #include <soc/tegra/fuse.h>
> @@ -29,8 +30,15 @@
> #include "clk-dfll.h"
> #include "cvb.h"
>
> +struct dfll_fcpu_data {
> + const unsigned long *cpu_max_freq_table;
> + unsigned int cpu_max_freq_table_size;
> + const struct cvb_table *cpu_cvb_tables;
> + unsigned int cpu_cvb_tables_size;
> +};
> +
> /* Maximum CPU frequency, indexed by CPU speedo id */
> -static const unsigned long cpu_max_freq_table[] = {
> +static const unsigned long tegra124_cpu_max_freq_table[] = {
> [0] = 2014500000UL,
> [1] = 2320500000UL,
> [2] = 2116500000UL,
> @@ -80,6 +88,21 @@
> },
> };
>
> +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
> + .cpu_max_freq_table = tegra124_cpu_max_freq_table,
> + .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
> + .cpu_cvb_tables = tegra124_cpu_cvb_tables,
> + .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
> +};
> +
> +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> + {
> + .compatible = "nvidia,tegra124-dfll",
> + .data = &tegra124_dfll_fcpu_data,
> + },
> + { },
> +};
> +
> static int get_alignment_from_regulator(struct device *dev,
> struct rail_alignment *align)
> {
> @@ -112,12 +135,17 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
> {
> int process_id, speedo_id, speedo_value, err;
> struct tegra_dfll_soc_data *soc;
> + const struct of_device_id *of_id;
> + const struct dfll_fcpu_data *fcpu_data;
> +
> + of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev);
> + fcpu_data = of_id->data;
Nit-pick, we can use of_device_get_match_data() here.
> process_id = tegra_sku_info.cpu_process_id;
> speedo_id = tegra_sku_info.cpu_speedo_id;
> speedo_value = tegra_sku_info.cpu_speedo_value;
>
> - if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
> + if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
> dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
> speedo_id);
> return -ENODEV;
> @@ -172,11 +200,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> - { .compatible = "nvidia,tegra124-dfll", },
> - { },
> -};
> -
> static const struct dev_pm_ops tegra124_dfll_pm_ops = {
> SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
> tegra_dfll_runtime_resume, NULL)
>
Otherwise ...
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2018-03-08 22:15 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver
[not found] ` <1517934852-23255-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-06 16:34 ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver
2018-02-06 16:35 ` Mark Brown
[not found] ` <20180206163544.GI5681-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07 8:47 ` Peter De Schrijver
2018-02-07 10:43 ` Mark Brown
[not found] ` <20180207104351.GA6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-07 12:37 ` Peter De Schrijver
[not found] ` <20180207123750.GA5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 14:18 ` Mark Brown
2018-02-07 14:32 ` Peter De Schrijver
[not found] ` <20180207143213.GB5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:01 ` Mark Brown
2018-02-07 15:20 ` Peter De Schrijver
[not found] ` <20180207152045.GC5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-07 15:37 ` Mark Brown
[not found] ` <20180207153711.GE6003-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2018-02-08 10:04 ` Laxman Dewangan
[not found] ` <86cd40ac-d255-f4b9-87cb-0cd34efba7d8-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-08 14:58 ` Mark Brown
2018-02-06 16:34 ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver
2018-03-08 22:26 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver
2018-03-08 22:15 ` Jon Hunter [this message]
2018-02-06 16:34 ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver
2018-03-08 22:28 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver
2018-03-08 22:50 ` Jon Hunter
2018-03-12 9:14 ` Peter De Schrijver
2018-03-12 11:08 ` Jon Hunter
2018-03-13 9:03 ` Peter De Schrijver
2018-03-13 10:07 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding " Peter De Schrijver
[not found] ` <1517934852-23255-8-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2018-02-09 23:19 ` Rob Herring
2018-03-08 23:21 ` Jon Hunter
2018-03-12 9:10 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver
2018-03-08 23:25 ` Jon Hunter
2018-03-09 8:14 ` Peter De Schrijver
2018-03-12 10:14 ` Jon Hunter
2018-03-13 9:28 ` Peter De Schrijver
2018-03-09 9:11 ` Viresh Kumar
2018-03-12 12:15 ` Jon Hunter
2018-03-13 9:51 ` Peter De Schrijver
2018-03-13 10:20 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver
2018-03-08 23:15 ` Jon Hunter
2018-03-09 8:12 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver
2018-03-08 23:22 ` Jon Hunter
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