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From: Randy Dunlap <rdunlap@infradead.org>
To: Yash Shah <yash.shah@sifive.com>,
	robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
	bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com
Cc: aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	sachin.ghadi@sifive.com
Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
Date: Sun, 6 Sep 2020 22:54:29 -0700
Message-ID: <697413e6-8f44-8db4-6434-0f22984bdc9c@infradead.org> (raw)
In-Reply-To: <1599457679-8947-3-git-send-email-yash.shah@sifive.com>

On 9/6/20 10:47 PM, Yash Shah wrote:
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c4..f41d8fe 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -7,4 +7,10 @@ config SIFIVE_L2
>  	help
>  	  Support for the L2 cache controller on SiFive platforms.
>  
> +config SIFIVE_DDR
> +	bool "Sifive DDR controller driver"
> +	help
> +	  Support for the management of cadence DDR controller on SiFive

	                                Cadence

> +	  platforms.
> +
>  endif


-- 
~Randy


  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07  5:47 [PATCH v2 0/3] SiFive DDR controller and EDAC support Yash Shah
2020-09-07  5:47 ` [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-09-15 15:24   ` Rob Herring
2020-09-07  5:47 ` [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-09-07  5:54   ` Randy Dunlap [this message]
2020-09-07  6:11   ` Christoph Hellwig
2020-09-09  3:12     ` Palmer Dabbelt
2020-09-09  3:56       ` Yash Shah
2020-09-09  6:00       ` Christoph Hellwig
2020-09-09 20:31         ` Palmer Dabbelt
2020-09-17  9:56       ` Dhananjay Vilasrao Kangude
2020-09-07  5:47 ` [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-09-23 17:10   ` Borislav Petkov
2020-09-15 15:22 ` [PATCH v2 0/3] SiFive DDR controller and EDAC support Rob Herring

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