From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, lukas@wunner.de
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v3 1/4] Documentation: fpga: dfl: Add documentation for DFHv1
Date: Tue, 4 Oct 2022 07:37:15 -0700 [thread overview]
Message-ID: <20221004143718.1076710-2-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20221004143718.1076710-1-matthew.gerlach@linux.intel.com>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Add documentation describing the extensions provided by Version
1 of the Device Feature Header (DFHv1).
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v3: no change
v2: s/GUILD/GUID/
add picture
---
Documentation/fpga/dfl.rst | 49 ++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 15b670926084..7c786b75b498 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -561,6 +561,55 @@ new DFL feature via UIO direct access, its feature id should be added to the
driver's id_table.
+Extending the Device Feature Header - DFHv1
+===========================================
+The current 8 bytes of the Device Feature Header, hereafter referred to as
+to DFHv0, provide very little opportunity for the hardware to describe itself
+to software. Version 1 of the Device Feature Header (DFHv1) is being introduced
+to provide increased flexibility and extensibility to hardware designs using
+Device Feature Lists. The list below describes some of the goals behind the
+changes in DFHv1:
+
+* Provide a standardized mechanism for features to describe
+ parameters/capabilities to software.
+* Standardize the use of a GUID for all DFHv1 types.
+* Decouple the location of the DFH from the register space of the feature itself.
+
+Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate
+a list of parameter values to a particular feature.
+
+With DFHv0, not all features types contained a GUID. DFHv1 makes the GUID standard
+across all types.
+
+With DFHv0, the register map of a given feature is located immediately following
+the DFHv0 in the memory space. With DFHv1, the location of the feature register
+map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1
+structure is shown below:
+
+ +-----------------------------------------------------------------------+
+ |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0|
+ +-----------------------------------------------------------------------+
+ |63 GUID_L 0|
+ +-----------------------------------------------------------------------+
+ |63 GUID_H 0|
+ +-----------------------------------------------------------------------+
+ |63 Address/Offset 1| Rel 0|
+ +-----------------------------------------------------------------------+
+ |63 Size of register set 32|Params 31|30 Group 16|15 Instance 0|
+ +-----------------------------------------------------------------------+
+ |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0|
+ +-----------------------------------------------------------------------+
+ |63 Parameter Data 0|
+ +-----------------------------------------------------------------------+
+
+ ...
+
+ +-----------------------------------------------------------------------+
+ |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0|
+ +-----------------------------------------------------------------------+
+ |63 Parameter Data 0|
+ +-----------------------------------------------------------------------+
+
Open discussion
===============
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
--
2.25.1
next prev parent reply other threads:[~2022-10-04 14:39 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 14:37 [PATCH v3 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-04 14:37 ` matthew.gerlach [this message]
2022-10-05 11:05 ` [PATCH v3 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Ilpo Järvinen
2022-10-10 17:34 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-04 14:55 ` Andy Shevchenko
2022-10-04 14:37 ` [PATCH v3 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-10-04 15:11 ` Andy Shevchenko
2022-10-06 9:47 ` Xu Yilun
2022-10-10 15:34 ` matthew.gerlach
2022-10-05 10:30 ` Ilpo Järvinen
2022-10-07 18:35 ` matthew.gerlach
2022-10-06 9:27 ` Xu Yilun
2022-10-10 16:58 ` matthew.gerlach
2022-10-11 6:28 ` Xu Yilun
2022-10-12 0:31 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-04 15:31 ` Andy Shevchenko
2022-10-06 17:00 ` matthew.gerlach
2022-10-06 17:44 ` Andy Shevchenko
2022-10-06 22:24 ` matthew.gerlach
2022-10-07 9:15 ` Andy Shevchenko
2022-10-07 15:10 ` matthew.gerlach
2022-10-07 15:28 ` Andy Shevchenko
2022-10-05 10:47 ` Ilpo Järvinen
2022-10-06 21:47 ` matthew.gerlach
2022-10-10 14:53 ` Marco Pagani
2022-10-10 19:42 ` matthew.gerlach
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221004143718.1076710-2-matthew.gerlach@linux.intel.com \
--to=matthew.gerlach@linux.intel.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=basheer.ahmed.muddebihal@intel.com \
--cc=corbet@lwn.net \
--cc=geert+renesas@glider.be \
--cc=gregkh@linuxfoundation.org \
--cc=hao.wu@intel.com \
--cc=jirislaby@kernel.org \
--cc=johan@kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-fpga@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=macro@orcam.me.uk \
--cc=mdf@kernel.org \
--cc=niklas.soderlund+renesas@ragnatech.se \
--cc=russell.h.weight@intel.com \
--cc=tianfei.zhang@intel.com \
--cc=trix@redhat.com \
--cc=yilun.xu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).