From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
tianfei.zhang@intel.com, corbet@lwn.net,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-serial <linux-serial@vger.kernel.org>,
Jiri Slaby <jirislaby@kernel.org>,
geert+renesas@glider.be,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, Lukas Wunner <lukas@wunner.de>,
kernel test robot <lkp@intel.com>
Subject: Re: [PATCH v3 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550.
Date: Wed, 5 Oct 2022 13:47:08 +0300 (EEST) [thread overview]
Message-ID: <d75abf9c-e982-563f-b2-d5a376367b1e@linux.intel.com> (raw)
In-Reply-To: <20221004143718.1076710-5-matthew.gerlach@linux.intel.com>
On Tue, 4 Oct 2022, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Add a Device Feature List (DFL) bus driver for the Altera
> 16550 implementation of UART.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Reported-by: kernel test robot <lkp@intel.com>
> ---
> v3: use passed in location of registers
> use cleaned up functions for parsing parameters
>
> v2: clean up error messages
> alphabetize header files
> fix 'missing prototype' error by making function static
> tried to sort Makefile and Kconfig better
> ---
> drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++
> drivers/tty/serial/8250/Kconfig | 9 ++
> drivers/tty/serial/8250/Makefile | 1 +
> 3 files changed, 187 insertions(+)
> create mode 100644 drivers/tty/serial/8250/8250_dfl.c
>
> diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c
> new file mode 100644
> index 000000000000..110ad3a73459
> --- /dev/null
> +++ b/drivers/tty/serial/8250/8250_dfl.c
> @@ -0,0 +1,177 @@
> +static int dfl_uart_get_params(struct device *dev, void __iomem *dfh_base, resource_size_t max,
> + struct uart_8250_port *uart)
> +{
> + u64 v, fifo_len, reg_width;
> + int off;
> +
> + if (!dfhv1_has_params(dfh_base)) {
> + dev_err(dev, "missing required DFH parameters\n");
> + return -EINVAL;
> + }
> +
> + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_CLK_FRQ);
> + if (off < 0) {
> + dev_err(dev, "missing CLK_FRQ param\n");
> + return -EINVAL;
> + }
> +
> + uart->port.uartclk = readq(dfh_base + off);
> + dev_dbg(dev, "UART_CLK_ID %u Hz\n", uart->port.uartclk);
> +
> + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_FIFO_LEN);
> + if (off < 0) {
> + dev_err(dev, "missing FIFO_LEN param\n");
> + return -EINVAL;
> + }
> +
> + fifo_len = readq(dfh_base + off);
> + dev_dbg(dev, "UART_FIFO_ID fifo_len %llu\n", fifo_len);
> +
> + switch (fifo_len) {
> + case 32:
> + uart->port.type = PORT_ALTR_16550_F32;
> + break;
> +
> + case 64:
> + uart->port.type = PORT_ALTR_16550_F64;
> + break;
> +
> + case 128:
> + uart->port.type = PORT_ALTR_16550_F128;
> + break;
> +
> + default:
> + dev_err(dev, "bad fifo_len %llu\n", fifo_len);
I'd tell user "unsupported" rather than "bad".
> + return -EINVAL;
> + }
> +
> + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_REG_LAYOUT);
> + if (off < 0) {
> + dev_err(dev, "missing REG_LAYOUT param\n");
> + return -EINVAL;
> + }
> +
> + v = readq(dfh_base + off);
> + uart->port.regshift = FIELD_GET(DFHv1_PARAM_ID_REG_SHIFT, v);
> + reg_width = FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v);
> +
> + dev_dbg(dev, "UART_LAYOUT_ID width %lld shift %d\n",
> + FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v), (int)uart->port.regshift);
Why not use reg_width directly?
> + switch (reg_width) {
> + case 4:
> + uart->port.iotype = UPIO_MEM32;
> + break;
> +
> + case 2:
> + uart->port.iotype = UPIO_MEM16;
> + break;
> +
> + default:
> + dev_err(dev, "invalid reg_width %lld\n", reg_width);
unsupported ?
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int dfl_uart_probe(struct dfl_device *dfl_dev)
> +{
> + struct device *dev = &dfl_dev->dev;
> + struct uart_8250_port uart;
> + struct dfl_uart *dfluart;
> + resource_size_t res_size;
> + void __iomem *dfh_base;
> + int ret;
> +
> + memset(&uart, 0, sizeof(uart));
> + uart.port.flags = UPF_IOREMAP;
> + uart.port.mapbase = dfl_dev->csr_res.start;
> + uart.port.mapsize = resource_size(&dfl_dev->csr_res);
> +
> + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL);
> + if (!dfluart)
> + return -ENOMEM;
> +
> + dfh_base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> + if (IS_ERR(dfh_base))
> + return PTR_ERR(dfh_base);
> +
> + res_size = resource_size(&dfl_dev->mmio_res);
> +
> + ret = dfl_uart_get_params(dev, dfh_base, res_size, &uart);
> +
> + devm_iounmap(dev, dfh_base);
> + devm_release_mem_region(dev, dfl_dev->mmio_res.start, res_size);
> +
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "failed uart feature walk\n");
> +
> + dev_dbg(dev, "nr_irqs %d %p\n", dfl_dev->num_irqs, dfl_dev->irqs);
> +
> + if (dfl_dev->num_irqs == 1)
> + uart.port.irq = dfl_dev->irqs[0];
> +
> + /* register the port */
This comment is pretty useless. Just drop it.
> + dfluart->line = serial8250_register_8250_port(&uart);
> + if (dfluart->line < 0)
> + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n");
> +
> + dev_info(dev, "serial8250_register_8250_port %d\n", dfluart->line);
This you want to drop too. It seems a debug thing rather than info level
stuff.
--
i.
next prev parent reply other threads:[~2022-10-05 10:49 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 14:37 [PATCH v3 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-05 11:05 ` Ilpo Järvinen
2022-10-10 17:34 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-04 14:55 ` Andy Shevchenko
2022-10-04 14:37 ` [PATCH v3 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-10-04 15:11 ` Andy Shevchenko
2022-10-06 9:47 ` Xu Yilun
2022-10-10 15:34 ` matthew.gerlach
2022-10-05 10:30 ` Ilpo Järvinen
2022-10-07 18:35 ` matthew.gerlach
2022-10-06 9:27 ` Xu Yilun
2022-10-10 16:58 ` matthew.gerlach
2022-10-11 6:28 ` Xu Yilun
2022-10-12 0:31 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-04 15:31 ` Andy Shevchenko
2022-10-06 17:00 ` matthew.gerlach
2022-10-06 17:44 ` Andy Shevchenko
2022-10-06 22:24 ` matthew.gerlach
2022-10-07 9:15 ` Andy Shevchenko
2022-10-07 15:10 ` matthew.gerlach
2022-10-07 15:28 ` Andy Shevchenko
2022-10-05 10:47 ` Ilpo Järvinen [this message]
2022-10-06 21:47 ` matthew.gerlach
2022-10-10 14:53 ` Marco Pagani
2022-10-10 19:42 ` matthew.gerlach
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