From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, lukas@wunner.de,
Basheer Ahmed Muddebihal
<basheer.ahmed.muddebihal@linux.intel.com>
Subject: Re: [PATCH v3 2/4] fpga: dfl: Add DFHv1 Register Definitions
Date: Tue, 4 Oct 2022 17:55:01 +0300 [thread overview]
Message-ID: <YzxJRcdnvm1rWROK@smile.fi.intel.com> (raw)
In-Reply-To: <20221004143718.1076710-3-matthew.gerlach@linux.intel.com>
On Tue, Oct 04, 2022 at 07:37:16AM -0700, matthew.gerlach@linux.intel.com wrote:
> From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
>
> This patch adds the definitions for DFHv1 header and related register
> bitfields.
...
> - * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + * Copyright (C) 2017-2022 Intel Corporation, Inc.
I do not think this is correct.
What happened to the code in 2019, 2020, and 2021? It's unclear. Have you
consulted with our lawyer about this?
That said, I _think_ (not your lawyer though) that the correct one should be
* Copyright (C) 2017-2018,2022 Intel Corporation, Inc.
If you wanted to correct that, perhaps it should be done in a separate patch
first with explanation for those years in the gap. Unfortunately I haven't
found any description for those.
Ditto for the rest similar cases.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-10-04 14:56 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 14:37 [PATCH v3 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-05 11:05 ` Ilpo Järvinen
2022-10-10 17:34 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-04 14:55 ` Andy Shevchenko [this message]
2022-10-04 14:37 ` [PATCH v3 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-10-04 15:11 ` Andy Shevchenko
2022-10-06 9:47 ` Xu Yilun
2022-10-10 15:34 ` matthew.gerlach
2022-10-05 10:30 ` Ilpo Järvinen
2022-10-07 18:35 ` matthew.gerlach
2022-10-06 9:27 ` Xu Yilun
2022-10-10 16:58 ` matthew.gerlach
2022-10-11 6:28 ` Xu Yilun
2022-10-12 0:31 ` matthew.gerlach
2022-10-04 14:37 ` [PATCH v3 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-04 15:31 ` Andy Shevchenko
2022-10-06 17:00 ` matthew.gerlach
2022-10-06 17:44 ` Andy Shevchenko
2022-10-06 22:24 ` matthew.gerlach
2022-10-07 9:15 ` Andy Shevchenko
2022-10-07 15:10 ` matthew.gerlach
2022-10-07 15:28 ` Andy Shevchenko
2022-10-05 10:47 ` Ilpo Järvinen
2022-10-06 21:47 ` matthew.gerlach
2022-10-10 14:53 ` Marco Pagani
2022-10-10 19:42 ` matthew.gerlach
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