* [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support
@ 2020-08-17 1:46 Nobuhiro Iwamatsu
2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon
Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel,
linux-gpio, Nobuhiro Iwamatsu
Hi,
Visconti is a series of Toshiba's SoCs targeting image processing
applications[0]. These set of patches adds support for Visconti5 a Arm
v8 based SoC.
The series add minimal support for the Visconti5 SoC and the TMPV7708 RM
main board. Peripherals such as UART, SPI, I2c and timer use Arm's
IP and work with the existing kernel drivers in the tree. The series
includes a pinctrl driver to select appropriate functions on the pins.
NOTE: Because Visconti5 does not have PSCI, it uses spin-table with enable-method.
And this patch series does not include a clock framework, so it is a
device-tree file that uses clocks with fixed-clock. This will be replaced by
the clock driver in the future.
[0]: https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html
Best regards,
Nobuhiro
Nobuhiro Iwamatsu (8):
dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC
pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support
dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs
dt-bindings: arm: toshiba: Add the TMPV7708 RM main board
arm64: visconti: Add initial support for Toshiba Visconti platform
arm64: dts: visconti: Add device tree for TMPV7708 RM main board
MAINTAINERS: Add information for Toshiba Visconti ARM SoCs
arm64: defconfig: Enable configs for Toshiba Visconti
.../devicetree/bindings/arm/toshiba.yaml | 22 +
.../pinctrl/toshiba,visconti-pinctrl.yaml | 82 ++++
MAINTAINERS | 11 +
arch/arm64/Kconfig.platforms | 7 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/toshiba/Makefile | 2 +
.../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 44 ++
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++
.../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++
arch/arm64/configs/defconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/visconti/Kconfig | 14 +
drivers/pinctrl/visconti/Makefile | 3 +
drivers/pinctrl/visconti/pinctrl-common.c | 320 ++++++++++++++
drivers/pinctrl/visconti/pinctrl-common.h | 96 +++++
drivers/pinctrl/visconti/pinctrl-tmpv7700.c | 355 ++++++++++++++++
17 files changed, 1443 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/toshiba.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/toshiba/Makefile
create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
create mode 100644 drivers/pinctrl/visconti/Kconfig
create mode 100644 drivers/pinctrl/visconti/Makefile
create mode 100644 drivers/pinctrl/visconti/pinctrl-common.c
create mode 100644 drivers/pinctrl/visconti/pinctrl-common.h
create mode 100644 drivers/pinctrl/visconti/pinctrl-tmpv7700.c
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 19:46 ` Rob Herring 2020-08-17 19:48 ` Rob Herring 2020-08-17 1:46 ` [PATCH 2/8] pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support Nobuhiro Iwamatsu ` (6 subsequent siblings) 7 siblings, 2 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml new file mode 100644 index 000000000000..4009902cd396 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti TMPV770x pin mux/config controller + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshiba's Visconti ARM SoC a pin mux/config controller. + +properties: + compatible: + enum: + - toshiba,tmpv7708-pinctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + '^.*$': + if: + type: object + then: + properties: + function: + description: + Function to mux. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, + spi0, spi1, spi2, spi3, spi4, spi5, spi6, + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] + + groups: + description: + Name of the pin group to use for the functions. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, + uart0_grp, uart1_grp, uart2_grp, uart3_grp, + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] + + drive-strength: + enum: [2, 4, 6, 8, 16, 24, 32] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + + spi_0: spi_0 { + function = "spi0"; + groups = "spi0_grp"; + }; + }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC 2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu @ 2020-08-17 19:46 ` Rob Herring 2020-08-19 5:33 ` Nobuhiro Iwamatsu 2020-08-17 19:48 ` Rob Herring 1 sibling, 1 reply; 17+ messages in thread From: Rob Herring @ 2020-08-17 19:46 UTC (permalink / raw) To: Nobuhiro Iwamatsu Cc: punit1.agrawal, linux-arm-kernel, Linus Walleij, linux-gpio, Rob Herring, Will Deacon, devicetree, Catalin Marinas, yuji2.ishikawa On Mon, 17 Aug 2020 10:46:25 +0900, Nobuhiro Iwamatsu wrote: > Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > --- > .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > My bot found errors running 'make dt_binding_check' on your patch: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.example.dt.yaml: example-0: pmux@24190000:reg:0: [0, 605618176, 0, 65536] is too long See https://patchwork.ozlabs.org/patch/1345570 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC 2020-08-17 19:46 ` Rob Herring @ 2020-08-19 5:33 ` Nobuhiro Iwamatsu 0 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-19 5:33 UTC (permalink / raw) To: Rob Herring Cc: punit1.agrawal, linux-arm-kernel, Linus Walleij, linux-gpio, Rob Herring, Will Deacon, devicetree, Catalin Marinas, yuji2.ishikawa Hi, Thanks for your review. On Mon, Aug 17, 2020 at 01:46:27PM -0600, Rob Herring wrote: > On Mon, 17 Aug 2020 10:46:25 +0900, Nobuhiro Iwamatsu wrote: > > Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. > > > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > --- > > .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.example.dt.yaml: example-0: pmux@24190000:reg:0: [0, 605618176, 0, 65536] is too long > > > See https://patchwork.ozlabs.org/patch/1345570 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade > > Please check and re-submit. > Thanks, I will fix this. Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC 2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu 2020-08-17 19:46 ` Rob Herring @ 2020-08-17 19:48 ` Rob Herring 2020-08-19 5:35 ` Nobuhiro Iwamatsu 1 sibling, 1 reply; 17+ messages in thread From: Rob Herring @ 2020-08-17 19:48 UTC (permalink / raw) To: Nobuhiro Iwamatsu Cc: Linus Walleij, Catalin Marinas, Will Deacon, punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio On Mon, Aug 17, 2020 at 10:46:25AM +0900, Nobuhiro Iwamatsu wrote: > Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > --- > .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > new file mode 100644 > index 000000000000..4009902cd396 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba Visconti TMPV770x pin mux/config controller > + > +maintainers: > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > + > +description: > + Toshiba's Visconti ARM SoC a pin mux/config controller. > + > +properties: > + compatible: > + enum: > + - toshiba,tmpv7708-pinctrl > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +patternProperties: > + '^.*$': For new bindings, please define something like '-pins$' for the pin nodes. > + if: > + type: object > + then: Then we don't have to do this if/then. This also needs a $ref to the common pinctrl schemas. > + properties: > + function: > + description: > + Function to mux. > + $ref: "/schemas/types.yaml#/definitions/string" > + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, > + spi0, spi1, spi2, spi3, spi4, spi5, spi6, > + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] > + > + groups: > + description: > + Name of the pin group to use for the functions. > + $ref: "/schemas/types.yaml#/definitions/string" > + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, > + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, > + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, > + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, > + uart0_grp, uart1_grp, uart2_grp, uart3_grp, > + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, > + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, > + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, > + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, > + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, > + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] > + > + drive-strength: > + enum: [2, 4, 6, 8, 16, 24, 32] > + default: 2 > + description: > + Selects the drive strength for the specified pins, in mA. > + > + bias-pull-up: true > + > + bias-pull-down: true > + > + bias-disable: true > + > +additionalProperties: false > + > +examples: > + # Pinmux controller node > + - | > + pmux: pmux@24190000 { > + compatible = "toshiba,tmpv7708-pinctrl"; > + reg = <0 0x24190000 0 0x10000>; > + > + spi_0: spi_0 { > + function = "spi0"; > + groups = "spi0_grp"; > + }; > + }; > -- > 2.27.0 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC 2020-08-17 19:48 ` Rob Herring @ 2020-08-19 5:35 ` Nobuhiro Iwamatsu 0 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-19 5:35 UTC (permalink / raw) To: Rob Herring Cc: Linus Walleij, Catalin Marinas, Will Deacon, punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio Hi, Thanks for your review. On Mon, Aug 17, 2020 at 01:48:33PM -0600, Rob Herring wrote: > On Mon, Aug 17, 2020 at 10:46:25AM +0900, Nobuhiro Iwamatsu wrote: > > Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. > > > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > --- > > .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > new file mode 100644 > > index 000000000000..4009902cd396 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Toshiba Visconti TMPV770x pin mux/config controller > > + > > +maintainers: > > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > + > > +description: > > + Toshiba's Visconti ARM SoC a pin mux/config controller. > > + > > +properties: > > + compatible: > > + enum: > > + - toshiba,tmpv7708-pinctrl > > + > > + reg: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + > > +patternProperties: > > + '^.*$': > > For new bindings, please define something like '-pins$' for the pin > nodes. OK, I will update. > > > + if: > > + type: object > > + then: > > Then we don't have to do this if/then. > > This also needs a $ref to the common pinctrl schemas. > OK, I will fix this. > > + properties: > > + function: > > + description: > > + Function to mux. > > + $ref: "/schemas/types.yaml#/definitions/string" > > + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, > > + spi0, spi1, spi2, spi3, spi4, spi5, spi6, > > + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] > > + Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/8] pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 3/8] dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu ` (5 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add pinctrl support to Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/visconti/Kconfig | 14 + drivers/pinctrl/visconti/Makefile | 3 + drivers/pinctrl/visconti/pinctrl-common.c | 320 ++++++++++++++++++ drivers/pinctrl/visconti/pinctrl-common.h | 96 ++++++ drivers/pinctrl/visconti/pinctrl-tmpv7700.c | 355 ++++++++++++++++++++ 7 files changed, 790 insertions(+) create mode 100644 drivers/pinctrl/visconti/Kconfig create mode 100644 drivers/pinctrl/visconti/Makefile create mode 100644 drivers/pinctrl/visconti/pinctrl-common.c create mode 100644 drivers/pinctrl/visconti/pinctrl-common.h create mode 100644 drivers/pinctrl/visconti/pinctrl-tmpv7700.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8828613c4e0e..6f62b9bb79bb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -429,6 +429,7 @@ source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/zte/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/visconti/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1731b2154df9..576cbedcbf73 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_ZX) += zte/ obj-y += cirrus/ +obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ diff --git a/drivers/pinctrl/visconti/Kconfig b/drivers/pinctrl/visconti/Kconfig new file mode 100644 index 000000000000..198ec33189cc --- /dev/null +++ b/drivers/pinctrl/visconti/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_VISCONTI + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + +config PINCTRL_TMPV7700 + bool "Toshiba Visconti TMPV7700 series pinctrl driver" + depends on OF + depends on ARM64 || COMPILE_TEST + select PINCTRL_VISCONTI + default ARM64 && ARCH_VISCONTI diff --git a/drivers/pinctrl/visconti/Makefile b/drivers/pinctrl/visconti/Makefile new file mode 100644 index 000000000000..43b2eb663bce --- /dev/null +++ b/drivers/pinctrl/visconti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PINCTRL_VISCONTI) += pinctrl-common.o +obj-$(CONFIG_PINCTRL_TMPV7700) += pinctrl-tmpv7700.o diff --git a/drivers/pinctrl/visconti/pinctrl-common.c b/drivers/pinctrl/visconti/pinctrl-common.c new file mode 100644 index 000000000000..3f7661867394 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#include <linux/init.h> +#include <linux/of.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include "pinctrl-common.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" + +#define SET_BIT(data, idx) ((data) |= BIT(idx)) +#define CLR_BIT(data, idx) ((data) &= ~BIT(idx)) + +/* private data */ +struct visconti_pinctrl { + void __iomem *base; + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + + const struct visconti_pinctrl_devdata *devdata; + + spinlock_t lock; +}; + +/* pinconf */ +static int visconti_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin]; + enum pin_config_param param; + unsigned int arg; + int i, ret = 0; + unsigned int val, set_val, pude_val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name); + + spin_lock_irqsave(&priv->lock, flags); + + for (i = 0; i < num_configs; i++) { + set_val = 0; + pude_val = 0; + + param = pinconf_to_config_param(configs[i]); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + set_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_PULL_DOWN: + /* update pudsel setting */ + val = readl(priv->base + pin->pudsel_offset); + CLR_BIT(val, pin->pud_shift); + val |= set_val << pin->pud_shift; + writel(val, priv->base + pin->pudsel_offset); + pude_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_DISABLE: + /* update pude setting */ + val = readl(priv->base + pin->pude_offset); + CLR_BIT(val, pin->pud_shift); + val |= pude_val << pin->pud_shift; + writel(val, priv->base + pin->pude_offset); + dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n", + param, pin->pude_offset, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(configs[i]); + dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg); + switch (arg) { + case 2: + case 4: + case 8: + case 16: + case 24: + case 32: + set_val = (arg / 2) - 1; + break; + default: + ret = -EINVAL; + goto err; + } + /* update drive setting */ + val = readl(priv->base + pin->dsel_offset); + val &= ~(GENMASK(3, 0) << pin->dsel_shift); + val |= set_val << pin->dsel_shift; + writel(val, priv->base + pin->dsel_offset); + break; + + default: + ret = -EOPNOTSUPP; + goto err; + } + } +err: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int num_pins; + int i, ret; + + pins = priv->devdata->groups[selector].pins; + num_pins = priv->devdata->groups[selector].nr_pins; + + dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n", + __func__, selector, num_pins, num_configs); + + for (i = 0; i < num_pins; i++) { + ret = visconti_pin_config_set(pctldev, pins[i], + configs, num_configs); + if (ret) + return ret; + } + + return 0; +} +static const struct pinconf_ops visconti_pinconf_ops = { + .is_generic = true, + .pin_config_set = visconti_pin_config_set, + .pin_config_group_set = visconti_pin_config_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* pinctrl */ +static int visconti_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_groups; +} + +static const char *visconti_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->groups[selector].name; +} + +static int visconti_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *pins = priv->devdata->groups[selector].pins; + *num_pins = priv->devdata->groups[selector].nr_pins; + + return 0; +} + +static const struct pinctrl_ops visconti_pinctrl_ops = { + .get_groups_count = visconti_get_groups_count, + .get_group_name = visconti_get_group_name, + .get_group_pins = visconti_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +/* pinmnux */ +static int visconti_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_functions; +} + +static const char *visconti_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->functions[selector].name; +} + +static int visconti_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = priv->devdata->functions[selector].groups; + *num_groups = priv->devdata->functions[selector].nr_groups; + + return 0; +} + +static int visconti_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_pin_function *func = &priv->devdata->functions[function]; + const struct visconti_pin_group *grp = &priv->devdata->groups[group]; + const struct visconti_mux *mux = &grp->mux; + unsigned int val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__, + function, func->name, group, grp->name); + + spin_lock_irqsave(&priv->lock, flags); + + /* update mux */ + val = readl(priv->base + mux->offset); + val &= ~mux->mask; + val |= mux->val; + writel(val, priv->base + mux->offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val); + + return 0; +} + +static int visconti_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_mux *gpio_mux = &priv->devdata->gpio_mux[pin]; + unsigned long flags; + unsigned int val; + + dev_dbg(priv->dev, "%s: pin = %d\n", __func__, pin); + + /* update mux */ + spin_lock_irqsave(&priv->lock, flags); + val = readl(priv->base + gpio_mux->offset); + val &= ~gpio_mux->mask; + val |= gpio_mux->val; + writel(val, priv->base + gpio_mux->offset); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct pinmux_ops visconti_pinmux_ops = { + .get_functions_count = visconti_get_functions_count, + .get_function_name = visconti_get_function_name, + .get_function_groups = visconti_get_function_groups, + .set_mux = visconti_set_mux, + .gpio_request_enable = visconti_gpio_request_enable, + .strict = true, +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata) +{ + struct device *dev = &pdev->dev; + struct visconti_pinctrl *priv; + struct pinctrl_pin_desc *pins; + int i, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->devdata = devdata; + spin_lock_init(&priv->lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) { + dev_err(dev, "unable to map I/O space\n"); + return PTR_ERR(priv->base); + } + + pins = devm_kcalloc(dev, devdata->nr_pins, + sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < devdata->nr_pins; i++) + pins[i] = devdata->pins[i].pin; + + priv->pctl_desc.name = dev_name(dev); + priv->pctl_desc.owner = THIS_MODULE; + priv->pctl_desc.pins = pins; + priv->pctl_desc.npins = devdata->nr_pins; + priv->pctl_desc.confops = &visconti_pinconf_ops; + priv->pctl_desc.pctlops = &visconti_pinctrl_ops; + priv->pctl_desc.pmxops = &visconti_pinmux_ops; + + ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc, + priv, &priv->pctl); + if (ret) { + dev_err(dev, "couldn't register pinctrl: %d\n", ret); + return ret; + } + + if (devdata->unlock) + devdata->unlock(priv->base); + + return pinctrl_enable(priv->pctl); +} diff --git a/drivers/pinctrl/visconti/pinctrl-common.h b/drivers/pinctrl/visconti/pinctrl-common.h new file mode 100644 index 000000000000..56a2eb0225fb --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#ifndef __VISCONTI_PINCTRL_COMMON_H__ +#define __VISCONTI_PINCTRL_COMMON_H__ + +struct pinctrl_pin_desc; + +/* PIN */ +#define VISCONTI_PINS(pins_name, ...) \ + static const unsigned int pins_name ## _pins[] = { __VA_ARGS__ } + +struct visconti_desc_pin { + struct pinctrl_pin_desc pin; + unsigned int dsel_offset; + unsigned int dsel_shift; + unsigned int pude_offset; + unsigned int pudsel_offset; + unsigned int pud_shift; +}; + +#define VISCONTI_PIN(_pin, dsel, d_sh, pude, pudsel, p_sh) \ +{ \ + .pin = _pin, \ + .dsel_offset = dsel, \ + .dsel_shift = d_sh, \ + .pude_offset = pude, \ + .pudsel_offset = pudsel, \ + .pud_shift = p_sh, \ +} + +/* Group */ +#define VISCONTI_GROUPS(groups_name, ...) \ + static const char * const groups_name ## _grps[] = { __VA_ARGS__ } + +struct visconti_mux { + unsigned int offset; + unsigned int mask; + unsigned int val; +}; + +struct visconti_pin_group { + const char *name; + const unsigned int *pins; + unsigned int nr_pins; + struct visconti_mux mux; +}; + +#define VISCONTI_PIN_GROUP(group_name, off, msk, v) \ +{ \ + .name = __stringify(group_name) "_grp", \ + .pins = group_name ## _pins, \ + .nr_pins = ARRAY_SIZE(group_name ## _pins), \ + .mux = { \ + .offset = off, \ + .mask = msk, \ + .val = v, \ + } \ +} + +/* MUX */ +struct visconti_pin_function { + const char *name; + const char * const *groups; + unsigned int nr_groups; +}; + +#define VISCONTI_PIN_FUNCTION(func) \ +{ \ + .name = #func, \ + .groups = func ## _grps, \ + .nr_groups = ARRAY_SIZE(func ## _grps), \ +} + +/* chip dependent data */ +struct visconti_pinctrl_devdata { + const struct visconti_desc_pin *pins; + unsigned int nr_pins; + const struct visconti_pin_group *groups; + unsigned int nr_groups; + const struct visconti_pin_function *functions; + unsigned int nr_functions; + + const struct visconti_mux *gpio_mux; + + void (*unlock)(void __iomem *base); +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata); + +#endif /* __VISCONTI_PINCTRL_COMMON_H__ */ diff --git a/drivers/pinctrl/visconti/pinctrl-tmpv7700.c b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c new file mode 100644 index 000000000000..38a00d514f74 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-common.h" + +#define tmpv7700_MAGIC_NUM 0x4932f70e + +/* register offset */ +#define REG_KEY_CTRL 0x0000 +#define REG_KEY_CMD 0x0004 +#define REG_PINMUX1 0x3000 +#define REG_PINMUX2 0x3004 +#define REG_PINMUX3 0x3008 +#define REG_PINMUX4 0x300c +#define REG_PINMUX5 0x3010 +#define REG_IOSET 0x3014 +#define REG_IO_VSEL 0x3018 +#define REG_IO_DSEL1 0x301c +#define REG_IO_DSEL2 0x3020 +#define REG_IO_DSEL3 0x3024 +#define REG_IO_DSEL4 0x3028 +#define REG_IO_DSEL5 0x302c +#define REG_IO_DSEL6 0x3030 +#define REG_IO_DSEL7 0x3034 +#define REG_IO_DSEL8 0x3038 +#define REG_IO_PUDE1 0x303c +#define REG_IO_PUDE2 0x3040 +#define REG_IO_PUDSEL1 0x3044 +#define REG_IO_PUDSEL2 0x3048 + +/* PIN */ +static const struct visconti_desc_pin pins_tmpv7700[] = { + VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24, + REG_IO_PUDE1, REG_IO_PUDSEL1, 30), + VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28, + REG_IO_PUDE1, REG_IO_PUDSEL1, 31), + VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 0), + VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 1), + VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 2), + VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 3), + VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 4), + VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 5), + VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 6), + VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 7), + VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 8), + VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 9), + VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 10), + VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 11), + VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 12), + VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 13), + VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 14), + VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 15), + VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 16), + VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 17), + VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 18), + VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 19), + VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 20), + VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 21), + VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 22), + VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 23), + VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 24), + VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 25), + VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 26), + VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8, + REG_IO_PUDE1, REG_IO_PUDSEL1, 26), + VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4, + REG_IO_PUDE1, REG_IO_PUDSEL1, 25), + VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0, + REG_IO_PUDE1, REG_IO_PUDSEL1, 24), + VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12, + REG_IO_PUDE1, REG_IO_PUDSEL1, 27), + VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16, + REG_IO_PUDE1, REG_IO_PUDSEL1, 28), + VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20, + REG_IO_PUDE1, REG_IO_PUDSEL1, 29), +}; + +/* Group */ +VISCONTI_PINS(i2c0, 0, 1); +VISCONTI_PINS(i2c1, 2, 3); +VISCONTI_PINS(i2c2, 12, 13); +VISCONTI_PINS(i2c3, 14, 15); +VISCONTI_PINS(i2c4, 16, 17); +VISCONTI_PINS(i2c5, 18, 19); +VISCONTI_PINS(i2c6, 33, 34); +VISCONTI_PINS(i2c7, 29, 32); +VISCONTI_PINS(i2c8, 30, 31); +VISCONTI_PINS(spi0_cs0, 29); +VISCONTI_PINS(spi0_cs1, 30); +VISCONTI_PINS(spi0_cs2, 31); +VISCONTI_PINS(spi1_cs, 3); +VISCONTI_PINS(spi2_cs, 7); +VISCONTI_PINS(spi3_cs, 11); +VISCONTI_PINS(spi4_cs, 15); +VISCONTI_PINS(spi5_cs, 19); +VISCONTI_PINS(spi6_cs, 27); +VISCONTI_PINS(spi0, 32, 33, 34); +VISCONTI_PINS(spi1, 0, 1, 2); +VISCONTI_PINS(spi2, 4, 5, 6); +VISCONTI_PINS(spi3, 8, 9, 10); +VISCONTI_PINS(spi4, 12, 13, 14); +VISCONTI_PINS(spi5, 16, 17, 18); +VISCONTI_PINS(spi6, 24, 25, 26); +VISCONTI_PINS(uart0, 4, 5, 6, 7); +VISCONTI_PINS(uart1, 8, 9, 10, 11); +VISCONTI_PINS(uart2, 12, 13, 14, 15); +VISCONTI_PINS(uart3, 16, 17, 18, 19); +VISCONTI_PINS(pwm0_gpio4, 4); +VISCONTI_PINS(pwm1_gpio5, 5); +VISCONTI_PINS(pwm2_gpio6, 6); +VISCONTI_PINS(pwm3_gpio7, 7); +VISCONTI_PINS(pwm0_gpio8, 8); +VISCONTI_PINS(pwm1_gpio9, 9); +VISCONTI_PINS(pwm2_gpio10, 10); +VISCONTI_PINS(pwm3_gpio11, 11); +VISCONTI_PINS(pwm0_gpio12, 12); +VISCONTI_PINS(pwm1_gpio13, 13); +VISCONTI_PINS(pwm2_gpio14, 14); +VISCONTI_PINS(pwm3_gpio15, 15); +VISCONTI_PINS(pwm0_gpio16, 16); +VISCONTI_PINS(pwm1_gpio17, 17); +VISCONTI_PINS(pwm2_gpio18, 18); +VISCONTI_PINS(pwm3_gpio19, 19); +VISCONTI_PINS(pcmif_out, 20, 21, 22); +VISCONTI_PINS(pcmif_in, 24, 25, 26); + +static const struct visconti_pin_group groups_tmpv7700[] = { + VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022), + VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200), + VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000), + VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000), + VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077), + VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700), + VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002), + VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000), + VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000), + VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000), + VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000), + VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001), + VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222), +}; + +/* MUX */ +VISCONTI_GROUPS(i2c0, "i2c0_grp"); +VISCONTI_GROUPS(i2c1, "i2c1_grp"); +VISCONTI_GROUPS(i2c2, "i2c2_grp"); +VISCONTI_GROUPS(i2c3, "i2c3_grp"); +VISCONTI_GROUPS(i2c4, "i2c4_grp"); +VISCONTI_GROUPS(i2c5, "i2c5_grp"); +VISCONTI_GROUPS(i2c6, "i2c6_grp"); +VISCONTI_GROUPS(i2c7, "i2c7_grp"); +VISCONTI_GROUPS(i2c8, "i2c8_grp"); +VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp", + "spi0_cs1_grp", "spi0_cs2_grp"); +VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp"); +VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp"); +VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp"); +VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp"); +VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp"); +VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp"); +VISCONTI_GROUPS(uart0, "uart0_grp"); +VISCONTI_GROUPS(uart1, "uart1_grp"); +VISCONTI_GROUPS(uart2, "uart2_grp"); +VISCONTI_GROUPS(uart3, "uart3_grp"); +VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp", + "pwm0_gpio12_grp", "pwm0_gpio16_grp", + "pwm1_gpio5_grp", "pwm1_gpio9_grp", + "pwm1_gpio13_grp", "pwm1_gpio17_grp", + "pwm2_gpio6_grp", "pwm2_gpio10_grp", + "pwm2_gpio14_grp", "pwm2_gpio18_grp", + "pwm3_gpio7_grp", "pwm3_gpio11_grp", + "pwm3_gpio15_grp", "pwm3_gpio19_grp"); +VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp"); +VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp"); + +static const struct visconti_pin_function functions_tmpv7700[] = { + VISCONTI_PIN_FUNCTION(i2c0), + VISCONTI_PIN_FUNCTION(i2c1), + VISCONTI_PIN_FUNCTION(i2c2), + VISCONTI_PIN_FUNCTION(i2c3), + VISCONTI_PIN_FUNCTION(i2c4), + VISCONTI_PIN_FUNCTION(i2c5), + VISCONTI_PIN_FUNCTION(i2c6), + VISCONTI_PIN_FUNCTION(i2c7), + VISCONTI_PIN_FUNCTION(i2c8), + VISCONTI_PIN_FUNCTION(spi0), + VISCONTI_PIN_FUNCTION(spi1), + VISCONTI_PIN_FUNCTION(spi2), + VISCONTI_PIN_FUNCTION(spi3), + VISCONTI_PIN_FUNCTION(spi4), + VISCONTI_PIN_FUNCTION(spi5), + VISCONTI_PIN_FUNCTION(spi6), + VISCONTI_PIN_FUNCTION(uart0), + VISCONTI_PIN_FUNCTION(uart1), + VISCONTI_PIN_FUNCTION(uart2), + VISCONTI_PIN_FUNCTION(uart3), + VISCONTI_PIN_FUNCTION(pwm), + VISCONTI_PIN_FUNCTION(pcmif_in), + VISCONTI_PIN_FUNCTION(pcmif_out), +}; + +/* GPIO MUX */ +#define tmpv7700_GPIO_MUX(off, msk) \ +{ \ + .offset = off, \ + .mask = msk, \ + .val = 0, \ +} + +static const struct visconti_mux gpio_mux_tmpv7700[] = { + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)), +}; + +static void tmpv7700_pinctrl_unlock(void __iomem *base) +{ + writel(1, base + REG_KEY_CTRL); + writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD); +} + +/* chip dependent data */ +static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = { + .pins = pins_tmpv7700, + .nr_pins = ARRAY_SIZE(pins_tmpv7700), + .groups = groups_tmpv7700, + .nr_groups = ARRAY_SIZE(groups_tmpv7700), + .functions = functions_tmpv7700, + .nr_functions = ARRAY_SIZE(functions_tmpv7700), + .gpio_mux = gpio_mux_tmpv7700, + .unlock = tmpv7700_pinctrl_unlock, +}; + +static int tmpv7700_pinctrl_probe(struct platform_device *pdev) +{ + return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data); +} + +static const struct of_device_id tmpv7700_pctrl_of_match[] = { + { .compatible = "toshiba,tmpv7708-pinctrl", }, + {}, +}; + +static struct platform_driver tmpv7700_pinctrl_driver = { + .probe = tmpv7700_pinctrl_probe, + .driver = { + .name = "tmpv7700-pinctrl", + .of_match_table = tmpv7700_pctrl_of_match, + }, +}; + +static int __init tmpv7700_pinctrl_init(void) +{ + return platform_driver_register(&tmpv7700_pinctrl_driver); +} +arch_initcall(tmpv7700_pinctrl_init); -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 2/8] pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 4/8] dt-bindings: arm: toshiba: Add the TMPV7708 RM main board Nobuhiro Iwamatsu ` (4 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add device tree bindings for the Toshiba Visconti ARM SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- .../devicetree/bindings/arm/toshiba.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/toshiba.yaml diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml new file mode 100644 index 000000000000..efd3f4859669 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/toshiba.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti Platform Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Visconti5 TMPV7708 + items: + - const: toshiba,tmpv7708 +... -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/8] dt-bindings: arm: toshiba: Add the TMPV7708 RM main board 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu ` (2 preceding siblings ...) 2020-08-17 1:46 ` [PATCH 3/8] dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 5/8] arm64: visconti: Add initial support for Toshiba Visconti platform Nobuhiro Iwamatsu ` (3 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add an entry for the Toshiba Visconti TMPV7708 RM main board (tmpv7708-rm-mbrc) to the board/SoC bindings. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- Documentation/devicetree/bindings/arm/toshiba.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml index efd3f4859669..0e066290238e 100644 --- a/Documentation/devicetree/bindings/arm/toshiba.yaml +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -16,5 +16,7 @@ properties: oneOf: - description: Visconti5 TMPV7708 items: + - enum: + - toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board - const: toshiba,tmpv7708 ... -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] arm64: visconti: Add initial support for Toshiba Visconti platform 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu ` (3 preceding siblings ...) 2020-08-17 1:46 ` [PATCH 4/8] dt-bindings: arm: toshiba: Add the TMPV7708 RM main board Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Nobuhiro Iwamatsu ` (2 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add the initial device tree files for Toshiba Visconti platform. For starters, the only SoC supported will be Visconti5 TMPV7708. https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- arch/arm64/Kconfig.platforms | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c..a9181e074e9e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -280,6 +280,13 @@ config ARCH_VEXPRESS This enables support for the ARMv8 software model (Versatile Express). +config ARCH_VISCONTI + bool "Toshiba Visconti SoC Family" + select PINCTRL + select PINCTRL_VISCONTI + help + This enables support for Toshiba Visconti SoCs Family. + config ARCH_VULCAN def_bool n -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu ` (4 preceding siblings ...) 2020-08-17 1:46 ` [PATCH 5/8] arm64: visconti: Add initial support for Toshiba Visconti platform Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 8:23 ` Sudeep Holla 2020-08-17 9:00 ` Marc Zyngier 2020-08-17 1:46 ` [PATCH 7/8] MAINTAINERS: Add information for Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 8/8] arm64: defconfig: Enable configs for Toshiba Visconti Nobuhiro Iwamatsu 7 siblings, 2 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add basic support for the Visconti TMPV7708 SoC peripherals - - CPU - CA53 x 4 and 2 cluster. - not support PSCI, currently only spin-table is supported. - Interrupt controller (ARM Generic Interrupt Controller) - Timer (ARM architected timer) - UART (ARM PL011 UART controller) - SPI (ARM PL022 SPI controller) - I2C (Synopsys DesignWare APB I2C Controller) - Pin control (Visconti specific) Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/toshiba/Makefile | 2 + .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 44 ++ arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++ .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++ 5 files changed, 530 insertions(+) create mode 100644 arch/arm64/boot/dts/toshiba/Makefile create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d..c58bdab675ea 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -26,5 +26,6 @@ subdir-y += socionext subdir-y += sprd subdir-y += synaptics subdir-y += ti +subdir-y += toshiba subdir-y += xilinx subdir-y += zte diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile new file mode 100644 index 000000000000..8cd460d5b68e --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts new file mode 100644 index 000000000000..a883d3ab1858 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for TMPV7708 RM main board + * + * (C) Copyright 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + */ + +/dts-v1/; + +#include "tmpv7708.dtsi" + +/ { + model = "Toshiba TMPV7708 RM main board"; + compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon=pl011,0x28200000"; + stdout-path = "serial0:115200n8"; + }; + + /* 768MB memory */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + }; +}; + +&uart0 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi new file mode 100644 index 000000000000..f78ebb707aa4 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the TMPV7708 + * + * (C) Copyright 2018 - 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + * + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ + +/ { + compatible = "toshiba,tmpv7708"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x00>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x01>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x02>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x03>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x103>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + always-on; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@24001000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x24001000 0 0x1000>, + <0 0x24002000 0 0x2000>, + <0 0x24004000 0 0x2000>, + <0 0x24006000 0 0x2000>; + }; + + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + }; + + uart0: serial@28200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28200000 0 0x1000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart_0>; + status = "disabled"; + }; + + uart1: serial@28201000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28201000 0 0x1000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart_1>; + status = "disabled"; + }; + + uart2: serial@28202000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28202000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart_2>; + status = "disabled"; + }; + + uart3: serial@28203000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28203000 0 0x1000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart_3>; + status = "disabled"; + }; + + i2c0: i2c@28030000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28030000 0 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@28031000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28031000 0 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@28032000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28032000 0 0x1000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_2>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@28033000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28033000 0 0x1000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_3>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@28034000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28034000 0 0x1000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@28035000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28035000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_5>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@28036000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28036000 0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_6>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@28037000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28037000 0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_7>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@28038000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28038000 0 0x1000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_8>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@28140000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28140000 0 0x1000>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_0>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@28141000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28141000 0 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_1>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@28142000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28142000 0 0x1000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_2>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@28143000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28143000 0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_3>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@28144000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28144000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_4>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@28145000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28145000 0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_5>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@28146000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28146000 0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_6>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; + +#include "tmpv7708_pins.dtsi" diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi new file mode 100644 index 000000000000..fb630f51cfe2 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pmux { + spi_0: spi_0 { + function = "spi0"; + groups = "spi0_grp"; + }; + spi_1: spi_1 { + function = "spi1"; + groups = "spi1_grp"; + }; + spi_2: spi_2 { + function = "spi2"; + groups = "spi2_grp"; + }; + spi_3: spi_3 { + function = "spi3"; + groups = "spi3_grp"; + }; + spi_4: spi_4 { + function = "spi4"; + groups = "spi4_grp"; + }; + spi_5: spi_5 { + function = "spi5"; + groups = "spi5_grp"; + }; + spi_6: spi_6 { + function = "spi6"; + groups = "spi6_grp"; + }; + uart_0: uart_0 { + function = "uart0"; + groups = "uart0_grp"; + }; + uart_1: uart_1 { + function = "uart1"; + groups = "uart1_grp"; + }; + uart_2: uart_2 { + function = "uart2"; + groups = "uart2_grp"; + }; + uart_3: uart_3 { + function = "uart3"; + groups = "uart3_grp"; + }; + i2c_0: i2c_0 { + function = "i2c0"; + groups = "i2c0_grp"; + bias-pull-up; + }; + i2c_1: i2c_1 { + function = "i2c1"; + groups = "i2c1_grp"; + bias-pull-up; + }; + i2c_2: i2c_2 { + function = "i2c2"; + groups = "i2c2_grp"; + bias-pull-up; + }; + i2c_3: i2c_3 { + function = "i2c3"; + groups = "i2c3_grp"; + bias-pull-up; + }; + i2c_4: i2c_4 { + function = "i2c4"; + groups = "i2c4_grp"; + bias-pull-up; + }; + i2c_5: i2c_5 { + function = "i2c5"; + groups = "i2c5_grp"; + bias-pull-up; + }; + i2c_6: i2c_6 { + function = "i2c6"; + groups = "i2c6_grp"; + bias-pull-up; + }; + i2c_7: i2c_7 { + function = "i2c7"; + groups = "i2c7_grp"; + bias-pull-up; + }; + i2c_8: i2c_8 { + function = "i2c8"; + groups = "i2c8_grp"; + bias-pull-up; + }; +}; -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board 2020-08-17 1:46 ` [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Nobuhiro Iwamatsu @ 2020-08-17 8:23 ` Sudeep Holla 2020-08-19 4:58 ` Nobuhiro Iwamatsu 2020-08-17 9:00 ` Marc Zyngier 1 sibling, 1 reply; 17+ messages in thread From: Sudeep Holla @ 2020-08-17 8:23 UTC (permalink / raw) To: Nobuhiro Iwamatsu Cc: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon, devicetree, punit1.agrawal, linux-gpio, yuji2.ishikawa, linux-arm-kernel, Sudeep Holla On Mon, Aug 17, 2020 at 10:46:30AM +0900, Nobuhiro Iwamatsu wrote: > Add basic support for the Visconti TMPV7708 SoC peripherals - > - CPU > - CA53 x 4 and 2 cluster. > - not support PSCI, currently only spin-table is supported. Do you have plans to support PSCI in future ? It is now almost more than 5 year old specification. So they should be strong reason for not supporting that. [..] > diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile > new file mode 100644 > index 000000000000..8cd460d5b68e > --- /dev/null > +++ b/arch/arm64/boot/dts/toshiba/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > new file mode 100644 > index 000000000000..a883d3ab1858 > --- /dev/null > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > @@ -0,0 +1,44 @@ [..] > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + always-on; Will this be true when CPU is in low power modes ? -- Regards, Sudeep ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board 2020-08-17 8:23 ` Sudeep Holla @ 2020-08-19 4:58 ` Nobuhiro Iwamatsu 0 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-19 4:58 UTC (permalink / raw) To: Sudeep Holla Cc: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon, devicetree, punit1.agrawal, linux-gpio, yuji2.ishikawa, linux-arm-kernel Hi, Thanks for your review. On Mon, Aug 17, 2020 at 09:23:25AM +0100, Sudeep Holla wrote: > On Mon, Aug 17, 2020 at 10:46:30AM +0900, Nobuhiro Iwamatsu wrote: > > Add basic support for the Visconti TMPV7708 SoC peripherals - > > - CPU > > - CA53 x 4 and 2 cluster. > > - not support PSCI, currently only spin-table is supported. > > Do you have plans to support PSCI in future ? > It is now almost more than 5 year old specification. So they should be > strong reason for not supporting that. I understand that the problem exists and I am considering with our firmware development team. Currently spin-table is set, but if the firmware supports it, I plan to switch to PSCI. If the firmware doesn't support PSCI now, would it be difficult to apply the patch? > > > [..] > > > diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile > > new file mode 100644 > > index 000000000000..8cd460d5b68e > > --- /dev/null > > +++ b/arch/arm64/boot/dts/toshiba/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb > > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > new file mode 100644 > > index 000000000000..a883d3ab1858 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > @@ -0,0 +1,44 @@ > > [..] > > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupt-parent = <&gic>; > > + always-on; > > Will this be true when CPU is in low power modes ? > Although it is related to the above PSCI, Visconti5 does not have a low power mode etc., so it is set like this. > -- > Regards, > Sudeep > Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board 2020-08-17 1:46 ` [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Nobuhiro Iwamatsu 2020-08-17 8:23 ` Sudeep Holla @ 2020-08-17 9:00 ` Marc Zyngier 2020-08-19 5:32 ` Nobuhiro Iwamatsu 1 sibling, 1 reply; 17+ messages in thread From: Marc Zyngier @ 2020-08-17 9:00 UTC (permalink / raw) To: Nobuhiro Iwamatsu Cc: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon, devicetree, punit1.agrawal, linux-gpio, yuji2.ishikawa, linux-arm-kernel On 2020-08-17 02:46, Nobuhiro Iwamatsu wrote: > Add basic support for the Visconti TMPV7708 SoC peripherals - > - CPU > - CA53 x 4 and 2 cluster. > - not support PSCI, currently only spin-table is supported. We have pushed back on other SoCs in the past when they didn't implement PSCI. There really is not good reason not to have even the most trivial PSCI implementation these days. > - Interrupt controller (ARM Generic Interrupt Controller) > - Timer (ARM architected timer) > - UART (ARM PL011 UART controller) > - SPI (ARM PL022 SPI controller) > - I2C (Synopsys DesignWare APB I2C Controller) > - Pin control (Visconti specific) > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/toshiba/Makefile | 2 + > .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 44 ++ > arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++ > .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++ > 5 files changed, 530 insertions(+) > create mode 100644 arch/arm64/boot/dts/toshiba/Makefile > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi > [...] > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > new file mode 100644 > index 000000000000..a883d3ab1858 > --- /dev/null > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree File for TMPV7708 RM main board > + * > + * (C) Copyright 2020, Toshiba Corporation. > + * (C) Copyright 2020, Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp> > + */ > + > +/dts-v1/; > + > +#include "tmpv7708.dtsi" > + > +/ { > + model = "Toshiba TMPV7708 RM main board"; > + compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + bootargs = "earlycon=pl011,0x28200000"; > + stdout-path = "serial0:115200n8"; These should be provided by the bootloader, and not hardcoded. > + }; > + > + /* 768MB memory */ > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x30000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > + clocks = <&uart_clk>; > + clock-names = "apb_pclk"; > +}; > + > +&uart1 { > + status = "okay"; > + clocks = <&uart_clk>; > + clock-names = "apb_pclk"; > +}; > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi > b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi > new file mode 100644 > index 000000000000..f78ebb707aa4 > --- /dev/null > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi > @@ -0,0 +1,390 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree Source for the TMPV7708 > + * > + * (C) Copyright 2018 - 2020, Toshiba Corporation. > + * (C) Copyright 2020, Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp> > + * > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ > + > +/ { > + compatible = "toshiba,tmpv7708"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x00>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x01>; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x02>; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x03>; > + }; > + > + cpu4: cpu@100 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x100>; > + }; > + > + cpu5: cpu@101 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x101>; > + }; > + > + cpu6: cpu@102 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x102>; > + }; > + > + cpu7: cpu@103 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x81100000>; > + reg = <0x103>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + always-on; That's unlikely to be true. A53 does have low-power modes that will kill the comparator, and you will miss timer deadlines. This property really only applies to virtual machines, which isn't the case here. > + interrupts = > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + uart_clk: uart-clk { > + compatible = "fixed-clock"; > + clock-frequency = <150000000>; > + #clock-cells = <0>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + gic: interrupt-controller@24001000 { > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0 0x24001000 0 0x1000>, > + <0 0x24002000 0 0x2000>, > + <0 0x24004000 0 0x2000>, > + <0 0x24006000 0 0x2000>; You are missing the maintenance interrupt. Thanks, M. -- Who you jivin' with that Cosmik Debris? ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board 2020-08-17 9:00 ` Marc Zyngier @ 2020-08-19 5:32 ` Nobuhiro Iwamatsu 0 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-19 5:32 UTC (permalink / raw) To: Marc Zyngier Cc: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon, devicetree, punit1.agrawal, linux-gpio, yuji2.ishikawa, linux-arm-kernel Hi, Thanks for your review. On Mon, Aug 17, 2020 at 10:00:45AM +0100, Marc Zyngier wrote: > On 2020-08-17 02:46, Nobuhiro Iwamatsu wrote: > > Add basic support for the Visconti TMPV7708 SoC peripherals - > > - CPU > > - CA53 x 4 and 2 cluster. > > - not support PSCI, currently only spin-table is supported. > > We have pushed back on other SoCs in the past when they didn't > implement PSCI. There really is not good reason not to have > even the most trivial PSCI implementation these days. As I've responded to Sudeep Holla, I already understood about this issue, so I am considering into PSCI support with firmware team. > > > - Interrupt controller (ARM Generic Interrupt Controller) > > - Timer (ARM architected timer) > > - UART (ARM PL011 UART controller) > > - SPI (ARM PL022 SPI controller) > > - I2C (Synopsys DesignWare APB I2C Controller) > > - Pin control (Visconti specific) > > > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > --- > > arch/arm64/boot/dts/Makefile | 1 + > > arch/arm64/boot/dts/toshiba/Makefile | 2 + > > .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 44 ++ > > arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++ > > .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++ > > 5 files changed, 530 insertions(+) > > create mode 100644 arch/arm64/boot/dts/toshiba/Makefile > > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi > > create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi > > > > [...] > > > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > new file mode 100644 > > index 000000000000..a883d3ab1858 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts > > @@ -0,0 +1,44 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Device Tree File for TMPV7708 RM main board > > + * > > + * (C) Copyright 2020, Toshiba Corporation. > > + * (C) Copyright 2020, Nobuhiro Iwamatsu > > <nobuhiro1.iwamatsu@toshiba.co.jp> > > + */ > > + > > +/dts-v1/; > > + > > +#include "tmpv7708.dtsi" > > + > > +/ { > > + model = "Toshiba TMPV7708 RM main board"; > > + compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + }; > > + > > + chosen { > > + bootargs = "earlycon=pl011,0x28200000"; > > + stdout-path = "serial0:115200n8"; > > These should be provided by the bootloader, and not hardcoded. > OK, I will remove this line. > > + }; > > + > > + /* 768MB memory */ > > + memory@80000000 { > > + device_type = "memory"; > > + reg = <0x0 0x80000000 0x0 0x30000000>; > > + }; > > +}; > > + <snip> > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupt-parent = <&gic>; > > + always-on; > > That's unlikely to be true. A53 does have low-power modes that > will kill the comparator, and you will miss timer deadlines. > This property really only applies to virtual machines, which isn't > the case here. I see. Thank you for the explanation. I remove this parameter. > > > + interrupts = > > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > > + }; > > + > > + uart_clk: uart-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <150000000>; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + compatible = "simple-bus"; > > + interrupt-parent = <&gic>; > > + ranges; > > + > > + gic: interrupt-controller@24001000 { > > + compatible = "arm,gic-400"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + reg = <0 0x24001000 0 0x1000>, > > + <0 0x24002000 0 0x2000>, > > + <0 0x24004000 0 0x2000>, > > + <0 0x24006000 0 0x2000>; > > You are missing the maintenance interrupt. Thanks! I will add interrupts parameter. > > Thanks, > > M. Best regards, Nobuhiro > -- > Who you jivin' with that Cosmik Debris? > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 7/8] MAINTAINERS: Add information for Toshiba Visconti ARM SoCs 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu ` (5 preceding siblings ...) 2020-08-17 1:46 ` [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 8/8] arm64: defconfig: Enable configs for Toshiba Visconti Nobuhiro Iwamatsu 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Add information about Toshiba Visconti ARM SoCs to MAINTAINERS. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e2698cc7e23..6080196045ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2612,6 +2612,17 @@ M: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> M: Dirk Opfer <dirk@opfer-online.de> S: Maintained +ARM/TOSHIBA VISCONTI ARCHITECTURE +M: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git +F: Documentation/devicetree/bindings/arm/toshiba.yaml +F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml +F: arch/arm64/boot/dts/toshiba/ +F: drivers/pinctrl/visconti/ +N: visconti + ARM/UNIPHIER ARCHITECTURE M: Masahiro Yamada <yamada.masahiro@socionext.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] arm64: defconfig: Enable configs for Toshiba Visconti 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu ` (6 preceding siblings ...) 2020-08-17 1:46 ` [PATCH 7/8] MAINTAINERS: Add information for Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu @ 2020-08-17 1:46 ` Nobuhiro Iwamatsu 7 siblings, 0 replies; 17+ messages in thread From: Nobuhiro Iwamatsu @ 2020-08-17 1:46 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Catalin Marinas, Will Deacon Cc: punit1.agrawal, yuji2.ishikawa, devicetree, linux-arm-kernel, linux-gpio, Nobuhiro Iwamatsu Enable support for the Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2ca7ba69c318..7e547812b9d5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -57,6 +57,7 @@ CONFIG_ARCH_THUNDER=y CONFIG_ARCH_THUNDER2=y CONFIG_ARCH_UNIPHIER=y CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VISCONTI=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZX=y CONFIG_ARCH_ZYNQMP=y -- 2.27.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-08-19 5:36 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-17 1:46 [PATCH 0/8] Add Toshiba Visconti ARM64 Platform support Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Nobuhiro Iwamatsu 2020-08-17 19:46 ` Rob Herring 2020-08-19 5:33 ` Nobuhiro Iwamatsu 2020-08-17 19:48 ` Rob Herring 2020-08-19 5:35 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 2/8] pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 3/8] dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 4/8] dt-bindings: arm: toshiba: Add the TMPV7708 RM main board Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 5/8] arm64: visconti: Add initial support for Toshiba Visconti platform Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board Nobuhiro Iwamatsu 2020-08-17 8:23 ` Sudeep Holla 2020-08-19 4:58 ` Nobuhiro Iwamatsu 2020-08-17 9:00 ` Marc Zyngier 2020-08-19 5:32 ` Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 7/8] MAINTAINERS: Add information for Toshiba Visconti ARM SoCs Nobuhiro Iwamatsu 2020-08-17 1:46 ` [PATCH 8/8] arm64: defconfig: Enable configs for Toshiba Visconti Nobuhiro Iwamatsu
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