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From: Boris Brezillon <boris.brezillon@collabora.com>
To: Vitor Soares <vitor.soares@synopsys.com>
Cc: Przemyslaw Gaj <pgaj@cadence.com>,
	"bbrezillon@kernel.org" <bbrezillon@kernel.org>,
	"linux-i3c@lists.infradead.org" <linux-i3c@lists.infradead.org>,
	"rafalc@cadence.com" <rafalc@cadence.com>,
	"agolec@cadence.com" <agolec@cadence.com>
Subject: Re: [PATCH v4 3/6] i3c: Add support for mastership request to I3C subsystem
Date: Mon, 15 Apr 2019 15:08:26 +0200
Message-ID: <20190415150826.168fa0c3@collabora.com> (raw)
In-Reply-To: <13D59CF9CEBAF94592A12E8AE55501350A614688@DE02WEMBXB.internal.synopsys.com>

Hi Vitor,

On Mon, 15 Apr 2019 12:02:02 +0000
Vitor Soares <vitor.soares@synopsys.com> wrote:

> From: Boris Brezillon <boris.brezillon@collabora.com>
> Date: Fri, Apr 12, 
> 2019 at 15:57:19
> 
> > On Fri, 12 Apr 2019 14:28:26 +0000
> > Vitor Soares <vitor.soares@synopsys.com> wrote:
> >   
> > > > > What if the slave is a secondary master? In your opinion what should be 
> > > > > the flow?    
> > > > 
> > > > i3c_slave_regiter(&ctrl->slave);
> > > > i3c_master_regiter(&ctrl->master);
> > > > 
> > > > The order is arbitrary, and those might actually be called from
> > > > different path if it makes more sense. I'm just pointing out that
> > > > registering a slave and registering a master are 2 different things,
> > > > and the master side of the framework should probably not automate slave
> > > > registration, at least not until we have a better idea of what the
> > > > slave API will look like.    
> > > 
> > > We need to understand better your point.
> > > 
> > > The secondary master can have both roles and even not implementing all 
> > > slave function it is a slave when is not a master.
> > > For me still keep the idea:
> > > 
> > >         bus
> > >          / \
> > >        /     \
> > > slave    master
> > > 
> > > and just one role is active at time.
> > > 
> > > I didn't get why the bus shouldn't be instantiated for slave. Can you 
> > > explain?  
> > 
> > Because, from a SW PoV, pure slave devices don't care about the bus
> > concept. Do you have use cases where you'd need to know what bus the
> > slave is connected to?
> >   
> 
> In device model I expect that the slave is under a bus.

Attached to a bus_type, maybe, under an I3C bus object, I'm not
convinced.

> You may not need 
> to know the bus topologies and the devices connect but at least we might 
> need to know the bus is alive.

Yes, AFAICT, the slave status (and potentially the I3C dynamic address)
are the only thing an I3C slave controller driver might need.

> 
> The I2C subsystem implement that and it is working.

But is it needed? That's what I'm questioning here. What would you put
in the bus object if the only thing you know about it is that the slave
controller is present on the bus. Does it make sense to re-use the same
logic/struct for the slave case?
Maybe my feeling about this problem is wrong, but as usual, I don't see
a real use case expressed or a PoC that shows me why you'd need to have
an i3c_bus attached to the slave. So it's hard to say who's right/wrong.
If you come up with an RFC for the slave API we'll have something
concrete to discuss about. Until this happens, I'd like to close this
topic. And of course, I'd appreciate that we keep focusing on the
mastership handover/secondary master case without thinking too much
about how things will be impacted by the slave API.

> 
> I still don't understand your position, is there any other reasons?

My position is: I don't see the point of adding complex concepts to
something that's otherwise way simpler than managing an I3C bus. You can
prove me wrong with a detailed example, or even better, a patch series
adding the slave API plus a reference driver to show how it's supposed
to work :P.

> 
> > AFAICT, all you can do is reply to master requests (probably with some
> > predefined messages, like values stored in a regmap or data queued in
> > a FIFO).  
> 
> We can list it:
>   - RX/TX SDR data
>   - RX/TX HDR data
>   - SIR
>   - HJ
>   - MR (case of sec master)

Yes, but that case falls in the I3C master API.

>   - CCC 
>   - and perhaps timing control.
> 
> >   
> > > 
> > > In any case we will need a common point to switch the roles.  
> > 
> > We'd need a way to relinquish bus ownership, that's all. When the
> > master is not the current master, it automatically becomes a slave, and
> > if it has any "I3C slave" profile registered, it can reply to requests
> > coming from the current master.  
> 
> This is too abstract to me. Can you point a current example? Because for 
> me we need a common layer for both master slave structures.

We need to share a few things (CCC defs and probably other things,
but I don't know which ones yet), yes, but I don't think the i3c_bus
struct is one of them.

I also don't know what the slave API will look like, and that's
actually something someone (you??) should work on before having
advanced discussions about what has to be shared between the
master/slave layers.

> 
> >   
> > > > > > > > > In this way you are able to add DEFSLVS even before the HC has enable MR       
> > > > > > > > events like it is done      
> > > > > > > > > with dt devices.      
> > > > > > > > 
> > > > > > > > I don't get it. What do you mean "add DEFSLVS"? DEFSLVS should be received 
> > > > > > > > from
> > > > > > > > current master right after ENTDAA. Could you please explain?      
> > > > > > > 
> > > > > > > So the current master receive an hot join and send the DEFSLVS, when do you
> > > > > > > add them to the bus? Will you go for the all process to get all dev info and so on?
> > > > > > >       
> > > > > > 
> > > > > > When current master receives an hot-join, do ENTDAA to enumerate device which
> > > > > > joined the bus and then sends DEFSLVS. This data is stored in secondary master
> > > > > > controller and if secondary master can request mastership, collects all
> > > > > > required informations and adds the devices. It has to collect PID, DEFSLVS does
> > > > > > not provide this information.      
> > > > > 
> > > > > I see now. You need to take care here because when the secondary master 
> > > > > add the i3c_dev it might change the address.
> > > > > This is one of the reasons I would prefer a dedicated function to add the 
> > > > > DEFSLVS.    
> > > > 
> > > > IIRC, Cadence IP is parsing DEFSLVS in HW, and the device table is
> > > > automatically filled based on that. We should only add the DEFSLVS
> > > > parsing helper once we start seeing a need for it (probably when adding
> > > > secondary slave support since you seem to insist on this aspect :-)).    
> > > 
> > > For me the subsystem should hold and handle all this information. Anyway, 
> > > this information is received and needed before the mastership takeover.  
> > 
> > It is, and we already have a bunch of helpers to add new devices. Maybe
> > we need a few more, I'm just saying that forging a DEFSLVS frame to then
> > pass it to the core is not the right solution IMO. 
> > If you need an helper
> > that automatically parses a DEFSLVS frame and add the new devices, then
> > fine, add this helper to the framework and use it in your driver, but
> > don't force other drivers to use this method.  
> 
> This is not based in a need. I can also add the devices one by one.
> If I have everything available why not send it straight away to the 
> subsystem and let it do the management?

This is exactly what I recommend you to do: provide an helper that will
automate that, but don't force other drivers to use this helper. Since
the Cadence driver will not use this helper, it should not be
introduced in this patch series, that's all I said.

> But ok, I understand your point and I can do the helper to parse the 
> DEFSLVS.
> 
> Another question:
>   How do we know what is the main master in case we want to send back the 
> bus mastership?

There's a ->cur_master field in struct i3c_bus. It should be updated
when the bus owner changes. Not sure exactly how other masters can be
informed about that, but those doing the handshake know about the
change, that's for sure.

> 
> >   
> > > Basically I want to avoid to put this type of logistics in HC driver 
> > > layer and call the maintenance_lock.  
> > 
> > And yet, I don't think forging a DEFSLVS frame is the right way to
> > provide the kind of abstraction you're talking about.   
> 
> Can you explain?

I keep explaining you that reconstructing a fake DEFSLVS frame just for
the sake of having all drivers use the helper you want to add is not a
good idea.

To sum-up one last time: adding the
i3c_master_parse_defslvs_and_add_devs() helper is fine, forcing all
drivers to use it is not. Is that clear enough?

> 
> > Note that I said
> > a few things should be provided as helpers in my review.
> >   
> > > 
> > > I'm insisting because it seems that I have a different use case to 
> > > address and I don't see how this fit on it.  
> > 
> > Can you be more specific, because we don't know about your use cases.  
> 
> According to the spec the sec master may have all function of a Main 
> master and may have all function of a slave.

So you're back to the master/slave dual role thing?

> 
> The implementation should made with this in mind and I'm asking 
> flexibility for that. 

What you're asking for is the opposite of flexibility, and most
importantly it's based on assumptions about something that has not been
fully designed yet: the I3C slave API.

So let's have a plan for this discussion to actually lead to something
useful:

1/ propose an RFC for the slave API + a reference driver
2/ think about how dual role devs can implement both interfaces and the
things they need to share

See, we keep discussing #2 while #1 is not even ready yet, and it's
definitely a pre-requisite to #2. So please work #1 first.

Regards,

Boris

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  reply index

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-10 13:58 [PATCH v4 0/6] Add the I3C mastership request Przemyslaw Gaj
2019-03-10 13:58 ` [PATCH v4 1/6] i3c: add addr and lvr to i2c_dev_desc structure Przemyslaw Gaj
2019-03-30 14:36   ` Boris Brezillon
2019-04-01 18:17     ` vitor
2019-04-01 18:31       ` Boris Brezillon
2019-04-01 18:48         ` vitor
2019-04-01 19:10           ` Przemyslaw Gaj
2019-04-01 19:24           ` Boris Brezillon
2019-04-02 11:10             ` vitor
2019-04-02 11:22               ` Przemyslaw Gaj
2019-04-02 11:32                 ` vitor
2019-04-02 11:53                   ` Boris Brezillon
2019-04-02 11:48     ` Boris Brezillon
2019-03-10 13:58 ` [PATCH v4 2/6] i3c: export bus maintenance lock and unlock functions Przemyslaw Gaj
2019-03-10 13:58 ` [PATCH v4 3/6] i3c: Add support for mastership request to I3C subsystem Przemyslaw Gaj
2019-03-30 15:06   ` Boris Brezillon
2019-04-01 18:41   ` vitor
2019-04-01 19:18     ` Boris Brezillon
2019-04-09 14:31     ` Vitor Soares
2019-04-09 15:20       ` Przemyslaw Gaj
2019-04-09 15:46         ` Vitor Soares
2019-04-10  6:53           ` Przemyslaw Gaj
2019-04-10 10:05             ` Vitor Soares
2019-04-10 10:36               ` Boris Brezillon
2019-04-12 14:28                 ` Vitor Soares
2019-04-12 14:57                   ` Boris Brezillon
2019-04-15 12:02                     ` Vitor Soares
2019-04-15 13:08                       ` Boris Brezillon [this message]
2019-03-10 13:58 ` [PATCH v4 4/6] i3c: master: cdns: add support for mastership request to Cadence I3C master driver Przemyslaw Gaj
2019-03-30 15:44   ` Boris Brezillon
2019-04-29 10:36     ` Przemyslaw Gaj
2019-05-18  7:34       ` Boris Brezillon
2019-03-10 13:58 ` [PATCH v4 5/6] i3c: master: Add module author Przemyslaw Gaj
2019-03-10 13:58 ` [PATCH v4 6/6] MAINTAINERS: add myself as co-maintainer of i3c subsystem Przemyslaw Gaj

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