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From: Boris Brezillon <boris.brezillon@collabora.com>
To: Vitor Soares <Vitor.Soares@synopsys.com>
Cc: Przemyslaw Gaj <pgaj@cadence.com>,
	"linux-i3c@lists.infradead.org" <linux-i3c@lists.infradead.org>,
	"bbrezillon@kernel.org" <bbrezillon@kernel.org>
Subject: Re: I3C Mastership RFC
Date: Mon, 25 Nov 2019 15:50:25 +0100
Message-ID: <20191125155025.33b76933@collabora.com> (raw)
In-Reply-To: <CH2PR12MB4216F1775A4F133EF845EC01AE4A0@CH2PR12MB4216.namprd12.prod.outlook.com>

On Mon, 25 Nov 2019 14:27:18 +0000
Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> From: Boris Brezillon <boris.brezillon@collabora.com>
> Date: Mon, Nov 25, 2019 at 13:09:36
> 
> > On Mon, 25 Nov 2019 13:00:17 +0000
> > Vitor Soares <Vitor.Soares@synopsys.com> wrote:
> >   
> > > > > > > > I'm pretty sure we solved that already (that's what
> > > > > > > > i3c_master_acquire_bus_ownership() calls are supposed to take care of).
> > > > > > > > Can you be a bit more specific? What makes you think the master might
> > > > > > > > not be in control of the bus when i3c_dev_do_priv_xfers_locked() is
> > > > > > > > called?      
> > > > > > > 
> > > > > > > You are assuming that after i3c_master_acquire_bus_ownership() return, 
> > > > > > > secondary master already owns the bus. Main master can ack the MR request 
> > > > > > > and not send the CETACCMST immediately.
> > > > > > >      
> > > > > > 
> > > > > > In Cadence HC driver, I'm waiting for GETACCMST longer, polling the
> > > > > > status and after I exit from ->request_mastership(), I'm the bus owner.
> > > > > > If not, error exit code is returned and we can't make the transfers.
> > > > > > Are you able to implement the same behavior?      
> > > > > 
> > > > > You can assume everyone will do in that way. What happen if you receive a 
> > > > > request or an information from current master?    
> > > > 
> > > > We have this ->request_mastership() method so controllers that have
> > > > this logic (MR+wait(GETACCMST) automated can still interface with the
> > > > subsystem.     
> > > 
> > > I can also poll the GETACCMST but we are assuming nothing will happen 
> > > between MR and GETACCMST.  
> > 
> > Nothing coming from the master that tries to acquire the bus, yes.
> > Nothing coming from the current master, no, and that shouldn't be a
> > problem as long as those operations don't involve acquiring bus->lock.
> > And if some of those operation involve acquiring the lock (I'd still
> > need to understand which operation that would be) they'll just be
> > delayed/rejected.  
> 
> You are assuming this is straight forward which is not the case. Between 
> MR and GETACCMST may happen everything as in a Master-Slave topology.

Like what? Be more specific, I want real examples that don't work
because of the way mastership handover is done in Przemek's proposal.

> For me, poll the controller to check when GETACCMST arrive and lock 
> everything is not a solution.

We don't lock everything: other devs can still communicate until we've
acquired the bus, and the slave end of your master should also work
(since the master is still not acting as a master yet).
We do prevent new MR request once we've acquired the bus to avoid
situations where another master requests bus ownership before we could
send the messages we were asked to send (device driver request). But
that's a completely orthogonal thing, and has nothing to do with the
polling solution you seem to complain about.
BTW, you don't have to poll the reg value, using interrupt-based
waiting is fine too. My point is, if we want to keep the code simple,
we have to make this operation synchronous from the caller PoV.

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Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-06  9:33 Przemyslaw Gaj
2019-11-10 10:30 ` Boris Brezillon
2019-11-11 12:30   ` Vitor Soares
2019-11-12  7:41     ` Boris Brezillon
2019-11-14  6:10       ` Przemyslaw Gaj
2019-11-14 11:56         ` Vitor Soares
2019-11-14 12:32           ` Boris Brezillon
2019-11-14 12:59             ` Przemyslaw Gaj
2019-11-14 14:17             ` Vitor Soares
2019-11-14 14:50               ` Boris Brezillon
2019-11-14 20:15                 ` Przemyslaw Gaj
2019-11-25  8:02               ` Przemyslaw Gaj
2019-11-25 11:19                 ` Vitor Soares
2019-11-25 11:34                   ` Boris Brezillon
2019-11-25 11:42                     ` Vitor Soares
2019-11-25 11:55                       ` Przemyslaw Gaj
2019-11-25 12:03                         ` Vitor Soares
2019-11-25 12:22                           ` Boris Brezillon
2019-11-25 13:00                             ` Vitor Soares
2019-11-25 13:09                               ` Boris Brezillon
2019-11-25 14:27                                 ` Vitor Soares
2019-11-25 14:50                                   ` Boris Brezillon [this message]
2019-11-25 14:59                                   ` Przemyslaw Gaj
2019-11-25 15:22                                     ` Vitor Soares
2019-11-25 12:25                           ` Przemyslaw Gaj
2019-11-25 12:56                             ` Vitor Soares
2019-11-25 11:50                     ` Przemyslaw Gaj

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