* [PATCH] getauxval.3: Add new cache geometry entries
@ 2019-09-16 18:41 Raphael Moreira Zinsly
2019-09-23 12:27 ` Michael Kerrisk (man-pages)
2019-09-24 4:27 ` Michael Kerrisk (man-pages)
0 siblings, 2 replies; 8+ messages in thread
From: Raphael Moreira Zinsly @ 2019-09-16 18:41 UTC (permalink / raw)
To: mtk.manpages; +Cc: linux-man, benh, mpe, Raphael Moreira Zinsly
Add entries for the new cache geometry values of the auxiliary vectors
that got included in the kernel.
Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
---
man3/getauxval.3 | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/man3/getauxval.3 b/man3/getauxval.3
index 794bc97b5..30f0757b5 100644
--- a/man3/getauxval.3
+++ b/man3/getauxval.3
@@ -123,6 +123,33 @@ The instruction cache block size.
.\" .TP
.\" .BR AT_NOTELF
.TP
+.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
+.BR AT_L1D_CACHEGEOMETRY
+Geometry of the L1 data cache, that is, line size and number
+of ways.
+.TP
+.BR AT_L1D_CACHESIZE
+The L1 data cache size.
+.TP
+.BR AT_L1I_CACHEGEOMETRY
+Geometry of the L1 instruction cache, that is, line size and
+number of ways.
+.TP
+.BR AT_L1I_CACHESIZE
+The L1 instruction cache size.
+.TP
+.BR AT_L2_CACHEGEOMETRY
+Geometry of the L2 cache, that is, line size and number of ways.
+.TP
+.BR AT_L2_CACHESIZE
+The L2 cache size.
+.TP
+.BR AT_L3_CACHEGEOMETRY
+Geometry of the L3 cache, that is, line size and number of ways.
+.TP
+.BR AT_L3_CACHESIZE
+The L3 cache size.
+.TP
.BR AT_PAGESZ
The system page size (the same value returned by
.IR sysconf(_SC_PAGESIZE) ).
--
2.21.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] getauxval.3: Add new cache geometry entries
2019-09-16 18:41 [PATCH] getauxval.3: Add new cache geometry entries Raphael Moreira Zinsly
@ 2019-09-23 12:27 ` Michael Kerrisk (man-pages)
2019-09-23 13:36 ` Raphael M Zinsly
2019-09-24 4:27 ` Michael Kerrisk (man-pages)
1 sibling, 1 reply; 8+ messages in thread
From: Michael Kerrisk (man-pages) @ 2019-09-23 12:27 UTC (permalink / raw)
To: Raphael Moreira Zinsly; +Cc: mtk.manpages, linux-man, benh, mpe
Hello Raphael,
Thanks for this patch. I have a question below.
On 9/16/19 8:41 PM, Raphael Moreira Zinsly wrote:
> Add entries for the new cache geometry values of the auxiliary vectors
> that got included in the kernel.
>
> Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
> ---
> man3/getauxval.3 | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/man3/getauxval.3 b/man3/getauxval.3
> index 794bc97b5..30f0757b5 100644
> --- a/man3/getauxval.3
> +++ b/man3/getauxval.3
> @@ -123,6 +123,33 @@ The instruction cache block size.
> .\" .TP
> .\" .BR AT_NOTELF
> .TP
> +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
> +.BR AT_L1D_CACHEGEOMETRY
> +Geometry of the L1 data cache, that is, line size and number
> +of ways.
What is "number of ways"?
Thanks,
Michael
> +.TP
> +.BR AT_L1D_CACHESIZE
> +The L1 data cache size.
> +.TP
> +.BR AT_L1I_CACHEGEOMETRY
> +Geometry of the L1 instruction cache, that is, line size and
> +number of ways.
> +.TP
> +.BR AT_L1I_CACHESIZE
> +The L1 instruction cache size.
> +.TP
> +.BR AT_L2_CACHEGEOMETRY
> +Geometry of the L2 cache, that is, line size and number of ways.
> +.TP
> +.BR AT_L2_CACHESIZE
> +The L2 cache size.
> +.TP
> +.BR AT_L3_CACHEGEOMETRY
> +Geometry of the L3 cache, that is, line size and number of ways.
> +.TP
> +.BR AT_L3_CACHESIZE
> +The L3 cache size.
> +.TP
> .BR AT_PAGESZ
> The system page size (the same value returned by
> .IR sysconf(_SC_PAGESIZE) ).
>
--
Michael Kerrisk
Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
Linux/UNIX System Programming Training: http://man7.org/training/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] getauxval.3: Add new cache geometry entries
2019-09-23 12:27 ` Michael Kerrisk (man-pages)
@ 2019-09-23 13:36 ` Raphael M Zinsly
2019-09-24 18:41 ` G. Branden Robinson
0 siblings, 1 reply; 8+ messages in thread
From: Raphael M Zinsly @ 2019-09-23 13:36 UTC (permalink / raw)
To: Michael Kerrisk (man-pages); +Cc: linux-man, benh, mpe
On 23/09/2019 09:27, Michael Kerrisk (man-pages) wrote:
> Hello Raphael,
>
> Thanks for this patch. I have a question below.
>
>
> On 9/16/19 8:41 PM, Raphael Moreira Zinsly wrote:
>> Add entries for the new cache geometry values of the auxiliary vectors
>> that got included in the kernel.
>>
>> Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
>> ---
>> man3/getauxval.3 | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/man3/getauxval.3 b/man3/getauxval.3
>> index 794bc97b5..30f0757b5 100644
>> --- a/man3/getauxval.3
>> +++ b/man3/getauxval.3
>> @@ -123,6 +123,33 @@ The instruction cache block size.
>> .\" .TP
>> .\" .BR AT_NOTELF
>> .TP
>> +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
>> +.BR AT_L1D_CACHEGEOMETRY
>> +Geometry of the L1 data cache, that is, line size and number
>> +of ways.
>
> What is "number of ways"?
>
It is the cache associativity, e.g.: 8 means the cache is 8-way set
associative.
> Thanks,
>
> Michael
>
>> +.TP
>> +.BR AT_L1D_CACHESIZE
>> +The L1 data cache size.
>> +.TP
>> +.BR AT_L1I_CACHEGEOMETRY
>> +Geometry of the L1 instruction cache, that is, line size and
>> +number of ways.
>> +.TP
>> +.BR AT_L1I_CACHESIZE
>> +The L1 instruction cache size.
>> +.TP
>> +.BR AT_L2_CACHEGEOMETRY
>> +Geometry of the L2 cache, that is, line size and number of ways.
>> +.TP
>> +.BR AT_L2_CACHESIZE
>> +The L2 cache size.
>> +.TP
>> +.BR AT_L3_CACHEGEOMETRY
>> +Geometry of the L3 cache, that is, line size and number of ways.
>> +.TP
>> +.BR AT_L3_CACHESIZE
>> +The L3 cache size.
>> +.TP
>> .BR AT_PAGESZ
>> The system page size (the same value returned by
>> .IR sysconf(_SC_PAGESIZE) ).
>>
>
>
Thanks,
--
Raphael Moreira Zinsly
IBM
Linux on Power Toolchain
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] getauxval.3: Add new cache geometry entries
2019-09-16 18:41 [PATCH] getauxval.3: Add new cache geometry entries Raphael Moreira Zinsly
2019-09-23 12:27 ` Michael Kerrisk (man-pages)
@ 2019-09-24 4:27 ` Michael Kerrisk (man-pages)
2019-09-24 13:11 ` [PATCH v2] " Raphael Moreira Zinsly
1 sibling, 1 reply; 8+ messages in thread
From: Michael Kerrisk (man-pages) @ 2019-09-24 4:27 UTC (permalink / raw)
To: Raphael Moreira Zinsly; +Cc: mtk.manpages, linux-man, benh, mpe
Hello Raphael,
On 9/16/19 8:41 PM, Raphael Moreira Zinsly wrote:
> Add entries for the new cache geometry values of the auxiliary vectors
> that got included in the kernel.
>
> Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
> ---
> man3/getauxval.3 | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/man3/getauxval.3 b/man3/getauxval.3
> index 794bc97b5..30f0757b5 100644
> --- a/man3/getauxval.3
> +++ b/man3/getauxval.3
> @@ -123,6 +123,33 @@ The instruction cache block size.
> .\" .TP
> .\" .BR AT_NOTELF
> .TP
> +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
> +.BR AT_L1D_CACHEGEOMETRY
> +Geometry of the L1 data cache, that is, line size and number
> +of ways.
Thanks for the clarification of "ways" in you other mail.
So, I think what could be added here is how these two pieces
of information are encoded into the value. Could you add a
sentence here? The other CACHEGEOMETRY entries could then
just have a sentence "Encoded as for AT_L1D_CACHEGEOMETRY."
Thanks,
Michael
> +.TP
> +.BR AT_L1D_CACHESIZE
> +The L1 data cache size.
> +.TP
> +.BR AT_L1I_CACHEGEOMETRY
> +Geometry of the L1 instruction cache, that is, line size and
> +number of ways.
> +.TP
> +.BR AT_L1I_CACHESIZE
> +The L1 instruction cache size.
> +.TP
> +.BR AT_L2_CACHEGEOMETRY
> +Geometry of the L2 cache, that is, line size and number of ways.
> +.TP
> +.BR AT_L2_CACHESIZE
> +The L2 cache size.
> +.TP
> +.BR AT_L3_CACHEGEOMETRY
> +Geometry of the L3 cache, that is, line size and number of ways.
> +.TP
> +.BR AT_L3_CACHESIZE
> +The L3 cache size.
> +.TP
> .BR AT_PAGESZ
> The system page size (the same value returned by
> .IR sysconf(_SC_PAGESIZE) ).
>
--
Michael Kerrisk
Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
Linux/UNIX System Programming Training: http://man7.org/training/
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] getauxval.3: Add new cache geometry entries
2019-09-24 4:27 ` Michael Kerrisk (man-pages)
@ 2019-09-24 13:11 ` Raphael Moreira Zinsly
2019-09-24 20:05 ` Michael Kerrisk (man-pages)
0 siblings, 1 reply; 8+ messages in thread
From: Raphael Moreira Zinsly @ 2019-09-24 13:11 UTC (permalink / raw)
To: mtk.manpages; +Cc: linux-man, benh, mpe, Raphael Moreira Zinsly
Add entries for the new cache geometry values of the auxiliary vectors
that got included in the kernel.
Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
---
man3/getauxval.3 | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/man3/getauxval.3 b/man3/getauxval.3
index 794bc97b5..b78a63225 100644
--- a/man3/getauxval.3
+++ b/man3/getauxval.3
@@ -123,6 +123,34 @@ The instruction cache block size.
.\" .TP
.\" .BR AT_NOTELF
.TP
+.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
+.BR AT_L1D_CACHEGEOMETRY
+Geometry of the L1 data cache, encoded with the cache line size in
+bytes in the bottom 16 bits and the cache associativity in the next 16
+bits. The associativity is such that if N is the 16-bit value, the cache
+is N-way set associative.
+.TP
+.BR AT_L1D_CACHESIZE
+The L1 data cache size.
+.TP
+.BR AT_L1I_CACHEGEOMETRY
+Geometry of the L1 instruction cache, encoded as for AT_L1D_CACHEGEOMETRY.
+.TP
+.BR AT_L1I_CACHESIZE
+The L1 instruction cache size.
+.TP
+.BR AT_L2_CACHEGEOMETRY
+Geometry of the L2 cache, encoded as for AT_L1D_CACHEGEOMETRY.
+.TP
+.BR AT_L2_CACHESIZE
+The L2 cache size.
+.TP
+.BR AT_L3_CACHEGEOMETRY
+Geometry of the L3 cache, encoded as for AT_L1D_CACHEGEOMETRY.
+.TP
+.BR AT_L3_CACHESIZE
+The L3 cache size.
+.TP
.BR AT_PAGESZ
The system page size (the same value returned by
.IR sysconf(_SC_PAGESIZE) ).
--
2.21.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] getauxval.3: Add new cache geometry entries
2019-09-23 13:36 ` Raphael M Zinsly
@ 2019-09-24 18:41 ` G. Branden Robinson
2019-09-24 20:08 ` Michael Kerrisk (man-pages)
0 siblings, 1 reply; 8+ messages in thread
From: G. Branden Robinson @ 2019-09-24 18:41 UTC (permalink / raw)
To: Michael Kerrisk (man-pages), linux-man, benh, mpe
[-- Attachment #1: Type: text/plain, Size: 1013 bytes --]
At 2019-09-23T10:36:16-0300, Raphael M Zinsly wrote:
> > > +Geometry of the L1 data cache, that is, line size and number
> > > +of ways.
> >
> > What is "number of ways"?
>
> It is the cache associativity, e.g.: 8 means the cache is 8-way set
> associative.
Yup. At some point when I wasn't looking, the "-way" in "n-way cache"
got promoted from a partial adjective along the lines of "all cars must
halt at the four-way stop sign" to a full-blooded noun and term of art.
I bumped into it while proofreading a Ph.D. thesis[1].
To help familiarize practitioners with the new cloak of terminology
draped over this hoary descendant of Old English "weg", I suggest adding
a parenthetical:
Geometry of the L1 data cache; that is, line size and number of ways
(e.g., \(lq4-way associative\(rq).
Regards,
Branden
[1] Ge, Qian, "Mitigating Microarchitecture-based Timing Channels with
Lightweight Operating System Mechanisms", Ph.D. thesis, University of
New South Wales, in press.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] getauxval.3: Add new cache geometry entries
2019-09-24 13:11 ` [PATCH v2] " Raphael Moreira Zinsly
@ 2019-09-24 20:05 ` Michael Kerrisk (man-pages)
0 siblings, 0 replies; 8+ messages in thread
From: Michael Kerrisk (man-pages) @ 2019-09-24 20:05 UTC (permalink / raw)
To: Raphael Moreira Zinsly; +Cc: mtk.manpages, linux-man, benh, mpe
Hello Raphael,
On 9/24/19 3:11 PM, Raphael Moreira Zinsly wrote:
> Add entries for the new cache geometry values of the auxiliary vectors
> that got included in the kernel.
Thanks the rewording, and also the explanation of the geometry
value.
I've applied the patch.
Thanks,
Michael
> Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
> ---
> man3/getauxval.3 | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/man3/getauxval.3 b/man3/getauxval.3
> index 794bc97b5..b78a63225 100644
> --- a/man3/getauxval.3
> +++ b/man3/getauxval.3
> @@ -123,6 +123,34 @@ The instruction cache block size.
> .\" .TP
> .\" .BR AT_NOTELF
> .TP
> +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
> +.BR AT_L1D_CACHEGEOMETRY
> +Geometry of the L1 data cache, encoded with the cache line size in
> +bytes in the bottom 16 bits and the cache associativity in the next 16
> +bits. The associativity is such that if N is the 16-bit value, the cache
> +is N-way set associative.
> +.TP
> +.BR AT_L1D_CACHESIZE
> +The L1 data cache size.
> +.TP
> +.BR AT_L1I_CACHEGEOMETRY
> +Geometry of the L1 instruction cache, encoded as for AT_L1D_CACHEGEOMETRY.
> +.TP
> +.BR AT_L1I_CACHESIZE
> +The L1 instruction cache size.
> +.TP
> +.BR AT_L2_CACHEGEOMETRY
> +Geometry of the L2 cache, encoded as for AT_L1D_CACHEGEOMETRY.
> +.TP
> +.BR AT_L2_CACHESIZE
> +The L2 cache size.
> +.TP
> +.BR AT_L3_CACHEGEOMETRY
> +Geometry of the L3 cache, encoded as for AT_L1D_CACHEGEOMETRY.
> +.TP
> +.BR AT_L3_CACHESIZE
> +The L3 cache size.
> +.TP
> .BR AT_PAGESZ
> The system page size (the same value returned by
> .IR sysconf(_SC_PAGESIZE) ).
>
--
Michael Kerrisk
Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
Linux/UNIX System Programming Training: http://man7.org/training/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] getauxval.3: Add new cache geometry entries
2019-09-24 18:41 ` G. Branden Robinson
@ 2019-09-24 20:08 ` Michael Kerrisk (man-pages)
0 siblings, 0 replies; 8+ messages in thread
From: Michael Kerrisk (man-pages) @ 2019-09-24 20:08 UTC (permalink / raw)
To: G. Branden Robinson, linux-man, benh, mpe; +Cc: mtk.manpages
On 9/24/19 8:41 PM, G. Branden Robinson wrote:
> At 2019-09-23T10:36:16-0300, Raphael M Zinsly wrote:
>>>> +Geometry of the L1 data cache, that is, line size and number
>>>> +of ways.
>>>
>>> What is "number of ways"?
>>
>> It is the cache associativity, e.g.: 8 means the cache is 8-way set
>> associative.
>
> Yup. At some point when I wasn't looking, the "-way" in "n-way cache"
> got promoted from a partial adjective along the lines of "all cars must
> halt at the four-way stop sign" to a full-blooded noun and term of art.
> I bumped into it while proofreading a Ph.D. thesis[1].
>
> To help familiarize practitioners with the new cloak of terminology
> draped over this hoary descendant of Old English "weg", I suggest adding
> a parenthetical:
>
> Geometry of the L1 data cache; that is, line size and number of ways
> (e.g., \(lq4-way associative\(rq).
Thanks jumping in Branden. I think Raphael's revised patch clarifies
things in a similar way, so I'm happy.
Cheers,
Michael
--
Michael Kerrisk
Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
Linux/UNIX System Programming Training: http://man7.org/training/
^ permalink raw reply [flat|nested] 8+ messages in thread
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2019-09-16 18:41 [PATCH] getauxval.3: Add new cache geometry entries Raphael Moreira Zinsly
2019-09-23 12:27 ` Michael Kerrisk (man-pages)
2019-09-23 13:36 ` Raphael M Zinsly
2019-09-24 18:41 ` G. Branden Robinson
2019-09-24 20:08 ` Michael Kerrisk (man-pages)
2019-09-24 4:27 ` Michael Kerrisk (man-pages)
2019-09-24 13:11 ` [PATCH v2] " Raphael Moreira Zinsly
2019-09-24 20:05 ` Michael Kerrisk (man-pages)
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