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From: Paul Cercueil <paul@crapouillou.net>
To: Zhou Yanjie <zhouyanjie@zoho.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org,
	paul.burton@mips.com, tglx@linutronix.de, mark.rutland@arm.com,
	jason@lakedaemon.net, marc.zyngier@arm.com
Subject: Re: [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
Date: Mon, 29 Jul 2019 13:19:14 -0400
Message-ID: <1564420754.6633.0@crapouillou.net> (raw)
In-Reply-To: <1564335273-22931-2-git-send-email-zhouyanjie@zoho.com>

Hi Zhou,



Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> The interrupt handling method is changed from old-style cascade to
> chained_irq which is more appropriate. Also, it can process the
> corner situation that more than one irq is coming to a single
> chip at the same time.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  drivers/irqchip/irq-ingenic.c | 37 
> +++++++++++++++++++++++--------------
>  1 file changed, 23 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-ingenic.c 
> b/drivers/irqchip/irq-ingenic.c
> index f126255..49f7685 100644
> --- a/drivers/irqchip/irq-ingenic.c
> +++ b/drivers/irqchip/irq-ingenic.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later
>  /*
>   *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
> - *  JZ4740 platform IRQ support
> + *  Ingenic XBurst platform IRQ support
>   */
> 
>  #include <linux/errno.h>
> @@ -10,6 +10,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/ioport.h>
>  #include <linux/irqchip.h>
> +#include <linux/irqchip/chained_irq.h>
>  #include <linux/irqchip/ingenic.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> @@ -32,22 +33,34 @@ struct ingenic_intc_data {
>  #define JZ_REG_INTC_PENDING	0x10
>  #define CHIP_SIZE		0x20
> 
> -static irqreturn_t intc_cascade(int irq, void *data)
> +static void ingenic_chained_handle_irq(struct irq_desc *desc)
>  {
> -	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
> -	uint32_t irq_reg;
> +	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	bool have_irq = false;
> +	uint32_t pending;
>  	unsigned i;
> 
> +	chained_irq_enter(chip, desc);
>  	for (i = 0; i < intc->num_chips; i++) {
> -		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
> +		pending = readl(intc->base + (i * CHIP_SIZE) +
>  				JZ_REG_INTC_PENDING);
> -		if (!irq_reg)
> +		if (!pending)
>  			continue;
> 
> -		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
> +		have_irq = true;
> +		while (pending) {
> +			int bit = __fls(pending);

Use the for_each_set_bit() macro here, that will be simpler.


> +
> +			generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
> +			pending &= ~BIT(bit);
> +		}
>  	}
> 
> -	return IRQ_HANDLED;
> +	if (!have_irq)
> +		spurious_interrupt();
> +
> +	chained_irq_exit(chip, desc);
>  }
> 
>  static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t 
> mask)
> @@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
>  	intc_irq_set_mask(gc, gc->mask_cache);
>  }
> 
> -static struct irqaction intc_cascade_action = {
> -	.handler = intc_cascade,
> -	.name = "SoC intc cascade interrupt",
> -};
> -
>  static int __init ingenic_intc_of_init(struct device_node *node,
>  				       unsigned num_chips)
>  {
> @@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct 
> device_node *node,
>  	if (!domain)
>  		pr_warn("unable to register IRQ domain\n");
> 
> -	setup_irq(parent_irq, &intc_cascade_action);
> +	irq_set_chained_handler_and_data(parent_irq,
> +					ingenic_chained_handle_irq, intc);
>  	return 0;
> 
>  out_unmap_irq:
> --
> 2.7.4



  reply index

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-01-27 10:21   ` Marc Zyngier
2019-01-27 14:49     ` Zhou Yanjie
2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 4/4] " Zhou Yanjie
2019-01-30 19:43       ` Rob Herring
2019-01-26 15:38 ` [PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-01-26 15:38 ` [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
2019-01-27 10:14   ` Marc Zyngier
2019-01-27 14:51     ` Zhou Yanjie
2019-01-26 15:38 ` [PATCH 4/4] " Zhou Yanjie
2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings Zhou Yanjie
2019-07-26 13:36     ` Marc Zyngier
2019-07-28 17:39       ` Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500 Zhou Yanjie
2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-07-29 17:19     ` Paul Cercueil [this message]
2019-07-30  6:41       ` Zhou Yanjie
2019-07-28 17:34   ` [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-07-28 17:34   ` [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings Zhou Yanjie
2019-07-28 17:34   ` [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs Zhou Yanjie
2019-07-29 17:25     ` Paul Cercueil
2019-07-30  6:26       ` Zhou Yanjie
2019-10-02 11:25 ` Add process for more than one irq at the same time v5 Zhou Yanjie
2019-10-02 11:25   ` [PATCH 1/5 v5] irqchip: ingenic: Drop redundant irq_suspend / irq_resume functions Zhou Yanjie
2019-10-06  0:13     ` Paul Cercueil
2019-10-06  6:01       ` Zhou Yanjie
2019-10-02 11:25   ` [PATCH 2/5 v5] irqchip: ingenic: Error out if IRQ domain creation failed Zhou Yanjie
2019-10-02 11:25   ` [PATCH 3/5 v5] irqchip: ingenic: Get virq number from IRQ domain Zhou Yanjie
2019-10-02 11:25   ` [PATCH 4/5 v5] irqchip: ingenic: Alloc generic chips " Zhou Yanjie
2019-10-02 11:25   ` [PATCH 5/5 v5] irqchip: Ingenic: Add process for more than one irq at the same time Zhou Yanjie
2019-10-06  0:15     ` Paul Cercueil
2019-10-12  5:53 ` Add process for more than one irq at the same time v6 Zhou Yanjie
2019-10-12  5:53   ` [PATCH 1/5 v6] irqchip: ingenic: Drop redundant irq_suspend / irq_resume functions Zhou Yanjie
2019-11-11 10:49     ` Marc Zyngier
2019-10-12  5:53   ` [PATCH 2/5 v6] irqchip: ingenic: Error out if IRQ domain creation failed Zhou Yanjie
2019-10-12  5:53   ` [PATCH 3/5 v6] irqchip: ingenic: Get virq number from IRQ domain Zhou Yanjie
2019-10-12  5:53   ` [PATCH 4/5 v6] irqchip: ingenic: Alloc generic chips " Zhou Yanjie
2019-10-12  5:53   ` [PATCH 5/5 v6] irqchip: Ingenic: Add process for more than one irq at the same time Zhou Yanjie

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