* [PATCH 0/4] MIPS I/II FP signal context handling fixes
@ 2016-10-31 16:24 Maciej W. Rozycki
2016-10-31 16:24 ` Maciej W. Rozycki
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:24 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Hi,
These fix a bunch of MIPS I/II FP signal context handling issues I have
discovered while working on the recent FCSR updates. See individual patch
descriptions for details.
Please queue for the upstream merge.
Maciej
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/4] MIPS I/II FP signal context handling fixes
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
@ 2016-10-31 16:24 ` Maciej W. Rozycki
2016-10-31 16:25 ` [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling Maciej W. Rozycki
` (3 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:24 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Hi,
These fix a bunch of MIPS I/II FP signal context handling issues I have
discovered while working on the recent FCSR updates. See individual patch
descriptions for details.
Please queue for the upstream merge.
Maciej
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
2016-10-31 16:24 ` Maciej W. Rozycki
@ 2016-10-31 16:25 ` Maciej W. Rozycki
2016-10-31 16:25 ` Maciej W. Rozycki
2016-11-01 9:27 ` Paul Burton
2016-10-31 16:26 ` [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context Maciej W. Rozycki
` (2 subsequent siblings)
4 siblings, 2 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:25 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit 0ae8dceaebe3 ("Merge with 2.3.10.") and use the local
`fault' handler to recover from FP sigcontext access violation faults,
like corresponding code does in r4k_fpu.S. The `bad_stack' handler is
in syscall.c and is not suitable here as we want to propagate the error
condition up through the caller rather than killing the thread outright.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
I guess it hardly ever triggers and code still builds, so it has aged so
well...
Maciej
linux-mips-isa1-sig-fp-context-fault.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:36:46.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:37:20.891186000 +0100
@@ -21,7 +21,7 @@
#define EX(a,b) \
9: a,##b; \
.section __ex_table,"a"; \
- PTR 9b,bad_stack; \
+ PTR 9b,fault; \
.previous
.set noreorder
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling
2016-10-31 16:25 ` [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling Maciej W. Rozycki
@ 2016-10-31 16:25 ` Maciej W. Rozycki
2016-11-01 9:27 ` Paul Burton
1 sibling, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:25 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit 0ae8dceaebe3 ("Merge with 2.3.10.") and use the local
`fault' handler to recover from FP sigcontext access violation faults,
like corresponding code does in r4k_fpu.S. The `bad_stack' handler is
in syscall.c and is not suitable here as we want to propagate the error
condition up through the caller rather than killing the thread outright.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
I guess it hardly ever triggers and code still builds, so it has aged so
well...
Maciej
linux-mips-isa1-sig-fp-context-fault.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:36:46.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:37:20.891186000 +0100
@@ -21,7 +21,7 @@
#define EX(a,b) \
9: a,##b; \
.section __ex_table,"a"; \
- PTR 9b,bad_stack; \
+ PTR 9b,fault; \
.previous
.set noreorder
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
2016-10-31 16:24 ` Maciej W. Rozycki
2016-10-31 16:25 ` [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling Maciej W. Rozycki
@ 2016-10-31 16:26 ` Maciej W. Rozycki
2016-10-31 16:26 ` Maciej W. Rozycki
2016-10-31 16:27 ` [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets Maciej W. Rozycki
2016-10-31 16:27 ` [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout Maciej W. Rozycki
4 siblings, 1 reply; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:26 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.")
and remove the Floating Point Implementation Register (FIR) from the FP
register set recorded in a signal context with MIPS I processors too, in
line with the change applied to r4k_fpu.S.
The `sc_fpc_eir' slot is unused according to our current ABI and the FIR
register is read-only and always directly accessible from user software.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa1-sig-fp-context-dsp.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:17:38.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:19:40.565112000 +0100
@@ -64,13 +64,9 @@ LEAF(_save_fp_context)
EX(swc1 $f29,(SC_FPREGS+232)(a0))
EX(swc1 $f30,(SC_FPREGS+240)(a0))
EX(swc1 $f31,(SC_FPREGS+248)(a0))
- EX(sw t1,(SC_FPC_CSR)(a0))
- cfc1 t0,$0 # implementation/version
jr ra
+ EX(sw t1,(SC_FPC_CSR)(a0))
.set pop
- .set nomacro
- EX(sw t0,(SC_FPC_EIR)(a0))
- .set macro
END(_save_fp_context)
/*
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context
2016-10-31 16:26 ` [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context Maciej W. Rozycki
@ 2016-10-31 16:26 ` Maciej W. Rozycki
0 siblings, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:26 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.")
and remove the Floating Point Implementation Register (FIR) from the FP
register set recorded in a signal context with MIPS I processors too, in
line with the change applied to r4k_fpu.S.
The `sc_fpc_eir' slot is unused according to our current ABI and the FIR
register is read-only and always directly accessible from user software.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa1-sig-fp-context-dsp.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:17:38.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:19:40.565112000 +0100
@@ -64,13 +64,9 @@ LEAF(_save_fp_context)
EX(swc1 $f29,(SC_FPREGS+232)(a0))
EX(swc1 $f30,(SC_FPREGS+240)(a0))
EX(swc1 $f31,(SC_FPREGS+248)(a0))
- EX(sw t1,(SC_FPC_CSR)(a0))
- cfc1 t0,$0 # implementation/version
jr ra
+ EX(sw t1,(SC_FPC_CSR)(a0))
.set pop
- .set nomacro
- EX(sw t0,(SC_FPC_EIR)(a0))
- .set macro
END(_save_fp_context)
/*
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
` (2 preceding siblings ...)
2016-10-31 16:26 ` [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context Maciej W. Rozycki
@ 2016-10-31 16:27 ` Maciej W. Rozycki
2016-10-31 16:27 ` Maciej W. Rozycki
2016-11-01 9:31 ` Paul Burton
2016-10-31 16:27 ` [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout Maciej W. Rozycki
4 siblings, 2 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Paul Burton, linux-mips, linux-kernel
Fix a regression introduced with commit 2db9ca0a3551 ("MIPS: Use struct
mips_abi offsets to save FP context") for MIPS I/I FP signal contexts,
by converting save/restore code to the updated internal API. Start FGR
offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than
the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status
Register (FCSR).
Document the new internal API and adjust assembly code formatting for
consistency.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa12-sig-fp-context-offsets.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:28:09.266462000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:29:01.523906000 +0100
@@ -26,97 +26,104 @@
.set noreorder
.set mips1
- /* Save floating point context */
+
+/**
+ * _save_fp_context() - save FP context from the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
+ *
+ * Save FP context, including the 32 FP data registers and the FP
+ * control & status register, from the FPU to signal context.
+ */
LEAF(_save_fp_context)
.set push
SET_HARDFLOAT
li v0, 0 # assume success
- cfc1 t1,fcr31
- EX(swc1 $f0,(SC_FPREGS+0)(a0))
- EX(swc1 $f1,(SC_FPREGS+8)(a0))
- EX(swc1 $f2,(SC_FPREGS+16)(a0))
- EX(swc1 $f3,(SC_FPREGS+24)(a0))
- EX(swc1 $f4,(SC_FPREGS+32)(a0))
- EX(swc1 $f5,(SC_FPREGS+40)(a0))
- EX(swc1 $f6,(SC_FPREGS+48)(a0))
- EX(swc1 $f7,(SC_FPREGS+56)(a0))
- EX(swc1 $f8,(SC_FPREGS+64)(a0))
- EX(swc1 $f9,(SC_FPREGS+72)(a0))
- EX(swc1 $f10,(SC_FPREGS+80)(a0))
- EX(swc1 $f11,(SC_FPREGS+88)(a0))
- EX(swc1 $f12,(SC_FPREGS+96)(a0))
- EX(swc1 $f13,(SC_FPREGS+104)(a0))
- EX(swc1 $f14,(SC_FPREGS+112)(a0))
- EX(swc1 $f15,(SC_FPREGS+120)(a0))
- EX(swc1 $f16,(SC_FPREGS+128)(a0))
- EX(swc1 $f17,(SC_FPREGS+136)(a0))
- EX(swc1 $f18,(SC_FPREGS+144)(a0))
- EX(swc1 $f19,(SC_FPREGS+152)(a0))
- EX(swc1 $f20,(SC_FPREGS+160)(a0))
- EX(swc1 $f21,(SC_FPREGS+168)(a0))
- EX(swc1 $f22,(SC_FPREGS+176)(a0))
- EX(swc1 $f23,(SC_FPREGS+184)(a0))
- EX(swc1 $f24,(SC_FPREGS+192)(a0))
- EX(swc1 $f25,(SC_FPREGS+200)(a0))
- EX(swc1 $f26,(SC_FPREGS+208)(a0))
- EX(swc1 $f27,(SC_FPREGS+216)(a0))
- EX(swc1 $f28,(SC_FPREGS+224)(a0))
- EX(swc1 $f29,(SC_FPREGS+232)(a0))
- EX(swc1 $f30,(SC_FPREGS+240)(a0))
- EX(swc1 $f31,(SC_FPREGS+248)(a0))
+ cfc1 t1, fcr31
+ EX(swc1 $f0, 0(a0))
+ EX(swc1 $f1, 8(a0))
+ EX(swc1 $f2, 16(a0))
+ EX(swc1 $f3, 24(a0))
+ EX(swc1 $f4, 32(a0))
+ EX(swc1 $f5, 40(a0))
+ EX(swc1 $f6, 48(a0))
+ EX(swc1 $f7, 56(a0))
+ EX(swc1 $f8, 64(a0))
+ EX(swc1 $f9, 72(a0))
+ EX(swc1 $f10, 80(a0))
+ EX(swc1 $f11, 88(a0))
+ EX(swc1 $f12, 96(a0))
+ EX(swc1 $f13, 104(a0))
+ EX(swc1 $f14, 112(a0))
+ EX(swc1 $f15, 120(a0))
+ EX(swc1 $f16, 128(a0))
+ EX(swc1 $f17, 136(a0))
+ EX(swc1 $f18, 144(a0))
+ EX(swc1 $f19, 152(a0))
+ EX(swc1 $f20, 160(a0))
+ EX(swc1 $f21, 168(a0))
+ EX(swc1 $f22, 176(a0))
+ EX(swc1 $f23, 184(a0))
+ EX(swc1 $f24, 192(a0))
+ EX(swc1 $f25, 200(a0))
+ EX(swc1 $f26, 208(a0))
+ EX(swc1 $f27, 216(a0))
+ EX(swc1 $f28, 224(a0))
+ EX(swc1 $f29, 232(a0))
+ EX(swc1 $f30, 240(a0))
+ EX(swc1 $f31, 248(a0))
jr ra
- EX(sw t1,(SC_FPC_CSR)(a0))
+ EX(sw t1, (a1))
.set pop
END(_save_fp_context)
-/*
- * Restore FPU state:
- * - fp gp registers
- * - cp1 status/control register
+/**
+ * _restore_fp_context() - restore FP context to the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
*
- * We base the decision which registers to restore from the signal stack
- * frame on the current content of c0_status, not on the content of the
- * stack frame which might have been changed by the user.
+ * Restore FP context, including the 32 FP data registers and the FP
+ * control & status register, from signal context to the FPU.
*/
LEAF(_restore_fp_context)
.set push
SET_HARDFLOAT
li v0, 0 # assume success
- EX(lw t0,(SC_FPC_CSR)(a0))
- EX(lwc1 $f0,(SC_FPREGS+0)(a0))
- EX(lwc1 $f1,(SC_FPREGS+8)(a0))
- EX(lwc1 $f2,(SC_FPREGS+16)(a0))
- EX(lwc1 $f3,(SC_FPREGS+24)(a0))
- EX(lwc1 $f4,(SC_FPREGS+32)(a0))
- EX(lwc1 $f5,(SC_FPREGS+40)(a0))
- EX(lwc1 $f6,(SC_FPREGS+48)(a0))
- EX(lwc1 $f7,(SC_FPREGS+56)(a0))
- EX(lwc1 $f8,(SC_FPREGS+64)(a0))
- EX(lwc1 $f9,(SC_FPREGS+72)(a0))
- EX(lwc1 $f10,(SC_FPREGS+80)(a0))
- EX(lwc1 $f11,(SC_FPREGS+88)(a0))
- EX(lwc1 $f12,(SC_FPREGS+96)(a0))
- EX(lwc1 $f13,(SC_FPREGS+104)(a0))
- EX(lwc1 $f14,(SC_FPREGS+112)(a0))
- EX(lwc1 $f15,(SC_FPREGS+120)(a0))
- EX(lwc1 $f16,(SC_FPREGS+128)(a0))
- EX(lwc1 $f17,(SC_FPREGS+136)(a0))
- EX(lwc1 $f18,(SC_FPREGS+144)(a0))
- EX(lwc1 $f19,(SC_FPREGS+152)(a0))
- EX(lwc1 $f20,(SC_FPREGS+160)(a0))
- EX(lwc1 $f21,(SC_FPREGS+168)(a0))
- EX(lwc1 $f22,(SC_FPREGS+176)(a0))
- EX(lwc1 $f23,(SC_FPREGS+184)(a0))
- EX(lwc1 $f24,(SC_FPREGS+192)(a0))
- EX(lwc1 $f25,(SC_FPREGS+200)(a0))
- EX(lwc1 $f26,(SC_FPREGS+208)(a0))
- EX(lwc1 $f27,(SC_FPREGS+216)(a0))
- EX(lwc1 $f28,(SC_FPREGS+224)(a0))
- EX(lwc1 $f29,(SC_FPREGS+232)(a0))
- EX(lwc1 $f30,(SC_FPREGS+240)(a0))
- EX(lwc1 $f31,(SC_FPREGS+248)(a0))
+ EX(lw t0, (a1))
+ EX(lwc1 $f0, 0(a0))
+ EX(lwc1 $f1, 8(a0))
+ EX(lwc1 $f2, 16(a0))
+ EX(lwc1 $f3, 24(a0))
+ EX(lwc1 $f4, 32(a0))
+ EX(lwc1 $f5, 40(a0))
+ EX(lwc1 $f6, 48(a0))
+ EX(lwc1 $f7, 56(a0))
+ EX(lwc1 $f8, 64(a0))
+ EX(lwc1 $f9, 72(a0))
+ EX(lwc1 $f10, 80(a0))
+ EX(lwc1 $f11, 88(a0))
+ EX(lwc1 $f12, 96(a0))
+ EX(lwc1 $f13, 104(a0))
+ EX(lwc1 $f14, 112(a0))
+ EX(lwc1 $f15, 120(a0))
+ EX(lwc1 $f16, 128(a0))
+ EX(lwc1 $f17, 136(a0))
+ EX(lwc1 $f18, 144(a0))
+ EX(lwc1 $f19, 152(a0))
+ EX(lwc1 $f20, 160(a0))
+ EX(lwc1 $f21, 168(a0))
+ EX(lwc1 $f22, 176(a0))
+ EX(lwc1 $f23, 184(a0))
+ EX(lwc1 $f24, 192(a0))
+ EX(lwc1 $f25, 200(a0))
+ EX(lwc1 $f26, 208(a0))
+ EX(lwc1 $f27, 216(a0))
+ EX(lwc1 $f28, 224(a0))
+ EX(lwc1 $f29, 232(a0))
+ EX(lwc1 $f30, 240(a0))
+ EX(lwc1 $f31, 248(a0))
jr ra
- ctc1 t0,fcr31
+ ctc1 t0, fcr31
.set pop
END(_restore_fp_context)
.set reorder
Index: linux-sfr-test/arch/mips/kernel/r6000_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:28:57.927876000 +0100
+++ linux-sfr-test/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:29:12.415002000 +0100
@@ -21,7 +21,14 @@
.set push
SET_HARDFLOAT
- /* Save floating point context */
+/**
+ * _save_fp_context() - save FP context from the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
+ *
+ * Save FP context, including the 32 FP data registers and the FP
+ * control & status register, from the FPU to signal context.
+ */
LEAF(_save_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
@@ -30,59 +37,59 @@
cfc1 t1,fcr31
/* Store the 16 double precision registers */
- sdc1 $f0,(SC_FPREGS+0)(a0)
- sdc1 $f2,(SC_FPREGS+16)(a0)
- sdc1 $f4,(SC_FPREGS+32)(a0)
- sdc1 $f6,(SC_FPREGS+48)(a0)
- sdc1 $f8,(SC_FPREGS+64)(a0)
- sdc1 $f10,(SC_FPREGS+80)(a0)
- sdc1 $f12,(SC_FPREGS+96)(a0)
- sdc1 $f14,(SC_FPREGS+112)(a0)
- sdc1 $f16,(SC_FPREGS+128)(a0)
- sdc1 $f18,(SC_FPREGS+144)(a0)
- sdc1 $f20,(SC_FPREGS+160)(a0)
- sdc1 $f22,(SC_FPREGS+176)(a0)
- sdc1 $f24,(SC_FPREGS+192)(a0)
- sdc1 $f26,(SC_FPREGS+208)(a0)
- sdc1 $f28,(SC_FPREGS+224)(a0)
- sdc1 $f30,(SC_FPREGS+240)(a0)
+ sdc1 $f0,0(a0)
+ sdc1 $f2,16(a0)
+ sdc1 $f4,32(a0)
+ sdc1 $f6,48(a0)
+ sdc1 $f8,64(a0)
+ sdc1 $f10,80(a0)
+ sdc1 $f12,96(a0)
+ sdc1 $f14,112(a0)
+ sdc1 $f16,128(a0)
+ sdc1 $f18,144(a0)
+ sdc1 $f20,160(a0)
+ sdc1 $f22,176(a0)
+ sdc1 $f24,192(a0)
+ sdc1 $f26,208(a0)
+ sdc1 $f28,224(a0)
+ sdc1 $f30,240(a0)
jr ra
- sw t0,SC_FPC_CSR(a0)
+ sw t0,(a1)
1: jr ra
nop
END(_save_fp_context)
-/* Restore FPU state:
- * - fp gp registers
- * - cp1 status/control register
+/**
+ * _restore_fp_context() - restore FP context to the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
*
- * We base the decision which registers to restore from the signal stack
- * frame on the current content of c0_status, not on the content of the
- * stack frame which might have been changed by the user.
+ * Restore FP context, including the 32 FP data registers and the FP
+ * control & status register, from signal context to the FPU.
*/
LEAF(_restore_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
bgez t0,1f
- lw t0,SC_FPC_CSR(a0)
+ lw t0,(a1)
/* Restore the 16 double precision registers */
- ldc1 $f0,(SC_FPREGS+0)(a0)
- ldc1 $f2,(SC_FPREGS+16)(a0)
- ldc1 $f4,(SC_FPREGS+32)(a0)
- ldc1 $f6,(SC_FPREGS+48)(a0)
- ldc1 $f8,(SC_FPREGS+64)(a0)
- ldc1 $f10,(SC_FPREGS+80)(a0)
- ldc1 $f12,(SC_FPREGS+96)(a0)
- ldc1 $f14,(SC_FPREGS+112)(a0)
- ldc1 $f16,(SC_FPREGS+128)(a0)
- ldc1 $f18,(SC_FPREGS+144)(a0)
- ldc1 $f20,(SC_FPREGS+160)(a0)
- ldc1 $f22,(SC_FPREGS+176)(a0)
- ldc1 $f24,(SC_FPREGS+192)(a0)
- ldc1 $f26,(SC_FPREGS+208)(a0)
- ldc1 $f28,(SC_FPREGS+224)(a0)
- ldc1 $f30,(SC_FPREGS+240)(a0)
+ ldc1 $f0,0(a0)
+ ldc1 $f2,16(a0)
+ ldc1 $f4,32(a0)
+ ldc1 $f6,48(a0)
+ ldc1 $f8,64(a0)
+ ldc1 $f10,80(a0)
+ ldc1 $f12,96(a0)
+ ldc1 $f14,112(a0)
+ ldc1 $f16,128(a0)
+ ldc1 $f18,144(a0)
+ ldc1 $f20,160(a0)
+ ldc1 $f22,176(a0)
+ ldc1 $f24,192(a0)
+ ldc1 $f26,208(a0)
+ ldc1 $f28,224(a0)
+ ldc1 $f30,240(a0)
jr ra
ctc1 t0,fcr31
1: jr ra
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-10-31 16:27 ` [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets Maciej W. Rozycki
@ 2016-10-31 16:27 ` Maciej W. Rozycki
2016-11-01 9:31 ` Paul Burton
1 sibling, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Paul Burton, linux-mips, linux-kernel
Fix a regression introduced with commit 2db9ca0a3551 ("MIPS: Use struct
mips_abi offsets to save FP context") for MIPS I/I FP signal contexts,
by converting save/restore code to the updated internal API. Start FGR
offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than
the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status
Register (FCSR).
Document the new internal API and adjust assembly code formatting for
consistency.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa12-sig-fp-context-offsets.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:28:09.266462000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:29:01.523906000 +0100
@@ -26,97 +26,104 @@
.set noreorder
.set mips1
- /* Save floating point context */
+
+/**
+ * _save_fp_context() - save FP context from the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
+ *
+ * Save FP context, including the 32 FP data registers and the FP
+ * control & status register, from the FPU to signal context.
+ */
LEAF(_save_fp_context)
.set push
SET_HARDFLOAT
li v0, 0 # assume success
- cfc1 t1,fcr31
- EX(swc1 $f0,(SC_FPREGS+0)(a0))
- EX(swc1 $f1,(SC_FPREGS+8)(a0))
- EX(swc1 $f2,(SC_FPREGS+16)(a0))
- EX(swc1 $f3,(SC_FPREGS+24)(a0))
- EX(swc1 $f4,(SC_FPREGS+32)(a0))
- EX(swc1 $f5,(SC_FPREGS+40)(a0))
- EX(swc1 $f6,(SC_FPREGS+48)(a0))
- EX(swc1 $f7,(SC_FPREGS+56)(a0))
- EX(swc1 $f8,(SC_FPREGS+64)(a0))
- EX(swc1 $f9,(SC_FPREGS+72)(a0))
- EX(swc1 $f10,(SC_FPREGS+80)(a0))
- EX(swc1 $f11,(SC_FPREGS+88)(a0))
- EX(swc1 $f12,(SC_FPREGS+96)(a0))
- EX(swc1 $f13,(SC_FPREGS+104)(a0))
- EX(swc1 $f14,(SC_FPREGS+112)(a0))
- EX(swc1 $f15,(SC_FPREGS+120)(a0))
- EX(swc1 $f16,(SC_FPREGS+128)(a0))
- EX(swc1 $f17,(SC_FPREGS+136)(a0))
- EX(swc1 $f18,(SC_FPREGS+144)(a0))
- EX(swc1 $f19,(SC_FPREGS+152)(a0))
- EX(swc1 $f20,(SC_FPREGS+160)(a0))
- EX(swc1 $f21,(SC_FPREGS+168)(a0))
- EX(swc1 $f22,(SC_FPREGS+176)(a0))
- EX(swc1 $f23,(SC_FPREGS+184)(a0))
- EX(swc1 $f24,(SC_FPREGS+192)(a0))
- EX(swc1 $f25,(SC_FPREGS+200)(a0))
- EX(swc1 $f26,(SC_FPREGS+208)(a0))
- EX(swc1 $f27,(SC_FPREGS+216)(a0))
- EX(swc1 $f28,(SC_FPREGS+224)(a0))
- EX(swc1 $f29,(SC_FPREGS+232)(a0))
- EX(swc1 $f30,(SC_FPREGS+240)(a0))
- EX(swc1 $f31,(SC_FPREGS+248)(a0))
+ cfc1 t1, fcr31
+ EX(swc1 $f0, 0(a0))
+ EX(swc1 $f1, 8(a0))
+ EX(swc1 $f2, 16(a0))
+ EX(swc1 $f3, 24(a0))
+ EX(swc1 $f4, 32(a0))
+ EX(swc1 $f5, 40(a0))
+ EX(swc1 $f6, 48(a0))
+ EX(swc1 $f7, 56(a0))
+ EX(swc1 $f8, 64(a0))
+ EX(swc1 $f9, 72(a0))
+ EX(swc1 $f10, 80(a0))
+ EX(swc1 $f11, 88(a0))
+ EX(swc1 $f12, 96(a0))
+ EX(swc1 $f13, 104(a0))
+ EX(swc1 $f14, 112(a0))
+ EX(swc1 $f15, 120(a0))
+ EX(swc1 $f16, 128(a0))
+ EX(swc1 $f17, 136(a0))
+ EX(swc1 $f18, 144(a0))
+ EX(swc1 $f19, 152(a0))
+ EX(swc1 $f20, 160(a0))
+ EX(swc1 $f21, 168(a0))
+ EX(swc1 $f22, 176(a0))
+ EX(swc1 $f23, 184(a0))
+ EX(swc1 $f24, 192(a0))
+ EX(swc1 $f25, 200(a0))
+ EX(swc1 $f26, 208(a0))
+ EX(swc1 $f27, 216(a0))
+ EX(swc1 $f28, 224(a0))
+ EX(swc1 $f29, 232(a0))
+ EX(swc1 $f30, 240(a0))
+ EX(swc1 $f31, 248(a0))
jr ra
- EX(sw t1,(SC_FPC_CSR)(a0))
+ EX(sw t1, (a1))
.set pop
END(_save_fp_context)
-/*
- * Restore FPU state:
- * - fp gp registers
- * - cp1 status/control register
+/**
+ * _restore_fp_context() - restore FP context to the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
*
- * We base the decision which registers to restore from the signal stack
- * frame on the current content of c0_status, not on the content of the
- * stack frame which might have been changed by the user.
+ * Restore FP context, including the 32 FP data registers and the FP
+ * control & status register, from signal context to the FPU.
*/
LEAF(_restore_fp_context)
.set push
SET_HARDFLOAT
li v0, 0 # assume success
- EX(lw t0,(SC_FPC_CSR)(a0))
- EX(lwc1 $f0,(SC_FPREGS+0)(a0))
- EX(lwc1 $f1,(SC_FPREGS+8)(a0))
- EX(lwc1 $f2,(SC_FPREGS+16)(a0))
- EX(lwc1 $f3,(SC_FPREGS+24)(a0))
- EX(lwc1 $f4,(SC_FPREGS+32)(a0))
- EX(lwc1 $f5,(SC_FPREGS+40)(a0))
- EX(lwc1 $f6,(SC_FPREGS+48)(a0))
- EX(lwc1 $f7,(SC_FPREGS+56)(a0))
- EX(lwc1 $f8,(SC_FPREGS+64)(a0))
- EX(lwc1 $f9,(SC_FPREGS+72)(a0))
- EX(lwc1 $f10,(SC_FPREGS+80)(a0))
- EX(lwc1 $f11,(SC_FPREGS+88)(a0))
- EX(lwc1 $f12,(SC_FPREGS+96)(a0))
- EX(lwc1 $f13,(SC_FPREGS+104)(a0))
- EX(lwc1 $f14,(SC_FPREGS+112)(a0))
- EX(lwc1 $f15,(SC_FPREGS+120)(a0))
- EX(lwc1 $f16,(SC_FPREGS+128)(a0))
- EX(lwc1 $f17,(SC_FPREGS+136)(a0))
- EX(lwc1 $f18,(SC_FPREGS+144)(a0))
- EX(lwc1 $f19,(SC_FPREGS+152)(a0))
- EX(lwc1 $f20,(SC_FPREGS+160)(a0))
- EX(lwc1 $f21,(SC_FPREGS+168)(a0))
- EX(lwc1 $f22,(SC_FPREGS+176)(a0))
- EX(lwc1 $f23,(SC_FPREGS+184)(a0))
- EX(lwc1 $f24,(SC_FPREGS+192)(a0))
- EX(lwc1 $f25,(SC_FPREGS+200)(a0))
- EX(lwc1 $f26,(SC_FPREGS+208)(a0))
- EX(lwc1 $f27,(SC_FPREGS+216)(a0))
- EX(lwc1 $f28,(SC_FPREGS+224)(a0))
- EX(lwc1 $f29,(SC_FPREGS+232)(a0))
- EX(lwc1 $f30,(SC_FPREGS+240)(a0))
- EX(lwc1 $f31,(SC_FPREGS+248)(a0))
+ EX(lw t0, (a1))
+ EX(lwc1 $f0, 0(a0))
+ EX(lwc1 $f1, 8(a0))
+ EX(lwc1 $f2, 16(a0))
+ EX(lwc1 $f3, 24(a0))
+ EX(lwc1 $f4, 32(a0))
+ EX(lwc1 $f5, 40(a0))
+ EX(lwc1 $f6, 48(a0))
+ EX(lwc1 $f7, 56(a0))
+ EX(lwc1 $f8, 64(a0))
+ EX(lwc1 $f9, 72(a0))
+ EX(lwc1 $f10, 80(a0))
+ EX(lwc1 $f11, 88(a0))
+ EX(lwc1 $f12, 96(a0))
+ EX(lwc1 $f13, 104(a0))
+ EX(lwc1 $f14, 112(a0))
+ EX(lwc1 $f15, 120(a0))
+ EX(lwc1 $f16, 128(a0))
+ EX(lwc1 $f17, 136(a0))
+ EX(lwc1 $f18, 144(a0))
+ EX(lwc1 $f19, 152(a0))
+ EX(lwc1 $f20, 160(a0))
+ EX(lwc1 $f21, 168(a0))
+ EX(lwc1 $f22, 176(a0))
+ EX(lwc1 $f23, 184(a0))
+ EX(lwc1 $f24, 192(a0))
+ EX(lwc1 $f25, 200(a0))
+ EX(lwc1 $f26, 208(a0))
+ EX(lwc1 $f27, 216(a0))
+ EX(lwc1 $f28, 224(a0))
+ EX(lwc1 $f29, 232(a0))
+ EX(lwc1 $f30, 240(a0))
+ EX(lwc1 $f31, 248(a0))
jr ra
- ctc1 t0,fcr31
+ ctc1 t0, fcr31
.set pop
END(_restore_fp_context)
.set reorder
Index: linux-sfr-test/arch/mips/kernel/r6000_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:28:57.927876000 +0100
+++ linux-sfr-test/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:29:12.415002000 +0100
@@ -21,7 +21,14 @@
.set push
SET_HARDFLOAT
- /* Save floating point context */
+/**
+ * _save_fp_context() - save FP context from the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
+ *
+ * Save FP context, including the 32 FP data registers and the FP
+ * control & status register, from the FPU to signal context.
+ */
LEAF(_save_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
@@ -30,59 +37,59 @@
cfc1 t1,fcr31
/* Store the 16 double precision registers */
- sdc1 $f0,(SC_FPREGS+0)(a0)
- sdc1 $f2,(SC_FPREGS+16)(a0)
- sdc1 $f4,(SC_FPREGS+32)(a0)
- sdc1 $f6,(SC_FPREGS+48)(a0)
- sdc1 $f8,(SC_FPREGS+64)(a0)
- sdc1 $f10,(SC_FPREGS+80)(a0)
- sdc1 $f12,(SC_FPREGS+96)(a0)
- sdc1 $f14,(SC_FPREGS+112)(a0)
- sdc1 $f16,(SC_FPREGS+128)(a0)
- sdc1 $f18,(SC_FPREGS+144)(a0)
- sdc1 $f20,(SC_FPREGS+160)(a0)
- sdc1 $f22,(SC_FPREGS+176)(a0)
- sdc1 $f24,(SC_FPREGS+192)(a0)
- sdc1 $f26,(SC_FPREGS+208)(a0)
- sdc1 $f28,(SC_FPREGS+224)(a0)
- sdc1 $f30,(SC_FPREGS+240)(a0)
+ sdc1 $f0,0(a0)
+ sdc1 $f2,16(a0)
+ sdc1 $f4,32(a0)
+ sdc1 $f6,48(a0)
+ sdc1 $f8,64(a0)
+ sdc1 $f10,80(a0)
+ sdc1 $f12,96(a0)
+ sdc1 $f14,112(a0)
+ sdc1 $f16,128(a0)
+ sdc1 $f18,144(a0)
+ sdc1 $f20,160(a0)
+ sdc1 $f22,176(a0)
+ sdc1 $f24,192(a0)
+ sdc1 $f26,208(a0)
+ sdc1 $f28,224(a0)
+ sdc1 $f30,240(a0)
jr ra
- sw t0,SC_FPC_CSR(a0)
+ sw t0,(a1)
1: jr ra
nop
END(_save_fp_context)
-/* Restore FPU state:
- * - fp gp registers
- * - cp1 status/control register
+/**
+ * _restore_fp_context() - restore FP context to the FPU
+ * @a0 - pointer to fpregs field of sigcontext
+ * @a1 - pointer to fpc_csr field of sigcontext
*
- * We base the decision which registers to restore from the signal stack
- * frame on the current content of c0_status, not on the content of the
- * stack frame which might have been changed by the user.
+ * Restore FP context, including the 32 FP data registers and the FP
+ * control & status register, from signal context to the FPU.
*/
LEAF(_restore_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
bgez t0,1f
- lw t0,SC_FPC_CSR(a0)
+ lw t0,(a1)
/* Restore the 16 double precision registers */
- ldc1 $f0,(SC_FPREGS+0)(a0)
- ldc1 $f2,(SC_FPREGS+16)(a0)
- ldc1 $f4,(SC_FPREGS+32)(a0)
- ldc1 $f6,(SC_FPREGS+48)(a0)
- ldc1 $f8,(SC_FPREGS+64)(a0)
- ldc1 $f10,(SC_FPREGS+80)(a0)
- ldc1 $f12,(SC_FPREGS+96)(a0)
- ldc1 $f14,(SC_FPREGS+112)(a0)
- ldc1 $f16,(SC_FPREGS+128)(a0)
- ldc1 $f18,(SC_FPREGS+144)(a0)
- ldc1 $f20,(SC_FPREGS+160)(a0)
- ldc1 $f22,(SC_FPREGS+176)(a0)
- ldc1 $f24,(SC_FPREGS+192)(a0)
- ldc1 $f26,(SC_FPREGS+208)(a0)
- ldc1 $f28,(SC_FPREGS+224)(a0)
- ldc1 $f30,(SC_FPREGS+240)(a0)
+ ldc1 $f0,0(a0)
+ ldc1 $f2,16(a0)
+ ldc1 $f4,32(a0)
+ ldc1 $f6,48(a0)
+ ldc1 $f8,64(a0)
+ ldc1 $f10,80(a0)
+ ldc1 $f12,96(a0)
+ ldc1 $f14,112(a0)
+ ldc1 $f16,128(a0)
+ ldc1 $f18,144(a0)
+ ldc1 $f20,160(a0)
+ ldc1 $f22,176(a0)
+ ldc1 $f24,192(a0)
+ ldc1 $f26,208(a0)
+ ldc1 $f28,224(a0)
+ ldc1 $f30,240(a0)
jr ra
ctc1 t0,fcr31
1: jr ra
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
` (3 preceding siblings ...)
2016-10-31 16:27 ` [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets Maciej W. Rozycki
@ 2016-10-31 16:27 ` Maciej W. Rozycki
2016-10-31 16:27 ` Maciej W. Rozycki
4 siblings, 1 reply; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit 80cbfad79096 ("MIPS: Correct MIPS I FP context
layout") and correct the way Floating Point General registers are stored
in a signal context with MIPS I hardware.
Use the S.D and L.D assembly macros to have pairs of SWC1 instructions
and pairs of LWC1 instructions produced, respectively, in an arrangement
which makes the memory representation of floating-point data passed
compatible with that used by hardware SDC1 and LDC1 instructions, where
available, regardless of the hardware endianness used. This matches the
layout used by r4k_fpu.S, ensuring run-time compatibility for MIPS I
software across all o32 hardware platforms.
Define an EX2 macro to handle exceptions from both hardware instructions
implicitly produced from S.D and L.D assembly macros.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa1-sig-fp-context.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:38:03.979547000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:41:53.059507000 +0100
@@ -24,6 +24,13 @@
PTR 9b,fault; \
.previous
+#define EX2(a,b) \
+9: a,##b; \
+ .section __ex_table,"a"; \
+ PTR 9b,bad_stack; \
+ PTR 9b+4,bad_stack; \
+ .previous
+
.set noreorder
.set mips1
@@ -40,38 +47,22 @@ LEAF(_save_fp_context)
SET_HARDFLOAT
li v0, 0 # assume success
cfc1 t1, fcr31
- EX(swc1 $f0, 0(a0))
- EX(swc1 $f1, 8(a0))
- EX(swc1 $f2, 16(a0))
- EX(swc1 $f3, 24(a0))
- EX(swc1 $f4, 32(a0))
- EX(swc1 $f5, 40(a0))
- EX(swc1 $f6, 48(a0))
- EX(swc1 $f7, 56(a0))
- EX(swc1 $f8, 64(a0))
- EX(swc1 $f9, 72(a0))
- EX(swc1 $f10, 80(a0))
- EX(swc1 $f11, 88(a0))
- EX(swc1 $f12, 96(a0))
- EX(swc1 $f13, 104(a0))
- EX(swc1 $f14, 112(a0))
- EX(swc1 $f15, 120(a0))
- EX(swc1 $f16, 128(a0))
- EX(swc1 $f17, 136(a0))
- EX(swc1 $f18, 144(a0))
- EX(swc1 $f19, 152(a0))
- EX(swc1 $f20, 160(a0))
- EX(swc1 $f21, 168(a0))
- EX(swc1 $f22, 176(a0))
- EX(swc1 $f23, 184(a0))
- EX(swc1 $f24, 192(a0))
- EX(swc1 $f25, 200(a0))
- EX(swc1 $f26, 208(a0))
- EX(swc1 $f27, 216(a0))
- EX(swc1 $f28, 224(a0))
- EX(swc1 $f29, 232(a0))
- EX(swc1 $f30, 240(a0))
- EX(swc1 $f31, 248(a0))
+ EX2(s.d $f0, 0(a0))
+ EX2(s.d $f2, 16(a0))
+ EX2(s.d $f4, 32(a0))
+ EX2(s.d $f6, 48(a0))
+ EX2(s.d $f8, 64(a0))
+ EX2(s.d $f10, 80(a0))
+ EX2(s.d $f12, 96(a0))
+ EX2(s.d $f14, 112(a0))
+ EX2(s.d $f16, 128(a0))
+ EX2(s.d $f18, 144(a0))
+ EX2(s.d $f20, 160(a0))
+ EX2(s.d $f22, 176(a0))
+ EX2(s.d $f24, 192(a0))
+ EX2(s.d $f26, 208(a0))
+ EX2(s.d $f28, 224(a0))
+ EX2(s.d $f30, 240(a0))
jr ra
EX(sw t1, (a1))
.set pop
@@ -90,38 +81,22 @@ LEAF(_restore_fp_context)
SET_HARDFLOAT
li v0, 0 # assume success
EX(lw t0, (a1))
- EX(lwc1 $f0, 0(a0))
- EX(lwc1 $f1, 8(a0))
- EX(lwc1 $f2, 16(a0))
- EX(lwc1 $f3, 24(a0))
- EX(lwc1 $f4, 32(a0))
- EX(lwc1 $f5, 40(a0))
- EX(lwc1 $f6, 48(a0))
- EX(lwc1 $f7, 56(a0))
- EX(lwc1 $f8, 64(a0))
- EX(lwc1 $f9, 72(a0))
- EX(lwc1 $f10, 80(a0))
- EX(lwc1 $f11, 88(a0))
- EX(lwc1 $f12, 96(a0))
- EX(lwc1 $f13, 104(a0))
- EX(lwc1 $f14, 112(a0))
- EX(lwc1 $f15, 120(a0))
- EX(lwc1 $f16, 128(a0))
- EX(lwc1 $f17, 136(a0))
- EX(lwc1 $f18, 144(a0))
- EX(lwc1 $f19, 152(a0))
- EX(lwc1 $f20, 160(a0))
- EX(lwc1 $f21, 168(a0))
- EX(lwc1 $f22, 176(a0))
- EX(lwc1 $f23, 184(a0))
- EX(lwc1 $f24, 192(a0))
- EX(lwc1 $f25, 200(a0))
- EX(lwc1 $f26, 208(a0))
- EX(lwc1 $f27, 216(a0))
- EX(lwc1 $f28, 224(a0))
- EX(lwc1 $f29, 232(a0))
- EX(lwc1 $f30, 240(a0))
- EX(lwc1 $f31, 248(a0))
+ EX2(l.d $f0, 0(a0))
+ EX2(l.d $f2, 16(a0))
+ EX2(l.d $f4, 32(a0))
+ EX2(l.d $f6, 48(a0))
+ EX2(l.d $f8, 64(a0))
+ EX2(l.d $f10, 80(a0))
+ EX2(l.d $f12, 96(a0))
+ EX2(l.d $f14, 112(a0))
+ EX2(l.d $f16, 128(a0))
+ EX2(l.d $f18, 144(a0))
+ EX2(l.d $f20, 160(a0))
+ EX2(l.d $f22, 176(a0))
+ EX2(l.d $f24, 192(a0))
+ EX2(l.d $f26, 208(a0))
+ EX2(l.d $f28, 224(a0))
+ EX2(l.d $f30, 240(a0))
jr ra
ctc1 t0, fcr31
.set pop
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout
2016-10-31 16:27 ` [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout Maciej W. Rozycki
@ 2016-10-31 16:27 ` Maciej W. Rozycki
0 siblings, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-10-31 16:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
Complement commit 80cbfad79096 ("MIPS: Correct MIPS I FP context
layout") and correct the way Floating Point General registers are stored
in a signal context with MIPS I hardware.
Use the S.D and L.D assembly macros to have pairs of SWC1 instructions
and pairs of LWC1 instructions produced, respectively, in an arrangement
which makes the memory representation of floating-point data passed
compatible with that used by hardware SDC1 and LDC1 instructions, where
available, regardless of the hardware endianness used. This matches the
layout used by r4k_fpu.S, ensuring run-time compatibility for MIPS I
software across all o32 hardware platforms.
Define an EX2 macro to handle exceptions from both hardware instructions
implicitly produced from S.D and L.D assembly macros.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-isa1-sig-fp-context.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:38:03.979547000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:41:53.059507000 +0100
@@ -24,6 +24,13 @@
PTR 9b,fault; \
.previous
+#define EX2(a,b) \
+9: a,##b; \
+ .section __ex_table,"a"; \
+ PTR 9b,bad_stack; \
+ PTR 9b+4,bad_stack; \
+ .previous
+
.set noreorder
.set mips1
@@ -40,38 +47,22 @@ LEAF(_save_fp_context)
SET_HARDFLOAT
li v0, 0 # assume success
cfc1 t1, fcr31
- EX(swc1 $f0, 0(a0))
- EX(swc1 $f1, 8(a0))
- EX(swc1 $f2, 16(a0))
- EX(swc1 $f3, 24(a0))
- EX(swc1 $f4, 32(a0))
- EX(swc1 $f5, 40(a0))
- EX(swc1 $f6, 48(a0))
- EX(swc1 $f7, 56(a0))
- EX(swc1 $f8, 64(a0))
- EX(swc1 $f9, 72(a0))
- EX(swc1 $f10, 80(a0))
- EX(swc1 $f11, 88(a0))
- EX(swc1 $f12, 96(a0))
- EX(swc1 $f13, 104(a0))
- EX(swc1 $f14, 112(a0))
- EX(swc1 $f15, 120(a0))
- EX(swc1 $f16, 128(a0))
- EX(swc1 $f17, 136(a0))
- EX(swc1 $f18, 144(a0))
- EX(swc1 $f19, 152(a0))
- EX(swc1 $f20, 160(a0))
- EX(swc1 $f21, 168(a0))
- EX(swc1 $f22, 176(a0))
- EX(swc1 $f23, 184(a0))
- EX(swc1 $f24, 192(a0))
- EX(swc1 $f25, 200(a0))
- EX(swc1 $f26, 208(a0))
- EX(swc1 $f27, 216(a0))
- EX(swc1 $f28, 224(a0))
- EX(swc1 $f29, 232(a0))
- EX(swc1 $f30, 240(a0))
- EX(swc1 $f31, 248(a0))
+ EX2(s.d $f0, 0(a0))
+ EX2(s.d $f2, 16(a0))
+ EX2(s.d $f4, 32(a0))
+ EX2(s.d $f6, 48(a0))
+ EX2(s.d $f8, 64(a0))
+ EX2(s.d $f10, 80(a0))
+ EX2(s.d $f12, 96(a0))
+ EX2(s.d $f14, 112(a0))
+ EX2(s.d $f16, 128(a0))
+ EX2(s.d $f18, 144(a0))
+ EX2(s.d $f20, 160(a0))
+ EX2(s.d $f22, 176(a0))
+ EX2(s.d $f24, 192(a0))
+ EX2(s.d $f26, 208(a0))
+ EX2(s.d $f28, 224(a0))
+ EX2(s.d $f30, 240(a0))
jr ra
EX(sw t1, (a1))
.set pop
@@ -90,38 +81,22 @@ LEAF(_restore_fp_context)
SET_HARDFLOAT
li v0, 0 # assume success
EX(lw t0, (a1))
- EX(lwc1 $f0, 0(a0))
- EX(lwc1 $f1, 8(a0))
- EX(lwc1 $f2, 16(a0))
- EX(lwc1 $f3, 24(a0))
- EX(lwc1 $f4, 32(a0))
- EX(lwc1 $f5, 40(a0))
- EX(lwc1 $f6, 48(a0))
- EX(lwc1 $f7, 56(a0))
- EX(lwc1 $f8, 64(a0))
- EX(lwc1 $f9, 72(a0))
- EX(lwc1 $f10, 80(a0))
- EX(lwc1 $f11, 88(a0))
- EX(lwc1 $f12, 96(a0))
- EX(lwc1 $f13, 104(a0))
- EX(lwc1 $f14, 112(a0))
- EX(lwc1 $f15, 120(a0))
- EX(lwc1 $f16, 128(a0))
- EX(lwc1 $f17, 136(a0))
- EX(lwc1 $f18, 144(a0))
- EX(lwc1 $f19, 152(a0))
- EX(lwc1 $f20, 160(a0))
- EX(lwc1 $f21, 168(a0))
- EX(lwc1 $f22, 176(a0))
- EX(lwc1 $f23, 184(a0))
- EX(lwc1 $f24, 192(a0))
- EX(lwc1 $f25, 200(a0))
- EX(lwc1 $f26, 208(a0))
- EX(lwc1 $f27, 216(a0))
- EX(lwc1 $f28, 224(a0))
- EX(lwc1 $f29, 232(a0))
- EX(lwc1 $f30, 240(a0))
- EX(lwc1 $f31, 248(a0))
+ EX2(l.d $f0, 0(a0))
+ EX2(l.d $f2, 16(a0))
+ EX2(l.d $f4, 32(a0))
+ EX2(l.d $f6, 48(a0))
+ EX2(l.d $f8, 64(a0))
+ EX2(l.d $f10, 80(a0))
+ EX2(l.d $f12, 96(a0))
+ EX2(l.d $f14, 112(a0))
+ EX2(l.d $f16, 128(a0))
+ EX2(l.d $f18, 144(a0))
+ EX2(l.d $f20, 160(a0))
+ EX2(l.d $f22, 176(a0))
+ EX2(l.d $f24, 192(a0))
+ EX2(l.d $f26, 208(a0))
+ EX2(l.d $f28, 224(a0))
+ EX2(l.d $f30, 240(a0))
jr ra
ctc1 t0, fcr31
.set pop
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling
2016-10-31 16:25 ` [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling Maciej W. Rozycki
2016-10-31 16:25 ` Maciej W. Rozycki
@ 2016-11-01 9:27 ` Paul Burton
2016-11-01 9:27 ` Paul Burton
1 sibling, 1 reply; 16+ messages in thread
From: Paul Burton @ 2016-11-01 9:27 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips, Ralf Baechle, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]
On Monday, 31 October 2016 16:25:44 GMT Maciej W. Rozycki wrote:
> Complement commit 0ae8dceaebe3 ("Merge with 2.3.10.") and use the local
> `fault' handler to recover from FP sigcontext access violation faults,
> like corresponding code does in r4k_fpu.S. The `bad_stack' handler is
> in syscall.c and is not suitable here as we want to propagate the error
> condition up through the caller rather than killing the thread outright.
>
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
> I guess it hardly ever triggers and code still builds, so it has aged so
> well...
>
> Maciej
>
> linux-mips-isa1-sig-fp-context-fault.patch
> Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22
> 02:36:46.000000000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:37:20.891186000
> +0100 @@ -21,7 +21,7 @@
> #define EX(a,b) \
> 9: a,##b; \
> .section __ex_table,"a"; \
> - PTR 9b,bad_stack; \
> + PTR 9b,fault; \
> .previous
>
> .set noreorder
Hi Maciej,
Looks good to me:
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Thanks,
Paul
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling
2016-11-01 9:27 ` Paul Burton
@ 2016-11-01 9:27 ` Paul Burton
0 siblings, 0 replies; 16+ messages in thread
From: Paul Burton @ 2016-11-01 9:27 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips, Ralf Baechle, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]
On Monday, 31 October 2016 16:25:44 GMT Maciej W. Rozycki wrote:
> Complement commit 0ae8dceaebe3 ("Merge with 2.3.10.") and use the local
> `fault' handler to recover from FP sigcontext access violation faults,
> like corresponding code does in r4k_fpu.S. The `bad_stack' handler is
> in syscall.c and is not suitable here as we want to propagate the error
> condition up through the caller rather than killing the thread outright.
>
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
> I guess it hardly ever triggers and code still builds, so it has aged so
> well...
>
> Maciej
>
> linux-mips-isa1-sig-fp-context-fault.patch
> Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22
> 02:36:46.000000000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:37:20.891186000
> +0100 @@ -21,7 +21,7 @@
> #define EX(a,b) \
> 9: a,##b; \
> .section __ex_table,"a"; \
> - PTR 9b,bad_stack; \
> + PTR 9b,fault; \
> .previous
>
> .set noreorder
Hi Maciej,
Looks good to me:
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Thanks,
Paul
[-- Attachment #2: This is a digitally signed message part. --]
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-10-31 16:27 ` [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets Maciej W. Rozycki
2016-10-31 16:27 ` Maciej W. Rozycki
@ 2016-11-01 9:31 ` Paul Burton
2016-11-01 9:31 ` Paul Burton
2016-11-01 11:49 ` Maciej W. Rozycki
1 sibling, 2 replies; 16+ messages in thread
From: Paul Burton @ 2016-11-01 9:31 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Ralf Baechle, linux-mips, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 10482 bytes --]
On Monday, 31 October 2016 16:27:01 GMT Maciej W. Rozycki wrote:
> Fix a regression introduced with commit 2db9ca0a3551 ("MIPS: Use struct
> mips_abi offsets to save FP context") for MIPS I/I FP signal contexts,
> by converting save/restore code to the updated internal API. Start FGR
> offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than
> the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status
> Register (FCSR).
>
> Document the new internal API and adjust assembly code formatting for
> consistency.
>
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
> linux-mips-isa12-sig-fp-context-offsets.patch
> Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22
> 02:28:09.266462000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:29:01.523906000
> +0100 @@ -26,97 +26,104 @@
>
> .set noreorder
> .set mips1
> - /* Save floating point context */
> +
> +/**
> + * _save_fp_context() - save FP context from the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> + *
> + * Save FP context, including the 32 FP data registers and the FP
> + * control & status register, from the FPU to signal context.
> + */
> LEAF(_save_fp_context)
> .set push
> SET_HARDFLOAT
> li v0, 0 # assume success
> - cfc1 t1,fcr31
> - EX(swc1 $f0,(SC_FPREGS+0)(a0))
> - EX(swc1 $f1,(SC_FPREGS+8)(a0))
> - EX(swc1 $f2,(SC_FPREGS+16)(a0))
> - EX(swc1 $f3,(SC_FPREGS+24)(a0))
> - EX(swc1 $f4,(SC_FPREGS+32)(a0))
> - EX(swc1 $f5,(SC_FPREGS+40)(a0))
> - EX(swc1 $f6,(SC_FPREGS+48)(a0))
> - EX(swc1 $f7,(SC_FPREGS+56)(a0))
> - EX(swc1 $f8,(SC_FPREGS+64)(a0))
> - EX(swc1 $f9,(SC_FPREGS+72)(a0))
> - EX(swc1 $f10,(SC_FPREGS+80)(a0))
> - EX(swc1 $f11,(SC_FPREGS+88)(a0))
> - EX(swc1 $f12,(SC_FPREGS+96)(a0))
> - EX(swc1 $f13,(SC_FPREGS+104)(a0))
> - EX(swc1 $f14,(SC_FPREGS+112)(a0))
> - EX(swc1 $f15,(SC_FPREGS+120)(a0))
> - EX(swc1 $f16,(SC_FPREGS+128)(a0))
> - EX(swc1 $f17,(SC_FPREGS+136)(a0))
> - EX(swc1 $f18,(SC_FPREGS+144)(a0))
> - EX(swc1 $f19,(SC_FPREGS+152)(a0))
> - EX(swc1 $f20,(SC_FPREGS+160)(a0))
> - EX(swc1 $f21,(SC_FPREGS+168)(a0))
> - EX(swc1 $f22,(SC_FPREGS+176)(a0))
> - EX(swc1 $f23,(SC_FPREGS+184)(a0))
> - EX(swc1 $f24,(SC_FPREGS+192)(a0))
> - EX(swc1 $f25,(SC_FPREGS+200)(a0))
> - EX(swc1 $f26,(SC_FPREGS+208)(a0))
> - EX(swc1 $f27,(SC_FPREGS+216)(a0))
> - EX(swc1 $f28,(SC_FPREGS+224)(a0))
> - EX(swc1 $f29,(SC_FPREGS+232)(a0))
> - EX(swc1 $f30,(SC_FPREGS+240)(a0))
> - EX(swc1 $f31,(SC_FPREGS+248)(a0))
> + cfc1 t1, fcr31
> + EX(swc1 $f0, 0(a0))
> + EX(swc1 $f1, 8(a0))
> + EX(swc1 $f2, 16(a0))
> + EX(swc1 $f3, 24(a0))
> + EX(swc1 $f4, 32(a0))
> + EX(swc1 $f5, 40(a0))
> + EX(swc1 $f6, 48(a0))
> + EX(swc1 $f7, 56(a0))
> + EX(swc1 $f8, 64(a0))
> + EX(swc1 $f9, 72(a0))
> + EX(swc1 $f10, 80(a0))
> + EX(swc1 $f11, 88(a0))
> + EX(swc1 $f12, 96(a0))
> + EX(swc1 $f13, 104(a0))
> + EX(swc1 $f14, 112(a0))
> + EX(swc1 $f15, 120(a0))
> + EX(swc1 $f16, 128(a0))
> + EX(swc1 $f17, 136(a0))
> + EX(swc1 $f18, 144(a0))
> + EX(swc1 $f19, 152(a0))
> + EX(swc1 $f20, 160(a0))
> + EX(swc1 $f21, 168(a0))
> + EX(swc1 $f22, 176(a0))
> + EX(swc1 $f23, 184(a0))
> + EX(swc1 $f24, 192(a0))
> + EX(swc1 $f25, 200(a0))
> + EX(swc1 $f26, 208(a0))
> + EX(swc1 $f27, 216(a0))
> + EX(swc1 $f28, 224(a0))
> + EX(swc1 $f29, 232(a0))
> + EX(swc1 $f30, 240(a0))
> + EX(swc1 $f31, 248(a0))
> jr ra
> - EX(sw t1,(SC_FPC_CSR)(a0))
> + EX(sw t1, (a1))
> .set pop
> END(_save_fp_context)
>
> -/*
> - * Restore FPU state:
> - * - fp gp registers
> - * - cp1 status/control register
> +/**
> + * _restore_fp_context() - restore FP context to the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> *
> - * We base the decision which registers to restore from the signal stack
> - * frame on the current content of c0_status, not on the content of the
> - * stack frame which might have been changed by the user.
> + * Restore FP context, including the 32 FP data registers and the FP
> + * control & status register, from signal context to the FPU.
> */
> LEAF(_restore_fp_context)
> .set push
> SET_HARDFLOAT
> li v0, 0 # assume success
> - EX(lw t0,(SC_FPC_CSR)(a0))
> - EX(lwc1 $f0,(SC_FPREGS+0)(a0))
> - EX(lwc1 $f1,(SC_FPREGS+8)(a0))
> - EX(lwc1 $f2,(SC_FPREGS+16)(a0))
> - EX(lwc1 $f3,(SC_FPREGS+24)(a0))
> - EX(lwc1 $f4,(SC_FPREGS+32)(a0))
> - EX(lwc1 $f5,(SC_FPREGS+40)(a0))
> - EX(lwc1 $f6,(SC_FPREGS+48)(a0))
> - EX(lwc1 $f7,(SC_FPREGS+56)(a0))
> - EX(lwc1 $f8,(SC_FPREGS+64)(a0))
> - EX(lwc1 $f9,(SC_FPREGS+72)(a0))
> - EX(lwc1 $f10,(SC_FPREGS+80)(a0))
> - EX(lwc1 $f11,(SC_FPREGS+88)(a0))
> - EX(lwc1 $f12,(SC_FPREGS+96)(a0))
> - EX(lwc1 $f13,(SC_FPREGS+104)(a0))
> - EX(lwc1 $f14,(SC_FPREGS+112)(a0))
> - EX(lwc1 $f15,(SC_FPREGS+120)(a0))
> - EX(lwc1 $f16,(SC_FPREGS+128)(a0))
> - EX(lwc1 $f17,(SC_FPREGS+136)(a0))
> - EX(lwc1 $f18,(SC_FPREGS+144)(a0))
> - EX(lwc1 $f19,(SC_FPREGS+152)(a0))
> - EX(lwc1 $f20,(SC_FPREGS+160)(a0))
> - EX(lwc1 $f21,(SC_FPREGS+168)(a0))
> - EX(lwc1 $f22,(SC_FPREGS+176)(a0))
> - EX(lwc1 $f23,(SC_FPREGS+184)(a0))
> - EX(lwc1 $f24,(SC_FPREGS+192)(a0))
> - EX(lwc1 $f25,(SC_FPREGS+200)(a0))
> - EX(lwc1 $f26,(SC_FPREGS+208)(a0))
> - EX(lwc1 $f27,(SC_FPREGS+216)(a0))
> - EX(lwc1 $f28,(SC_FPREGS+224)(a0))
> - EX(lwc1 $f29,(SC_FPREGS+232)(a0))
> - EX(lwc1 $f30,(SC_FPREGS+240)(a0))
> - EX(lwc1 $f31,(SC_FPREGS+248)(a0))
> + EX(lw t0, (a1))
> + EX(lwc1 $f0, 0(a0))
> + EX(lwc1 $f1, 8(a0))
> + EX(lwc1 $f2, 16(a0))
> + EX(lwc1 $f3, 24(a0))
> + EX(lwc1 $f4, 32(a0))
> + EX(lwc1 $f5, 40(a0))
> + EX(lwc1 $f6, 48(a0))
> + EX(lwc1 $f7, 56(a0))
> + EX(lwc1 $f8, 64(a0))
> + EX(lwc1 $f9, 72(a0))
> + EX(lwc1 $f10, 80(a0))
> + EX(lwc1 $f11, 88(a0))
> + EX(lwc1 $f12, 96(a0))
> + EX(lwc1 $f13, 104(a0))
> + EX(lwc1 $f14, 112(a0))
> + EX(lwc1 $f15, 120(a0))
> + EX(lwc1 $f16, 128(a0))
> + EX(lwc1 $f17, 136(a0))
> + EX(lwc1 $f18, 144(a0))
> + EX(lwc1 $f19, 152(a0))
> + EX(lwc1 $f20, 160(a0))
> + EX(lwc1 $f21, 168(a0))
> + EX(lwc1 $f22, 176(a0))
> + EX(lwc1 $f23, 184(a0))
> + EX(lwc1 $f24, 192(a0))
> + EX(lwc1 $f25, 200(a0))
> + EX(lwc1 $f26, 208(a0))
> + EX(lwc1 $f27, 216(a0))
> + EX(lwc1 $f28, 224(a0))
> + EX(lwc1 $f29, 232(a0))
> + EX(lwc1 $f30, 240(a0))
> + EX(lwc1 $f31, 248(a0))
> jr ra
> - ctc1 t0,fcr31
> + ctc1 t0, fcr31
> .set pop
> END(_restore_fp_context)
> .set reorder
> Index: linux-sfr-test/arch/mips/kernel/r6000_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r6000_fpu.S 2016-10-22
> 02:28:57.927876000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:29:12.415002000
> +0100 @@ -21,7 +21,14 @@
> .set push
> SET_HARDFLOAT
>
> - /* Save floating point context */
> +/**
> + * _save_fp_context() - save FP context from the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> + *
> + * Save FP context, including the 32 FP data registers and the FP
> + * control & status register, from the FPU to signal context.
> + */
> LEAF(_save_fp_context)
> mfc0 t0,CP0_STATUS
> sll t0,t0,2
> @@ -30,59 +37,59 @@
>
> cfc1 t1,fcr31
> /* Store the 16 double precision registers */
> - sdc1 $f0,(SC_FPREGS+0)(a0)
> - sdc1 $f2,(SC_FPREGS+16)(a0)
> - sdc1 $f4,(SC_FPREGS+32)(a0)
> - sdc1 $f6,(SC_FPREGS+48)(a0)
> - sdc1 $f8,(SC_FPREGS+64)(a0)
> - sdc1 $f10,(SC_FPREGS+80)(a0)
> - sdc1 $f12,(SC_FPREGS+96)(a0)
> - sdc1 $f14,(SC_FPREGS+112)(a0)
> - sdc1 $f16,(SC_FPREGS+128)(a0)
> - sdc1 $f18,(SC_FPREGS+144)(a0)
> - sdc1 $f20,(SC_FPREGS+160)(a0)
> - sdc1 $f22,(SC_FPREGS+176)(a0)
> - sdc1 $f24,(SC_FPREGS+192)(a0)
> - sdc1 $f26,(SC_FPREGS+208)(a0)
> - sdc1 $f28,(SC_FPREGS+224)(a0)
> - sdc1 $f30,(SC_FPREGS+240)(a0)
> + sdc1 $f0,0(a0)
> + sdc1 $f2,16(a0)
> + sdc1 $f4,32(a0)
> + sdc1 $f6,48(a0)
> + sdc1 $f8,64(a0)
> + sdc1 $f10,80(a0)
> + sdc1 $f12,96(a0)
> + sdc1 $f14,112(a0)
> + sdc1 $f16,128(a0)
> + sdc1 $f18,144(a0)
> + sdc1 $f20,160(a0)
> + sdc1 $f22,176(a0)
> + sdc1 $f24,192(a0)
> + sdc1 $f26,208(a0)
> + sdc1 $f28,224(a0)
> + sdc1 $f30,240(a0)
> jr ra
> - sw t0,SC_FPC_CSR(a0)
> + sw t0,(a1)
> 1: jr ra
> nop
> END(_save_fp_context)
>
> -/* Restore FPU state:
> - * - fp gp registers
> - * - cp1 status/control register
> +/**
> + * _restore_fp_context() - restore FP context to the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> *
> - * We base the decision which registers to restore from the signal stack
> - * frame on the current content of c0_status, not on the content of the
> - * stack frame which might have been changed by the user.
> + * Restore FP context, including the 32 FP data registers and the FP
> + * control & status register, from signal context to the FPU.
> */
> LEAF(_restore_fp_context)
> mfc0 t0,CP0_STATUS
> sll t0,t0,2
>
> bgez t0,1f
> - lw t0,SC_FPC_CSR(a0)
> + lw t0,(a1)
> /* Restore the 16 double precision registers */
> - ldc1 $f0,(SC_FPREGS+0)(a0)
> - ldc1 $f2,(SC_FPREGS+16)(a0)
> - ldc1 $f4,(SC_FPREGS+32)(a0)
> - ldc1 $f6,(SC_FPREGS+48)(a0)
> - ldc1 $f8,(SC_FPREGS+64)(a0)
> - ldc1 $f10,(SC_FPREGS+80)(a0)
> - ldc1 $f12,(SC_FPREGS+96)(a0)
> - ldc1 $f14,(SC_FPREGS+112)(a0)
> - ldc1 $f16,(SC_FPREGS+128)(a0)
> - ldc1 $f18,(SC_FPREGS+144)(a0)
> - ldc1 $f20,(SC_FPREGS+160)(a0)
> - ldc1 $f22,(SC_FPREGS+176)(a0)
> - ldc1 $f24,(SC_FPREGS+192)(a0)
> - ldc1 $f26,(SC_FPREGS+208)(a0)
> - ldc1 $f28,(SC_FPREGS+224)(a0)
> - ldc1 $f30,(SC_FPREGS+240)(a0)
> + ldc1 $f0,0(a0)
> + ldc1 $f2,16(a0)
> + ldc1 $f4,32(a0)
> + ldc1 $f6,48(a0)
> + ldc1 $f8,64(a0)
> + ldc1 $f10,80(a0)
> + ldc1 $f12,96(a0)
> + ldc1 $f14,112(a0)
> + ldc1 $f16,128(a0)
> + ldc1 $f18,144(a0)
> + ldc1 $f20,160(a0)
> + ldc1 $f22,176(a0)
> + ldc1 $f24,192(a0)
> + ldc1 $f26,208(a0)
> + ldc1 $f28,224(a0)
> + ldc1 $f30,240(a0)
> jr ra
> ctc1 t0,fcr31
> 1: jr ra
Hi Maciej,
Thanks for fixing that up:
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
BTW, do you have a feel for whether there's a good r2k/r3k platform (ideal
would be some software emulator if any are good enough) that we could hook up
to our continuous integration system? That would help us to catch any
regressions like this in future before they hit mainline.
Thanks,
Paul
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-11-01 9:31 ` Paul Burton
@ 2016-11-01 9:31 ` Paul Burton
2016-11-01 11:49 ` Maciej W. Rozycki
1 sibling, 0 replies; 16+ messages in thread
From: Paul Burton @ 2016-11-01 9:31 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Ralf Baechle, linux-mips, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 10482 bytes --]
On Monday, 31 October 2016 16:27:01 GMT Maciej W. Rozycki wrote:
> Fix a regression introduced with commit 2db9ca0a3551 ("MIPS: Use struct
> mips_abi offsets to save FP context") for MIPS I/I FP signal contexts,
> by converting save/restore code to the updated internal API. Start FGR
> offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than
> the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status
> Register (FCSR).
>
> Document the new internal API and adjust assembly code formatting for
> consistency.
>
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
> linux-mips-isa12-sig-fp-context-offsets.patch
> Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22
> 02:28:09.266462000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:29:01.523906000
> +0100 @@ -26,97 +26,104 @@
>
> .set noreorder
> .set mips1
> - /* Save floating point context */
> +
> +/**
> + * _save_fp_context() - save FP context from the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> + *
> + * Save FP context, including the 32 FP data registers and the FP
> + * control & status register, from the FPU to signal context.
> + */
> LEAF(_save_fp_context)
> .set push
> SET_HARDFLOAT
> li v0, 0 # assume success
> - cfc1 t1,fcr31
> - EX(swc1 $f0,(SC_FPREGS+0)(a0))
> - EX(swc1 $f1,(SC_FPREGS+8)(a0))
> - EX(swc1 $f2,(SC_FPREGS+16)(a0))
> - EX(swc1 $f3,(SC_FPREGS+24)(a0))
> - EX(swc1 $f4,(SC_FPREGS+32)(a0))
> - EX(swc1 $f5,(SC_FPREGS+40)(a0))
> - EX(swc1 $f6,(SC_FPREGS+48)(a0))
> - EX(swc1 $f7,(SC_FPREGS+56)(a0))
> - EX(swc1 $f8,(SC_FPREGS+64)(a0))
> - EX(swc1 $f9,(SC_FPREGS+72)(a0))
> - EX(swc1 $f10,(SC_FPREGS+80)(a0))
> - EX(swc1 $f11,(SC_FPREGS+88)(a0))
> - EX(swc1 $f12,(SC_FPREGS+96)(a0))
> - EX(swc1 $f13,(SC_FPREGS+104)(a0))
> - EX(swc1 $f14,(SC_FPREGS+112)(a0))
> - EX(swc1 $f15,(SC_FPREGS+120)(a0))
> - EX(swc1 $f16,(SC_FPREGS+128)(a0))
> - EX(swc1 $f17,(SC_FPREGS+136)(a0))
> - EX(swc1 $f18,(SC_FPREGS+144)(a0))
> - EX(swc1 $f19,(SC_FPREGS+152)(a0))
> - EX(swc1 $f20,(SC_FPREGS+160)(a0))
> - EX(swc1 $f21,(SC_FPREGS+168)(a0))
> - EX(swc1 $f22,(SC_FPREGS+176)(a0))
> - EX(swc1 $f23,(SC_FPREGS+184)(a0))
> - EX(swc1 $f24,(SC_FPREGS+192)(a0))
> - EX(swc1 $f25,(SC_FPREGS+200)(a0))
> - EX(swc1 $f26,(SC_FPREGS+208)(a0))
> - EX(swc1 $f27,(SC_FPREGS+216)(a0))
> - EX(swc1 $f28,(SC_FPREGS+224)(a0))
> - EX(swc1 $f29,(SC_FPREGS+232)(a0))
> - EX(swc1 $f30,(SC_FPREGS+240)(a0))
> - EX(swc1 $f31,(SC_FPREGS+248)(a0))
> + cfc1 t1, fcr31
> + EX(swc1 $f0, 0(a0))
> + EX(swc1 $f1, 8(a0))
> + EX(swc1 $f2, 16(a0))
> + EX(swc1 $f3, 24(a0))
> + EX(swc1 $f4, 32(a0))
> + EX(swc1 $f5, 40(a0))
> + EX(swc1 $f6, 48(a0))
> + EX(swc1 $f7, 56(a0))
> + EX(swc1 $f8, 64(a0))
> + EX(swc1 $f9, 72(a0))
> + EX(swc1 $f10, 80(a0))
> + EX(swc1 $f11, 88(a0))
> + EX(swc1 $f12, 96(a0))
> + EX(swc1 $f13, 104(a0))
> + EX(swc1 $f14, 112(a0))
> + EX(swc1 $f15, 120(a0))
> + EX(swc1 $f16, 128(a0))
> + EX(swc1 $f17, 136(a0))
> + EX(swc1 $f18, 144(a0))
> + EX(swc1 $f19, 152(a0))
> + EX(swc1 $f20, 160(a0))
> + EX(swc1 $f21, 168(a0))
> + EX(swc1 $f22, 176(a0))
> + EX(swc1 $f23, 184(a0))
> + EX(swc1 $f24, 192(a0))
> + EX(swc1 $f25, 200(a0))
> + EX(swc1 $f26, 208(a0))
> + EX(swc1 $f27, 216(a0))
> + EX(swc1 $f28, 224(a0))
> + EX(swc1 $f29, 232(a0))
> + EX(swc1 $f30, 240(a0))
> + EX(swc1 $f31, 248(a0))
> jr ra
> - EX(sw t1,(SC_FPC_CSR)(a0))
> + EX(sw t1, (a1))
> .set pop
> END(_save_fp_context)
>
> -/*
> - * Restore FPU state:
> - * - fp gp registers
> - * - cp1 status/control register
> +/**
> + * _restore_fp_context() - restore FP context to the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> *
> - * We base the decision which registers to restore from the signal stack
> - * frame on the current content of c0_status, not on the content of the
> - * stack frame which might have been changed by the user.
> + * Restore FP context, including the 32 FP data registers and the FP
> + * control & status register, from signal context to the FPU.
> */
> LEAF(_restore_fp_context)
> .set push
> SET_HARDFLOAT
> li v0, 0 # assume success
> - EX(lw t0,(SC_FPC_CSR)(a0))
> - EX(lwc1 $f0,(SC_FPREGS+0)(a0))
> - EX(lwc1 $f1,(SC_FPREGS+8)(a0))
> - EX(lwc1 $f2,(SC_FPREGS+16)(a0))
> - EX(lwc1 $f3,(SC_FPREGS+24)(a0))
> - EX(lwc1 $f4,(SC_FPREGS+32)(a0))
> - EX(lwc1 $f5,(SC_FPREGS+40)(a0))
> - EX(lwc1 $f6,(SC_FPREGS+48)(a0))
> - EX(lwc1 $f7,(SC_FPREGS+56)(a0))
> - EX(lwc1 $f8,(SC_FPREGS+64)(a0))
> - EX(lwc1 $f9,(SC_FPREGS+72)(a0))
> - EX(lwc1 $f10,(SC_FPREGS+80)(a0))
> - EX(lwc1 $f11,(SC_FPREGS+88)(a0))
> - EX(lwc1 $f12,(SC_FPREGS+96)(a0))
> - EX(lwc1 $f13,(SC_FPREGS+104)(a0))
> - EX(lwc1 $f14,(SC_FPREGS+112)(a0))
> - EX(lwc1 $f15,(SC_FPREGS+120)(a0))
> - EX(lwc1 $f16,(SC_FPREGS+128)(a0))
> - EX(lwc1 $f17,(SC_FPREGS+136)(a0))
> - EX(lwc1 $f18,(SC_FPREGS+144)(a0))
> - EX(lwc1 $f19,(SC_FPREGS+152)(a0))
> - EX(lwc1 $f20,(SC_FPREGS+160)(a0))
> - EX(lwc1 $f21,(SC_FPREGS+168)(a0))
> - EX(lwc1 $f22,(SC_FPREGS+176)(a0))
> - EX(lwc1 $f23,(SC_FPREGS+184)(a0))
> - EX(lwc1 $f24,(SC_FPREGS+192)(a0))
> - EX(lwc1 $f25,(SC_FPREGS+200)(a0))
> - EX(lwc1 $f26,(SC_FPREGS+208)(a0))
> - EX(lwc1 $f27,(SC_FPREGS+216)(a0))
> - EX(lwc1 $f28,(SC_FPREGS+224)(a0))
> - EX(lwc1 $f29,(SC_FPREGS+232)(a0))
> - EX(lwc1 $f30,(SC_FPREGS+240)(a0))
> - EX(lwc1 $f31,(SC_FPREGS+248)(a0))
> + EX(lw t0, (a1))
> + EX(lwc1 $f0, 0(a0))
> + EX(lwc1 $f1, 8(a0))
> + EX(lwc1 $f2, 16(a0))
> + EX(lwc1 $f3, 24(a0))
> + EX(lwc1 $f4, 32(a0))
> + EX(lwc1 $f5, 40(a0))
> + EX(lwc1 $f6, 48(a0))
> + EX(lwc1 $f7, 56(a0))
> + EX(lwc1 $f8, 64(a0))
> + EX(lwc1 $f9, 72(a0))
> + EX(lwc1 $f10, 80(a0))
> + EX(lwc1 $f11, 88(a0))
> + EX(lwc1 $f12, 96(a0))
> + EX(lwc1 $f13, 104(a0))
> + EX(lwc1 $f14, 112(a0))
> + EX(lwc1 $f15, 120(a0))
> + EX(lwc1 $f16, 128(a0))
> + EX(lwc1 $f17, 136(a0))
> + EX(lwc1 $f18, 144(a0))
> + EX(lwc1 $f19, 152(a0))
> + EX(lwc1 $f20, 160(a0))
> + EX(lwc1 $f21, 168(a0))
> + EX(lwc1 $f22, 176(a0))
> + EX(lwc1 $f23, 184(a0))
> + EX(lwc1 $f24, 192(a0))
> + EX(lwc1 $f25, 200(a0))
> + EX(lwc1 $f26, 208(a0))
> + EX(lwc1 $f27, 216(a0))
> + EX(lwc1 $f28, 224(a0))
> + EX(lwc1 $f29, 232(a0))
> + EX(lwc1 $f30, 240(a0))
> + EX(lwc1 $f31, 248(a0))
> jr ra
> - ctc1 t0,fcr31
> + ctc1 t0, fcr31
> .set pop
> END(_restore_fp_context)
> .set reorder
> Index: linux-sfr-test/arch/mips/kernel/r6000_fpu.S
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/r6000_fpu.S 2016-10-22
> 02:28:57.927876000 +0100 +++
> linux-sfr-test/arch/mips/kernel/r6000_fpu.S 2016-10-22 02:29:12.415002000
> +0100 @@ -21,7 +21,14 @@
> .set push
> SET_HARDFLOAT
>
> - /* Save floating point context */
> +/**
> + * _save_fp_context() - save FP context from the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> + *
> + * Save FP context, including the 32 FP data registers and the FP
> + * control & status register, from the FPU to signal context.
> + */
> LEAF(_save_fp_context)
> mfc0 t0,CP0_STATUS
> sll t0,t0,2
> @@ -30,59 +37,59 @@
>
> cfc1 t1,fcr31
> /* Store the 16 double precision registers */
> - sdc1 $f0,(SC_FPREGS+0)(a0)
> - sdc1 $f2,(SC_FPREGS+16)(a0)
> - sdc1 $f4,(SC_FPREGS+32)(a0)
> - sdc1 $f6,(SC_FPREGS+48)(a0)
> - sdc1 $f8,(SC_FPREGS+64)(a0)
> - sdc1 $f10,(SC_FPREGS+80)(a0)
> - sdc1 $f12,(SC_FPREGS+96)(a0)
> - sdc1 $f14,(SC_FPREGS+112)(a0)
> - sdc1 $f16,(SC_FPREGS+128)(a0)
> - sdc1 $f18,(SC_FPREGS+144)(a0)
> - sdc1 $f20,(SC_FPREGS+160)(a0)
> - sdc1 $f22,(SC_FPREGS+176)(a0)
> - sdc1 $f24,(SC_FPREGS+192)(a0)
> - sdc1 $f26,(SC_FPREGS+208)(a0)
> - sdc1 $f28,(SC_FPREGS+224)(a0)
> - sdc1 $f30,(SC_FPREGS+240)(a0)
> + sdc1 $f0,0(a0)
> + sdc1 $f2,16(a0)
> + sdc1 $f4,32(a0)
> + sdc1 $f6,48(a0)
> + sdc1 $f8,64(a0)
> + sdc1 $f10,80(a0)
> + sdc1 $f12,96(a0)
> + sdc1 $f14,112(a0)
> + sdc1 $f16,128(a0)
> + sdc1 $f18,144(a0)
> + sdc1 $f20,160(a0)
> + sdc1 $f22,176(a0)
> + sdc1 $f24,192(a0)
> + sdc1 $f26,208(a0)
> + sdc1 $f28,224(a0)
> + sdc1 $f30,240(a0)
> jr ra
> - sw t0,SC_FPC_CSR(a0)
> + sw t0,(a1)
> 1: jr ra
> nop
> END(_save_fp_context)
>
> -/* Restore FPU state:
> - * - fp gp registers
> - * - cp1 status/control register
> +/**
> + * _restore_fp_context() - restore FP context to the FPU
> + * @a0 - pointer to fpregs field of sigcontext
> + * @a1 - pointer to fpc_csr field of sigcontext
> *
> - * We base the decision which registers to restore from the signal stack
> - * frame on the current content of c0_status, not on the content of the
> - * stack frame which might have been changed by the user.
> + * Restore FP context, including the 32 FP data registers and the FP
> + * control & status register, from signal context to the FPU.
> */
> LEAF(_restore_fp_context)
> mfc0 t0,CP0_STATUS
> sll t0,t0,2
>
> bgez t0,1f
> - lw t0,SC_FPC_CSR(a0)
> + lw t0,(a1)
> /* Restore the 16 double precision registers */
> - ldc1 $f0,(SC_FPREGS+0)(a0)
> - ldc1 $f2,(SC_FPREGS+16)(a0)
> - ldc1 $f4,(SC_FPREGS+32)(a0)
> - ldc1 $f6,(SC_FPREGS+48)(a0)
> - ldc1 $f8,(SC_FPREGS+64)(a0)
> - ldc1 $f10,(SC_FPREGS+80)(a0)
> - ldc1 $f12,(SC_FPREGS+96)(a0)
> - ldc1 $f14,(SC_FPREGS+112)(a0)
> - ldc1 $f16,(SC_FPREGS+128)(a0)
> - ldc1 $f18,(SC_FPREGS+144)(a0)
> - ldc1 $f20,(SC_FPREGS+160)(a0)
> - ldc1 $f22,(SC_FPREGS+176)(a0)
> - ldc1 $f24,(SC_FPREGS+192)(a0)
> - ldc1 $f26,(SC_FPREGS+208)(a0)
> - ldc1 $f28,(SC_FPREGS+224)(a0)
> - ldc1 $f30,(SC_FPREGS+240)(a0)
> + ldc1 $f0,0(a0)
> + ldc1 $f2,16(a0)
> + ldc1 $f4,32(a0)
> + ldc1 $f6,48(a0)
> + ldc1 $f8,64(a0)
> + ldc1 $f10,80(a0)
> + ldc1 $f12,96(a0)
> + ldc1 $f14,112(a0)
> + ldc1 $f16,128(a0)
> + ldc1 $f18,144(a0)
> + ldc1 $f20,160(a0)
> + ldc1 $f22,176(a0)
> + ldc1 $f24,192(a0)
> + ldc1 $f26,208(a0)
> + ldc1 $f28,224(a0)
> + ldc1 $f30,240(a0)
> jr ra
> ctc1 t0,fcr31
> 1: jr ra
Hi Maciej,
Thanks for fixing that up:
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
BTW, do you have a feel for whether there's a good r2k/r3k platform (ideal
would be some software emulator if any are good enough) that we could hook up
to our continuous integration system? That would help us to catch any
regressions like this in future before they hit mainline.
Thanks,
Paul
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-11-01 9:31 ` Paul Burton
2016-11-01 9:31 ` Paul Burton
@ 2016-11-01 11:49 ` Maciej W. Rozycki
2016-11-01 11:49 ` Maciej W. Rozycki
1 sibling, 1 reply; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-11-01 11:49 UTC (permalink / raw)
To: Paul Burton; +Cc: Ralf Baechle, linux-mips, linux-kernel
On Tue, 1 Nov 2016, Paul Burton wrote:
> BTW, do you have a feel for whether there's a good r2k/r3k platform (ideal
> would be some software emulator if any are good enough) that we could hook up
> to our continuous integration system? That would help us to catch any
> regressions like this in future before they hit mainline.
I know about no such platform I'm afraid.
QEMU does not have the R2k/R3k exception/MMU/cache model and implementing
that would be a considerable effort I see no volunteers for. I haven't
heard of any other simulator which might be closer to implementing that
model.
As to using real hardware -- I might be the closest myself to be capable
of doing some automated testing as I have an R3k machine in my home lab
wired for remote control. It could track Ralf's `mips-for-linux-next'
branch and watch out for regressions, by trying to build and boot kernels
automatically on a regular basis; maybe doing some further validation
even, such as running GCC or glibc regression testing. But while the
target is ready I'm still missing the host-side setup, which I haven't
completed. I don't think there's any other hardware readily available
which could be hooked somewhere.
So for the time being I think we need to continue relying on people
spotting issues by hand. I think we've been doing pretty good overall.
Thanks for your review.
Maciej
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets
2016-11-01 11:49 ` Maciej W. Rozycki
@ 2016-11-01 11:49 ` Maciej W. Rozycki
0 siblings, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2016-11-01 11:49 UTC (permalink / raw)
To: Paul Burton; +Cc: Ralf Baechle, linux-mips, linux-kernel
On Tue, 1 Nov 2016, Paul Burton wrote:
> BTW, do you have a feel for whether there's a good r2k/r3k platform (ideal
> would be some software emulator if any are good enough) that we could hook up
> to our continuous integration system? That would help us to catch any
> regressions like this in future before they hit mainline.
I know about no such platform I'm afraid.
QEMU does not have the R2k/R3k exception/MMU/cache model and implementing
that would be a considerable effort I see no volunteers for. I haven't
heard of any other simulator which might be closer to implementing that
model.
As to using real hardware -- I might be the closest myself to be capable
of doing some automated testing as I have an R3k machine in my home lab
wired for remote control. It could track Ralf's `mips-for-linux-next'
branch and watch out for regressions, by trying to build and boot kernels
automatically on a regular basis; maybe doing some further validation
even, such as running GCC or glibc regression testing. But while the
target is ready I'm still missing the host-side setup, which I haven't
completed. I don't think there's any other hardware readily available
which could be hooked somewhere.
So for the time being I think we need to continue relying on people
spotting issues by hand. I think we've been doing pretty good overall.
Thanks for your review.
Maciej
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-11-01 11:50 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-31 16:24 [PATCH 0/4] MIPS I/II FP signal context handling fixes Maciej W. Rozycki
2016-10-31 16:24 ` Maciej W. Rozycki
2016-10-31 16:25 ` [PATCH 1/4] MIPS: Fix ISA I FP sigcontext access violation handling Maciej W. Rozycki
2016-10-31 16:25 ` Maciej W. Rozycki
2016-11-01 9:27 ` Paul Burton
2016-11-01 9:27 ` Paul Burton
2016-10-31 16:26 ` [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context Maciej W. Rozycki
2016-10-31 16:26 ` Maciej W. Rozycki
2016-10-31 16:27 ` [PATCH 3/4] MIPS: Fix ISA I/II FP signal context offsets Maciej W. Rozycki
2016-10-31 16:27 ` Maciej W. Rozycki
2016-11-01 9:31 ` Paul Burton
2016-11-01 9:31 ` Paul Burton
2016-11-01 11:49 ` Maciej W. Rozycki
2016-11-01 11:49 ` Maciej W. Rozycki
2016-10-31 16:27 ` [PATCH 4/4] MIPS: Correct MIPS I FP sigcontext layout Maciej W. Rozycki
2016-10-31 16:27 ` Maciej W. Rozycki
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