From: Paul Burton <paul.burton@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <marc.zyngier@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH 1/5] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
Date: Thu, 30 Mar 2017 12:06:09 -0700 [thread overview]
Message-ID: <20170330190614.14844-2-paul.burton@imgtec.com> (raw)
In-Reply-To: <20170330190614.14844-1-paul.burton@imgtec.com>
Replace use of the magic number 0x100 (ie. bit 8) with the more
explanatory IE_SW0 (ie. interrupt enable for software interrupt 0) or
C_SW0 (ie. cause bit for software interrupt 0) as appropriate.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
drivers/irqchip/irq-mips-cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 8c504f562e9d..e6b413669e57 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -41,13 +41,13 @@
static inline void unmask_mips_irq(struct irq_data *d)
{
- set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_enable_hazard();
}
static inline void mask_mips_irq(struct irq_data *d)
{
- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard();
}
@@ -70,7 +70,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
unmask_mips_irq(d);
return 0;
@@ -83,7 +83,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
static void mips_mt_cpu_irq_ack(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
mask_mips_irq(d);
}
--
2.12.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <marc.zyngier@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH 1/5] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
Date: Thu, 30 Mar 2017 12:06:09 -0700 [thread overview]
Message-ID: <20170330190614.14844-2-paul.burton@imgtec.com> (raw)
Message-ID: <20170330190609.8qsJBAVZrr39jAOLC0yEr0DeOoiBMQREZVcQVS5Ttqk@z> (raw)
In-Reply-To: <20170330190614.14844-1-paul.burton@imgtec.com>
Replace use of the magic number 0x100 (ie. bit 8) with the more
explanatory IE_SW0 (ie. interrupt enable for software interrupt 0) or
C_SW0 (ie. cause bit for software interrupt 0) as appropriate.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
drivers/irqchip/irq-mips-cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 8c504f562e9d..e6b413669e57 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -41,13 +41,13 @@
static inline void unmask_mips_irq(struct irq_data *d)
{
- set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_enable_hazard();
}
static inline void mask_mips_irq(struct irq_data *d)
{
- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard();
}
@@ -70,7 +70,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
unmask_mips_irq(d);
return 0;
@@ -83,7 +83,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
static void mips_mt_cpu_irq_ack(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
mask_mips_irq(d);
}
--
2.12.1
next prev parent reply other threads:[~2017-03-30 19:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-30 19:06 [PATCH 0/5] MIPS/irqchip: Use IPI IRQ domains for CPU interrupt controller IPIs Paul Burton
2017-03-30 19:06 ` Paul Burton
2017-03-30 19:06 ` Paul Burton [this message]
2017-03-30 19:06 ` [PATCH 1/5] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 Paul Burton
2017-03-30 19:06 ` [PATCH 2/5] irqchip: mips-cpu: Prepare for non-legacy IRQ domains Paul Burton
2017-03-30 19:06 ` Paul Burton
2017-03-30 19:06 ` [PATCH 3/5] irqchip: mips-cpu: Introduce IPI IRQ domain support Paul Burton
2017-03-30 19:06 ` Paul Burton
2017-03-30 19:06 ` [PATCH 4/5] MIPS: smp-mt: Use CPU interrupt controller " Paul Burton
2017-03-30 19:06 ` Paul Burton
2017-03-30 19:06 ` [PATCH 5/5] MIPS: Stengthen IPI IRQ domain sanity check Paul Burton
2017-03-30 19:06 ` Paul Burton
2017-03-31 9:02 ` [PATCH 0/5] MIPS/irqchip: Use IPI IRQ domains for CPU interrupt controller IPIs Thomas Gleixner
2017-04-12 21:14 ` Ralf Baechle
2017-03-31 21:31 ` Joshua Kinard
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