From: Paul Burton <paul.burton@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>, Jason Cooper <jason@lakedaemon.net>, Paul Burton <paul.burton@imgtec.com> Subject: [PATCH 2/5] irqchip: mips-cpu: Prepare for non-legacy IRQ domains Date: Thu, 30 Mar 2017 12:06:10 -0700 [thread overview] Message-ID: <20170330190614.14844-3-paul.burton@imgtec.com> (raw) In-Reply-To: <20170330190614.14844-1-paul.burton@imgtec.com> The various struct irq_chip callbacks in the MIPS CPU interrupt controller driver have been calculating the hardware interrupt number by subtracting MIPS_CPU_IRQ_BASE from the virq number. This presumes a linear mapping beginning from MIPS_CPU_IRQ_BASE, and this will not hold once an IPI IRQ domain is introduced. Switch to using the hwirq field of struct irq_data which already contains the hardware interrupt number instead of attempting to calculate it. Similarly, plat_irq_dispatch calculated the virq number by adding MIPS_CPU_IRQ_BASE to the hardware interrupt number. Ready this for the introduction of an IPI IRQ domain by instead using irq_linear_revmap. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index e6b413669e57..338de924b269 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -39,15 +39,17 @@ #include <asm/mipsmtregs.h> #include <asm/setup.h> +static struct irq_domain *irq_domain; + static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(IE_SW0 << d->hwirq); irq_enable_hazard(); } static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(IE_SW0 << d->hwirq); irq_disable_hazard(); } @@ -70,7 +72,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << d->hwirq); evpe(vpflags); unmask_mips_irq(d); return 0; @@ -83,7 +85,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << d->hwirq); evpe(vpflags); mask_mips_irq(d); } @@ -103,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = { asmlinkage void __weak plat_irq_dispatch(void) { unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; + unsigned int virq; int irq; if (!pending) { @@ -113,7 +116,8 @@ asmlinkage void __weak plat_irq_dispatch(void) pending >>= CAUSEB_IP; while (pending) { irq = fls(pending) - 1; - do_IRQ(MIPS_CPU_IRQ_BASE + irq); + virq = irq_linear_revmap(irq_domain, irq); + do_IRQ(virq); pending &= ~BIT(irq); } } @@ -145,15 +149,14 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = { static void __init __mips_cpu_irq_init(struct device_node *of_node) { - struct irq_domain *domain; - /* Mask interrupts. */ clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, - &mips_cpu_intc_irq_domain_ops, NULL); - if (!domain) + irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + &mips_cpu_intc_irq_domain_ops, + NULL); + if (!irq_domain) panic("Failed to add irqdomain for MIPS CPU"); } -- 2.12.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com> To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>, Jason Cooper <jason@lakedaemon.net>, Paul Burton <paul.burton@imgtec.com> Subject: [PATCH 2/5] irqchip: mips-cpu: Prepare for non-legacy IRQ domains Date: Thu, 30 Mar 2017 12:06:10 -0700 [thread overview] Message-ID: <20170330190614.14844-3-paul.burton@imgtec.com> (raw) Message-ID: <20170330190610.3VtiktsVzaVcGS_r7e0WJqdc6zY83kT61usjUtaLx-s@z> (raw) In-Reply-To: <20170330190614.14844-1-paul.burton@imgtec.com> The various struct irq_chip callbacks in the MIPS CPU interrupt controller driver have been calculating the hardware interrupt number by subtracting MIPS_CPU_IRQ_BASE from the virq number. This presumes a linear mapping beginning from MIPS_CPU_IRQ_BASE, and this will not hold once an IPI IRQ domain is introduced. Switch to using the hwirq field of struct irq_data which already contains the hardware interrupt number instead of attempting to calculate it. Similarly, plat_irq_dispatch calculated the virq number by adding MIPS_CPU_IRQ_BASE to the hardware interrupt number. Ready this for the introduction of an IPI IRQ domain by instead using irq_linear_revmap. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index e6b413669e57..338de924b269 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -39,15 +39,17 @@ #include <asm/mipsmtregs.h> #include <asm/setup.h> +static struct irq_domain *irq_domain; + static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(IE_SW0 << d->hwirq); irq_enable_hazard(); } static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(IE_SW0 << d->hwirq); irq_disable_hazard(); } @@ -70,7 +72,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << d->hwirq); evpe(vpflags); unmask_mips_irq(d); return 0; @@ -83,7 +85,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << d->hwirq); evpe(vpflags); mask_mips_irq(d); } @@ -103,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = { asmlinkage void __weak plat_irq_dispatch(void) { unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; + unsigned int virq; int irq; if (!pending) { @@ -113,7 +116,8 @@ asmlinkage void __weak plat_irq_dispatch(void) pending >>= CAUSEB_IP; while (pending) { irq = fls(pending) - 1; - do_IRQ(MIPS_CPU_IRQ_BASE + irq); + virq = irq_linear_revmap(irq_domain, irq); + do_IRQ(virq); pending &= ~BIT(irq); } } @@ -145,15 +149,14 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = { static void __init __mips_cpu_irq_init(struct device_node *of_node) { - struct irq_domain *domain; - /* Mask interrupts. */ clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, - &mips_cpu_intc_irq_domain_ops, NULL); - if (!domain) + irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + &mips_cpu_intc_irq_domain_ops, + NULL); + if (!irq_domain) panic("Failed to add irqdomain for MIPS CPU"); } -- 2.12.1
next prev parent reply other threads:[~2017-03-30 19:07 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-30 19:06 [PATCH 0/5] MIPS/irqchip: Use IPI IRQ domains for CPU interrupt controller IPIs Paul Burton 2017-03-30 19:06 ` Paul Burton 2017-03-30 19:06 ` [PATCH 1/5] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 Paul Burton 2017-03-30 19:06 ` Paul Burton 2017-03-30 19:06 ` Paul Burton [this message] 2017-03-30 19:06 ` [PATCH 2/5] irqchip: mips-cpu: Prepare for non-legacy IRQ domains Paul Burton 2017-03-30 19:06 ` [PATCH 3/5] irqchip: mips-cpu: Introduce IPI IRQ domain support Paul Burton 2017-03-30 19:06 ` Paul Burton 2017-03-30 19:06 ` [PATCH 4/5] MIPS: smp-mt: Use CPU interrupt controller " Paul Burton 2017-03-30 19:06 ` Paul Burton 2017-03-30 19:06 ` [PATCH 5/5] MIPS: Stengthen IPI IRQ domain sanity check Paul Burton 2017-03-30 19:06 ` Paul Burton 2017-03-31 9:02 ` [PATCH 0/5] MIPS/irqchip: Use IPI IRQ domains for CPU interrupt controller IPIs Thomas Gleixner 2017-04-12 21:14 ` Ralf Baechle 2017-03-31 21:31 ` Joshua Kinard
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