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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Huacai Chen <chenhc@lemote.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org, Fuxin Zhang <zhangfx@lemote.com>,
	Huacai Chen <chenhuacai@gmail.com>
Subject: Re: [PATCH 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler
Date: Wed, 29 Jul 2020 13:33:13 +0800	[thread overview]
Message-ID: <4b1c4634-341d-352c-95ac-9a26f9e2fbcf@flygoat.com> (raw)
In-Reply-To: <1596000130-8689-5-git-send-email-chenhc@lemote.com>



在 2020/7/29 13:22, Huacai Chen 写道:
> Loongson PCH PIC is a standard level triggered PIC, and it need to clear
> interrupt during unmask.

I had tested the driver with LS7A internal devices and it works.
But there are some reports that the driver is missing interrupts from
external PCIe slots.

Your patch solved that. Although according to the manual it should be a
fasteoi intc.......

Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
>   drivers/irqchip/irq-loongson-pch-pic.c | 15 ++++-----------
>   1 file changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
> index 2a05b93..61d06df 100644
> --- a/drivers/irqchip/irq-loongson-pch-pic.c
> +++ b/drivers/irqchip/irq-loongson-pch-pic.c
> @@ -64,15 +64,6 @@ static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit)
>   	raw_spin_unlock(&priv->pic_lock);
>   }
>   
> -static void pch_pic_eoi_irq(struct irq_data *d)
> -{
> -	u32 idx = PIC_REG_IDX(d->hwirq);
> -	struct pch_pic *priv = irq_data_get_irq_chip_data(d);
> -
> -	writel(BIT(PIC_REG_BIT(d->hwirq)),
> -			priv->base + PCH_PIC_CLR + idx * 4);
> -}
> -
>   static void pch_pic_mask_irq(struct irq_data *d)
>   {
>   	struct pch_pic *priv = irq_data_get_irq_chip_data(d);
> @@ -85,6 +76,9 @@ static void pch_pic_unmask_irq(struct irq_data *d)
>   {
>   	struct pch_pic *priv = irq_data_get_irq_chip_data(d);
>   
> +	writel(BIT(PIC_REG_BIT(d->hwirq)),
> +			priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4);
> +
>   	irq_chip_unmask_parent(d);
>   	pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);
>   }
> @@ -124,7 +118,6 @@ static struct irq_chip pch_pic_irq_chip = {
>   	.irq_mask		= pch_pic_mask_irq,
>   	.irq_unmask		= pch_pic_unmask_irq,
>   	.irq_ack		= irq_chip_ack_parent,
> -	.irq_eoi		= pch_pic_eoi_irq,
>   	.irq_set_affinity	= irq_chip_set_affinity_parent,
>   	.irq_set_type		= pch_pic_set_type,
>   };
> @@ -150,7 +143,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>   
>   	irq_domain_set_info(domain, virq, hwirq,
>   			    &pch_pic_irq_chip, priv,
> -			    handle_fasteoi_ack_irq, NULL, NULL);
> +			    handle_level_irq, NULL, NULL);
>   	irq_set_probe(virq);
>   
>   	return 0;

  reply	other threads:[~2020-07-29  5:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29  5:22 [PATCH 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Huacai Chen
2020-07-29  5:22 ` [PATCH 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Huacai Chen
2020-07-29  5:22 ` [PATCH 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache Huacai Chen
2020-07-29  5:26   ` Jiaxun Yang
2020-07-29 15:04     ` Marc Zyngier
2020-07-30  1:16       ` Huacai Chen
2020-07-29  5:22 ` [PATCH 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors Huacai Chen
2020-07-29  5:27   ` Jiaxun Yang
2020-07-29  5:22 ` [PATCH 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler Huacai Chen
2020-07-29  5:33   ` Jiaxun Yang [this message]
2020-07-29  5:25 ` [PATCH 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Jiaxun Yang

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