From: Paul Cercueil <paul@crapouillou.net>
To: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Paul Boddie <paul@boddie.org.uk>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Kees Cook <keescook@chromium.org>,
"Eric W. Biederman" <ebiederm@xmission.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Neil Armstrong <narmstrong@baylibre.com>,
Robert Foss <robert.foss@linaro.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Ezequiel Garcia <ezequiel@collabora.com>,
Harry Wentland <harry.wentland@amd.com>,
Sam Ravnborg <sam@ravnborg.org>,
Maxime Ripard <maxime@cerno.tech>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@vger.kernel.org>,
linux-mips <linux-mips@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Discussions about the Letux Kernel
<letux-kernel@openphoenux.org>, Jon as Karlman <jonas@kwiboo.se>,
dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers
Date: Tue, 09 Nov 2021 20:36:06 +0000 [thread overview]
Message-ID: <6WNB2R.GJ2KT1BB7QOY1@crapouillou.net> (raw)
In-Reply-To: <BF6CBFFA-E8AA-4CCE-A587-4D5D647DEC64@goldelico.com>
Hi Nikolaus,
Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller
<hns@goldelico.com> a écrit :
> Hi Paul,
>
>> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <paul@crapouillou.net>:
>>
>>> 6. Therefore I think it *may* work overclocked with 48MHz
>>> but is not guaranteed or reliable above 27 MHz.
>>> So everything is ok here.
>>
>> One thing though - the "assigned-clocks" and
>> "assigned-clock-rates", while it works here, should be moved to the
>> CGU node, to respect the YAML schemas.
>
> Trying to do this seems to break boot.
>
> I can boot up to
>
> [ 8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare
> HDMI I2C bus driver
>
> and
>
> [ 11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for
> 13050000.lcdc0 on minor 0
>
> but then the boot process becomes slow and hangs. Last sign of
> activity is
>
> [ 19.347659] hub 1-0:1.0: USB hub found
> [ 19.353478] hub 1-0:1.0: 1 port detected
> [ 32.321760] wlan0_power: disabling
>
> What I did was to just move
>
> assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
> assigned-clock-rates = <27000000>;
>
> from
>
> hdmi: hdmi@10180000 {
>
> to
>
> cgu: jz4780-cgu@10000000 {
>
> Does this mean the clock is assigned too early or too late?
>
> Do you have any suggestions since I don't know the details of CGU.
These properties are already set for the CGU node in ci20.dts:
&cgu {
/*
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
assigned-clock-rates = <48000000>;
};
So you want to update these properties to add the HDMI clock setting,
like this:
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
<&cgu JZ4780_CLK_HDMI>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
assigned-clock-rates = <48000000>, <0>, <27000000>;
Cheers,
-Paul
next prev parent reply other threads:[~2021-11-09 20:36 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-05 12:29 [PATCH v5 0/7] MIPS: JZ4780 and CI20 HDMI H. Nikolaus Schaller
2021-10-05 12:29 ` [PATCH v5 1/7] drm/ingenic: Fix drm_init error path if IPU was registered H. Nikolaus Schaller
2021-10-05 12:29 ` [PATCH v5 2/7] drm/ingenic: Add support for JZ4780 and HDMI output H. Nikolaus Schaller
2021-10-05 20:22 ` Paul Cercueil
[not found] ` <7CEBB741-2218-40A7-9800-B3A154895274@goldelico.com>
2021-11-07 19:01 ` Paul Cercueil
2021-11-07 20:25 ` H. Nikolaus Schaller
2021-11-08 9:37 ` Paul Cercueil
2021-11-08 10:52 ` H. Nikolaus Schaller
2021-11-08 12:20 ` Paul Cercueil
2021-11-08 15:29 ` H. Nikolaus Schaller
2021-11-08 16:30 ` Paul Cercueil
2021-11-08 17:22 ` H. Nikolaus Schaller
2021-11-08 17:49 ` Paul Cercueil
2021-11-08 18:33 ` H. Nikolaus Schaller
2021-11-08 18:53 ` Paul Cercueil
2021-12-22 14:03 ` H. Nikolaus Schaller
2022-01-18 14:50 ` H. Nikolaus Schaller
2022-01-18 16:58 ` Paul Cercueil
2022-01-18 17:14 ` H. Nikolaus Schaller
[not found] ` <13356060.GkHXLIg068@jason>
2022-01-19 6:40 ` H. Nikolaus Schaller
2022-01-19 20:04 ` Paul Boddie
2021-10-05 12:29 ` [PATCH v5 3/7] dt-bindings: display: Add ingenic,jz4780-dw-hdmi DT Schema H. Nikolaus Schaller
2021-10-05 20:43 ` Paul Cercueil
2021-11-07 13:43 ` H. Nikolaus Schaller
2021-11-07 19:03 ` Paul Cercueil
2021-10-05 22:45 ` Rob Herring
2021-10-05 12:29 ` [PATCH v5 4/7] drm/ingenic: Add dw-hdmi driver for jz4780 H. Nikolaus Schaller
2021-10-05 12:29 ` [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers H. Nikolaus Schaller
2021-10-05 20:50 ` Paul Cercueil
2021-10-05 21:44 ` Paul Boddie
2021-10-05 21:52 ` Paul Cercueil
2021-11-07 13:45 ` H. Nikolaus Schaller
2021-11-07 19:05 ` Paul Cercueil
2021-11-09 20:19 ` H. Nikolaus Schaller
2021-11-09 20:36 ` Paul Cercueil [this message]
2021-11-09 20:42 ` H. Nikolaus Schaller
2021-11-09 21:14 ` [Letux-kernel] " H. Nikolaus Schaller
2021-10-05 12:29 ` [PATCH v5 6/7] MIPS: DTS: CI20: Add DT nodes for HDMI setup H. Nikolaus Schaller
2021-10-05 12:29 ` [PATCH v5 7/7] MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 H. Nikolaus Schaller
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