* [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash
@ 2020-08-15 16:35 Hauke Mehrtens
2020-08-15 16:35 ` [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN Hauke Mehrtens
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Hauke Mehrtens @ 2020-08-15 16:35 UTC (permalink / raw)
To: tsbogend
Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89,
wigyori, Hauke Mehrtens
Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree.
The NAND flash chip is connected with quad SPI, but reading currently
fails in quad SPI mode.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts
index bf69da96dc8b..ea11a21b133b 100644
--- a/arch/mips/boot/dts/img/pistachio_marduk.dts
+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
@@ -88,6 +88,12 @@
reg = <0>;
spi-max-frequency = <50000000>;
};
+
+ flash@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ };
};
&uart0 {
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN 2020-08-15 16:35 [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Hauke Mehrtens @ 2020-08-15 16:35 ` Hauke Mehrtens 2020-08-16 9:14 ` Sergei Shtylyov 2020-08-15 16:35 ` [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW Hauke Mehrtens 2020-09-03 20:40 ` [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Rahul Bedarkar 2 siblings, 1 reply; 8+ messages in thread From: Hauke Mehrtens @ 2020-08-15 16:35 UTC (permalink / raw) To: tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori, Hauke Mehrtens Add Cascoda CA8210 6LoWPAN controller to device tree. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> --- arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts index ea11a21b133b..633a41954cc0 100644 --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts @@ -75,6 +75,28 @@ VDD-supply = <&internal_dac_supply>; }; +&spfi0 { + status = "okay"; + pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; + pinctrl-names = "default"; + + cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>, + <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; + + ca8210: ca8210@0 { + status = "okay"; + compatible = "cascoda,ca8210"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-cpol; + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + extclock-enable; + extclock-freq = <16000000>; + extclock-gpio = <2>; + }; +}; + &spfi1 { status = "okay"; -- 2.20.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN 2020-08-15 16:35 ` [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN Hauke Mehrtens @ 2020-08-16 9:14 ` Sergei Shtylyov 2020-08-16 10:59 ` Hauke Mehrtens 0 siblings, 1 reply; 8+ messages in thread From: Sergei Shtylyov @ 2020-08-16 9:14 UTC (permalink / raw) To: Hauke Mehrtens, tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori Hello! On 15.08.2020 19:35, Hauke Mehrtens wrote: > Add Cascoda CA8210 6LoWPAN controller to device tree. > > Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> > --- > arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts > index ea11a21b133b..633a41954cc0 100644 > --- a/arch/mips/boot/dts/img/pistachio_marduk.dts > +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts > @@ -75,6 +75,28 @@ > VDD-supply = <&internal_dac_supply>; > }; > > +&spfi0 { > + status = "okay"; > + pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; > + pinctrl-names = "default"; > + > + cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>, > + <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; > + > + ca8210: ca8210@0 { The device nodes are supposed to have the generic names... > + status = "okay"; > + compatible = "cascoda,ca8210"; > + reg = <0>; > + spi-max-frequency = <4000000>; Only 4MHz? > + spi-cpol; > + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; > + irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; > + extclock-enable; > + extclock-freq = <16000000>; > + extclock-gpio = <2>; Hm, strange spec for a GPIO prop, shouldn't they all be alike? > + }; > +}; > + > &spfi1 { > status = "okay"; > MBR, Sergei ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN 2020-08-16 9:14 ` Sergei Shtylyov @ 2020-08-16 10:59 ` Hauke Mehrtens 2020-08-16 17:06 ` Sergei Shtylyov 0 siblings, 1 reply; 8+ messages in thread From: Hauke Mehrtens @ 2020-08-16 10:59 UTC (permalink / raw) To: Sergei Shtylyov, tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori [-- Attachment #1.1: Type: text/plain, Size: 2968 bytes --] On 8/16/20 11:14 AM, Sergei Shtylyov wrote: > Hello! Thank you for the review Sergei. > On 15.08.2020 19:35, Hauke Mehrtens wrote: > >> Add Cascoda CA8210 6LoWPAN controller to device tree. >> >> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> >> --- >> arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts >> b/arch/mips/boot/dts/img/pistachio_marduk.dts >> index ea11a21b133b..633a41954cc0 100644 >> --- a/arch/mips/boot/dts/img/pistachio_marduk.dts >> +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts >> @@ -75,6 +75,28 @@ >> VDD-supply = <&internal_dac_supply>; >> }; >> +&spfi0 { >> + status = "okay"; >> + pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, >> <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; >> + pinctrl-names = "default"; >> + >> + cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 >> GPIO_ACTIVE_HIGH>, >> + <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; >> + >> + ca8210: ca8210@0 { > > The device nodes are supposed to have the generic names... I am not referencing this, so I can also remove it: ca8210@0 { Otherwise, would this be ok: ieee802154: ca8210@0 { >> + status = "okay"; This status = "okay"; can be removed. >> + compatible = "cascoda,ca8210"; >> + reg = <0>; >> + spi-max-frequency = <4000000>; > > Only 4MHz? The vendor device tree also use 4MHz: https://github.com/CreatorDev/openwrt/blob/ci40/target/linux/pistachio/dts/pistachio/pistachio_marduk.dts#L34 The device tree binding says "Maximum clock speed, should be *less than* 4000000", it could even make sense to switch this to 3MHz. https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt I do not have the datasheet for the cascoda,ca8210. >> + spi-cpol; >> + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; >> + irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; >> + extclock-enable; >> + extclock-freq = <16000000>; >> + extclock-gpio = <2>; > > Hm, strange spec for a GPIO prop, shouldn't they all be alike? I am also getting this compile warning: arch/mips/boot/dts/img/pistachio_marduk.dts:135.3-23: Warning (gpios_property): /spi@18100f00/ca8210@0:extclock-gpio: cell 0 is not a phandle reference arch/mips/boot/dts/img/pistachio_marduk.dts:126.19-136.4: Warning (gpios_property): /spi@18100f00/ca8210@0: Missing property '#gpio-cells' in node /clk@18144000 or bad phandle (referred from extclock-gpio[0]) I do not know how to fix this. The binding is defined here: https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt Hauke [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN 2020-08-16 10:59 ` Hauke Mehrtens @ 2020-08-16 17:06 ` Sergei Shtylyov 0 siblings, 0 replies; 8+ messages in thread From: Sergei Shtylyov @ 2020-08-16 17:06 UTC (permalink / raw) To: Hauke Mehrtens, tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori On 8/16/20 1:59 PM, Hauke Mehrtens wrote: > Thank you for the review Sergei. You're welcome. :-) [...] >>> Add Cascoda CA8210 6LoWPAN controller to device tree. >>> >>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> >>> --- >>> arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ >>> 1 file changed, 22 insertions(+) >>> >>> diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts >>> b/arch/mips/boot/dts/img/pistachio_marduk.dts >>> index ea11a21b133b..633a41954cc0 100644 >>> --- a/arch/mips/boot/dts/img/pistachio_marduk.dts >>> +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts >>> @@ -75,6 +75,28 @@ >>> VDD-supply = <&internal_dac_supply>; >>> }; >>> +&spfi0 { >>> + status = "okay"; >>> + pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, >>> <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; >>> + pinctrl-names = "default"; >>> + >>> + cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 >>> GPIO_ACTIVE_HIGH>, >>> + <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; >>> + >>> + ca8210: ca8210@0 { >> >> The device nodes are supposed to have the generic names... > > I am not referencing this, so I can also remove it: > ca8210@0 { I said name, not label. :-) > Otherwise, would this be ok: > ieee802154: ca8210@0 { > >>> + status = "okay"; > > This status = "okay"; can be removed. Yes, and probably even shpould be removed... >>> + compatible = "cascoda,ca8210"; >>> + reg = <0>; >>> + spi-max-frequency = <4000000>; >> >> Only 4MHz? > > The vendor device tree also use 4MHz: > https://github.com/CreatorDev/openwrt/blob/ci40/target/linux/pistachio/dts/pistachio/pistachio_marduk.dts#L34 > The device tree binding says "Maximum clock speed, should be *less than* > 4000000", it could even make sense to switch this to 3MHz. > https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt It just sounds too low SPI frequency, those a usually one order higher... > I do not have the datasheet for the cascoda,ca8210. > >>> + spi-cpol; >>> + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; >>> + irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; >>> + extclock-enable; >>> + extclock-freq = <16000000>; >>> + extclock-gpio = <2>; >> >> Hm, strange spec for a GPIO prop, shouldn't they all be alike? > > I am also getting this compile warning: > arch/mips/boot/dts/img/pistachio_marduk.dts:135.3-23: Warning > (gpios_property): /spi@18100f00/ca8210@0:extclock-gpio: cell 0 is not a > phandle reference > arch/mips/boot/dts/img/pistachio_marduk.dts:126.19-136.4: Warning > (gpios_property): /spi@18100f00/ca8210@0: Missing property '#gpio-cells' > in node /clk@18144000 or bad phandle (referred from extclock-gpio[0]) Expected. :-) > I do not know how to fix this. > The binding is defined here: > https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt Have to fix the bindings somehow, "extclock-gpio" was a bad name... > Hauke MBR, Sergei ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW 2020-08-15 16:35 [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Hauke Mehrtens 2020-08-15 16:35 ` [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN Hauke Mehrtens @ 2020-08-15 16:35 ` Hauke Mehrtens 2020-09-12 6:46 ` Zhou Yanjie 2020-09-03 20:40 ` [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Rahul Bedarkar 2 siblings, 1 reply; 8+ messages in thread From: Hauke Mehrtens @ 2020-08-15 16:35 UTC (permalink / raw) To: tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori, Hauke Mehrtens Add NXP SC16IS752IPW SPI-UART controller to device tree. This controller drives 2 UARTs and 7 LEDs on the board. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> --- arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts index 633a41954cc0..f4965a484b72 100644 --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts @@ -46,6 +46,46 @@ regulator-max-microvolt = <1800000>; }; + /* EXT clock from ca8210 is fed to sc16is752 */ + ca8210_ext_clk: ca8210-ext-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "ca8210_ext_clock"; + }; + + gpioleds { + compatible = "gpio-leds"; + user1 { + label = "marduk:red:user1"; + gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>; + }; + user2 { + label = "marduk:red:user2"; + gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>; + }; + user3 { + label = "marduk:red:user3"; + gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>; + }; + user4 { + label = "marduk:red:user4"; + gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>; + }; + user5 { + label = "marduk:red:user5"; + gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>; + }; + user6 { + label = "marduk:red:user6"; + gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>; + }; + user7 { + label = "marduk:red:user7"; + gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>; + }; + }; + leds { compatible = "pwm-leds"; heartbeat { @@ -95,6 +135,17 @@ extclock-freq = <16000000>; extclock-gpio = <2>; }; + + sc16is752: sc16is752@1 { + compatible = "nxp,sc16is752"; + reg = <1>; + clocks = <&ca8210_ext_clk>; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; }; &spfi1 { -- 2.20.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW 2020-08-15 16:35 ` [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW Hauke Mehrtens @ 2020-09-12 6:46 ` Zhou Yanjie 0 siblings, 0 replies; 8+ messages in thread From: Zhou Yanjie @ 2020-09-12 6:46 UTC (permalink / raw) To: Hauke Mehrtens, tsbogend Cc: linux-mips, devicetree, robh+dt, james.hartley, rahulbedarkar89, wigyori Hello Hauke, I would like to ask how to write UART nodes of SC16IS752, our CU1000-Neo board also uses SC16IS752 to expand GPIOs and UARTs, and the bluetooth module (from AP6212A) is connected to UART expanded by SC16IS752, but I don't know how to write UART node, so bluetooth cannot be used normally at present. Thanks and best regards！ 在 2020/8/16 上午12:35, Hauke Mehrtens 写道: > Add NXP SC16IS752IPW SPI-UART controller to device tree. > > This controller drives 2 UARTs and 7 LEDs on the board. > > Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> > --- > arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts > index 633a41954cc0..f4965a484b72 100644 > --- a/arch/mips/boot/dts/img/pistachio_marduk.dts > +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts > @@ -46,6 +46,46 @@ > regulator-max-microvolt = <1800000>; > }; > > + /* EXT clock from ca8210 is fed to sc16is752 */ > + ca8210_ext_clk: ca8210-ext-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <16000000>; > + clock-output-names = "ca8210_ext_clock"; > + }; > + > + gpioleds { > + compatible = "gpio-leds"; > + user1 { > + label = "marduk:red:user1"; > + gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>; > + }; > + user2 { > + label = "marduk:red:user2"; > + gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>; > + }; > + user3 { > + label = "marduk:red:user3"; > + gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>; > + }; > + user4 { > + label = "marduk:red:user4"; > + gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>; > + }; > + user5 { > + label = "marduk:red:user5"; > + gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>; > + }; > + user6 { > + label = "marduk:red:user6"; > + gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>; > + }; > + user7 { > + label = "marduk:red:user7"; > + gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>; > + }; > + }; > + > leds { > compatible = "pwm-leds"; > heartbeat { > @@ -95,6 +135,17 @@ > extclock-freq = <16000000>; > extclock-gpio = <2>; > }; > + > + sc16is752: sc16is752@1 { > + compatible = "nxp,sc16is752"; > + reg = <1>; > + clocks = <&ca8210_ext_clk>; > + spi-max-frequency = <4000000>; > + interrupt-parent = <&gpio0>; > + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > }; > > &spfi1 { ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash 2020-08-15 16:35 [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Hauke Mehrtens 2020-08-15 16:35 ` [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN Hauke Mehrtens 2020-08-15 16:35 ` [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW Hauke Mehrtens @ 2020-09-03 20:40 ` Rahul Bedarkar 2 siblings, 0 replies; 8+ messages in thread From: Rahul Bedarkar @ 2020-09-03 20:40 UTC (permalink / raw) To: Hauke Mehrtens Cc: tsbogend, linux-mips, devicetree, robh+dt, james.hartley, wigyori On Sat, Aug 15, 2020 at 10:05 PM Hauke Mehrtens <hauke@hauke-m.de> wrote: > > Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree. > > The NAND flash chip is connected with quad SPI, but reading currently > fails in quad SPI mode. > I think dual RX and quad TX should work. https://github.com/CreatorDev/openwrt/blob/ci40/target/linux/pistachio/dts/pistachio/pistachio_marduk_common.dtsi#L203 > Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Rahul Bedarkar <rahulbedarkar89@gmail.com> > --- > arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts > index bf69da96dc8b..ea11a21b133b 100644 > --- a/arch/mips/boot/dts/img/pistachio_marduk.dts > +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts > @@ -88,6 +88,12 @@ > reg = <0>; > spi-max-frequency = <50000000>; > }; > + > + flash@1 { > + compatible = "spi-nand"; > + reg = <1>; > + spi-max-frequency = <50000000>; > + }; > }; > > &uart0 { > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-12 6:46 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-15 16:35 [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Hauke Mehrtens 2020-08-15 16:35 ` [PATCH 2/3] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN Hauke Mehrtens 2020-08-16 9:14 ` Sergei Shtylyov 2020-08-16 10:59 ` Hauke Mehrtens 2020-08-16 17:06 ` Sergei Shtylyov 2020-08-15 16:35 ` [PATCH 3/3] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW Hauke Mehrtens 2020-09-12 6:46 ` Zhou Yanjie 2020-09-03 20:40 ` [PATCH 1/3] MIPS: DTS: img: marduk: Add SPI NAND flash Rahul Bedarkar
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